JPS6273770A - Semiconductor device - Google Patents
Semiconductor deviceInfo
- Publication number
- JPS6273770A JPS6273770A JP21402585A JP21402585A JPS6273770A JP S6273770 A JPS6273770 A JP S6273770A JP 21402585 A JP21402585 A JP 21402585A JP 21402585 A JP21402585 A JP 21402585A JP S6273770 A JPS6273770 A JP S6273770A
- Authority
- JP
- Japan
- Prior art keywords
- layer
- insulating layer
- film
- insulating
- semiconductor device
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 239000004065 semiconductor Substances 0.000 title claims description 16
- 230000003287 optical effect Effects 0.000 claims abstract description 24
- 239000000758 substrate Substances 0.000 claims abstract description 13
- 239000010409 thin film Substances 0.000 claims abstract description 10
- 229910052710 silicon Inorganic materials 0.000 claims description 5
- 239000010703 silicon Substances 0.000 claims description 5
- IJGRMHOSHXDMSA-UHFFFAOYSA-N Atomic nitrogen Chemical compound N#N IJGRMHOSHXDMSA-UHFFFAOYSA-N 0.000 claims 2
- 239000002184 metal Substances 0.000 claims 1
- 229910052757 nitrogen Inorganic materials 0.000 claims 1
- 239000010408 film Substances 0.000 abstract description 35
- 229910021417 amorphous silicon Inorganic materials 0.000 abstract description 7
- 230000007423 decrease Effects 0.000 abstract description 4
- 239000000203 mixture Substances 0.000 abstract description 3
- 238000013459 approach Methods 0.000 abstract description 2
- 230000005684 electric field Effects 0.000 abstract 2
- 230000000630 rising effect Effects 0.000 abstract 1
- QGZKDVFQNNGYKY-UHFFFAOYSA-N Ammonia Chemical compound N QGZKDVFQNNGYKY-UHFFFAOYSA-N 0.000 description 10
- 230000005669 field effect Effects 0.000 description 8
- 239000011521 glass Substances 0.000 description 6
- 239000007789 gas Substances 0.000 description 5
- 238000001259 photo etching Methods 0.000 description 5
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 4
- 238000005268 plasma chemical vapour deposition Methods 0.000 description 4
- BLRPTPMANUNPDV-UHFFFAOYSA-N Silane Chemical compound [SiH4] BLRPTPMANUNPDV-UHFFFAOYSA-N 0.000 description 3
- 238000010586 diagram Methods 0.000 description 3
- 239000011159 matrix material Substances 0.000 description 3
- 229910000069 nitrogen hydride Inorganic materials 0.000 description 3
- 229910004205 SiNX Inorganic materials 0.000 description 2
- 229910021529 ammonia Inorganic materials 0.000 description 2
- 229910052681 coesite Inorganic materials 0.000 description 2
- 229910052906 cristobalite Inorganic materials 0.000 description 2
- 230000006866 deterioration Effects 0.000 description 2
- 238000004519 manufacturing process Methods 0.000 description 2
- 238000000034 method Methods 0.000 description 2
- 238000000059 patterning Methods 0.000 description 2
- 229910000077 silane Inorganic materials 0.000 description 2
- 239000000377 silicon dioxide Substances 0.000 description 2
- 235000012239 silicon dioxide Nutrition 0.000 description 2
- 229910052682 stishovite Inorganic materials 0.000 description 2
- 229910052905 tridymite Inorganic materials 0.000 description 2
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 description 1
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical group [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
- 239000011111 cardboard Substances 0.000 description 1
- VNNRSPGTAMTISX-UHFFFAOYSA-N chromium nickel Chemical compound [Cr].[Ni] VNNRSPGTAMTISX-UHFFFAOYSA-N 0.000 description 1
- 238000004140 cleaning Methods 0.000 description 1
- 238000000354 decomposition reaction Methods 0.000 description 1
- 238000000151 deposition Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 239000004973 liquid crystal related substance Substances 0.000 description 1
- 229910001120 nichrome Inorganic materials 0.000 description 1
- 229910052698 phosphorus Inorganic materials 0.000 description 1
- 239000011574 phosphorus Substances 0.000 description 1
- 230000001681 protective effect Effects 0.000 description 1
- 239000012495 reaction gas Substances 0.000 description 1
- 239000000126 substance Substances 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Ceramic Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Electrodes Of Semiconductors (AREA)
Abstract
Description
【発明の詳細な説明】
〔概 要〕
本発明は、半導体装置、特に薄膜トランジスタ（Ｔｈｉ
ｎ ｆｉｌｍ Ｔｒａｎｓｉｓｔｏｒ、以下ＴＰＴと記
す）のゲート絶縁膜を２層構造とし、絶縁層としてシリ
コンを主成分とするＳｉＮｘ等を形成し、ゲート電極側
の第１及び第２の絶縁層の光学ギヤ・ノブＥＩＥ２をＥ
＋ ＞Ｅ２の関係を選択して高速なスイッチング特性
が得られ、安定性の優れた薄膜トランジスタを提供する
ものである。[Detailed Description of the Invention] [Summary] The present invention relates to semiconductor devices, particularly thin film transistors (Thin Film Transistors).
The gate insulating film of the n film transistor (hereinafter referred to as TPT) has a two-layer structure, and the insulating layer is made of SiNx, etc. whose main component is silicon, and the optical gear of the first and second insulating layers on the gate electrode side is formed. Knob EIE2
By selecting the relationship +>E2, high-speed switching characteristics can be obtained and a thin film transistor with excellent stability can be provided.
本発明は半導体装置に係り、特に液晶表示装置用薄膜ト
ランジスタのゲート絶縁層を二重構造とした半導体装置
に関する。The present invention relates to a semiconductor device, and particularly to a semiconductor device in which a gate insulating layer of a thin film transistor for a liquid crystal display device has a double structure.
平面ディスプレイとしてＬ ＣＤ （Ｌｉｑｗｉｄｃｒ
ｙｓｔａｌ ｄｉｓｐｌａｙ）は表示容量が増加しかな
り大型の画素数を有するものが市販されている。この様
に大型化すると駆動時間と非駆動時間の比が小さくなり
、コントラスト比が低下し、視野角も狭くなる問題があ
り、これを解決するためにスイッチング素子としてのＴ
ＰＴをマトリックス配列してＬＣＤを直接駆動するアク
チブマトリックス表示によって画素に直接電圧を印加す
ることで高いコントラスト比のディスプレイが得られる
ノこめに広く利用されている。LCD (Liqwidcr) is used as a flat display.
ystal displays) with increased display capacity and a considerably large number of pixels are commercially available. As the size increases in this way, the ratio of driving time to non-driving time becomes smaller, the contrast ratio decreases, and the viewing angle becomes narrower.To solve this problem, T
Active matrix display, in which PTs are arranged in a matrix to directly drive an LCD, is widely used in applications where a display with a high contrast ratio can be obtained by applying voltage directly to the pixels.
この様なアクチブマトリックス表示にスイッチング素子
としてＴＰＴやダイオードが用いられている。特にＴＰ
Ｔは大面積化やガラス基板が使える等で多く研究されて
いる。特にゲート絶縁層に非晶質のアモルファスシリコ
ン（ａ−ｓｉ）膜が用いられているため高抵抗を呈り１
画素駆動時のスイッチングのオン・オフ比が大きく出来
る。TPTs and diodes are used as switching elements in such active matrix displays. Especially T.P.
T has been extensively researched because it has a large area and can use glass substrates. In particular, since an amorphous silicon (a-si) film is used for the gate insulating layer, it exhibits high resistance.
The on/off ratio of switching when driving pixels can be increased.
この様なａ−３ｉ（非晶質シリコン）ＴＰＴにはスタガ
ード形及び逆スタガード形構造があり。Such a-3i (amorphous silicon) TPT has a staggered structure and an inverted staggered structure.
第４図乃至第６図にこれら各構造を説明する。第４図は
ａ−３ｉＴＦＴの平面図、第５図は第４図のＡ−Ａ ′
断面図を示すスタガード形ＴＰＴ、第６図は逆スタガー
ド形の側断面図である。第４図に於いて４はドレイン電
極を示し、１画素分の電極となるもので第５図に示すよ
うにガラス等の透明基板上に透明導電膜を形成し、ドレ
イン電極、４とソース電極５をフォトエツチングにより
パターン形成し、これらパターン上に（ドレイン電極４
には第４図に示すようにごく一部にオーパラ・ノブして
）ａ−Ｓｔ膜２をプラズマＣＶＤ法で形成する。このａ
−３ｔ膜２をパターニングしてパターン形成し、同じ（
プラズマＣＶＤ法でゲート絶縁層３を形成し、このゲー
ト絶縁Ｎ３にゲート電極膜を形成してゲート電極６パタ
ーンをフォトエツチングで形成し、保護絶縁膜形成後に
ＬＣＤ作成工程に入る様になされている。Each of these structures will be explained in FIGS. 4 to 6. Fig. 4 is a plan view of the a-3i TFT, and Fig. 5 is the A-A' of Fig. 4.
A cross-sectional view of a staggered TPT is shown, and FIG. 6 is a side cross-sectional view of an inverted staggered TPT. In Fig. 4, 4 indicates a drain electrode, which serves as an electrode for one pixel.As shown in Fig. 5, a transparent conductive film is formed on a transparent substrate such as glass, and the drain electrode, 4, and source electrode are formed on a transparent substrate such as glass. 5 is patterned by photoetching, and on these patterns (drain electrode 4
Then, as shown in FIG. 4, an a-St film 2 is formed by a plasma CVD method (with an Opara knob in a small portion). This a
-3t film 2 is patterned to form a pattern, and the same (
A gate insulating layer 3 is formed by the plasma CVD method, a gate electrode film is formed on this gate insulating layer N3, and a gate electrode 6 pattern is formed by photoetching, and after the protective insulating film is formed, the LCD manufacturing process is started. .
第６図の場合は逆スタガード形のａ−３ｉＴＦＴでガラ
ス基ｉｔ上にゲート電極を形成し、ゲート絶縁層３をプ
ラズマＣＶＤ等で形成して、その上にａ−３ｉ膜をプラ
ズマＣＶＤで形成してフォトエツチングでパターニング
し、ソース、ドレイン電極をパターニングしている。こ
れら逆スタガード及びスタガード形はそれぞれ一長一短
があり。In the case of Fig. 6, a gate electrode is formed on the glass substrate IT using an inverted staggered a-3i TFT, a gate insulating layer 3 is formed by plasma CVD, etc., and an a-3i film is formed on it by plasma CVD. Then, the source and drain electrodes are patterned by photoetching. These reverse staggered and staggered types each have their advantages and disadvantages.
逆スタガード形ではゲート絶縁膜と活性層のａ −３ｉ
膜を連続的に形成出来るし、スタガード形では活性層の
ａ−３ｉ膜がゲーＩ・絶縁膜で保護されていて信頼性が
高い特徴を有している。In the inverted staggered type, the a-3i of the gate insulating film and active layer
The film can be formed continuously, and in the staggered type, the a-3i film of the active layer is protected by a GaI insulating film, which has the feature of high reliability.
この様にゲート絶縁膜が一部からなるスタガード形式あ
るいは逆スタガード形ａ−３ｉＴＦＴではゲートストレ
ス印加後に闇値がシフトすると云う問題があった。As described above, the staggered type or reverse staggered type a-3i TFT in which the gate insulating film is partially formed has a problem in that the dark value shifts after gate stress is applied.
この様な闇値シフトを減少させようと４″るとａ−３ｉ
の電界効果移動度Ａｌ Ｏｆｆ （ｃＪ ／ ｖ 、
５ｅｃ）が低下し、ＴＰＴのスイッチング特性の低下を
招く欠点があった。即ち、第７図にゲート電圧ＶＧとド
レイン電流ＩＤとの特性曲線７を示すがゲートストレス
印加後加後の特性曲線は７ａに示す様にシフトする。In order to reduce such a dark value shift, 4'' and a-3i
The field effect mobility of Al Off (cJ/v,
5ec), which resulted in a disadvantage that the switching characteristics of the TPT deteriorated. That is, FIG. 7 shows a characteristic curve 7 of gate voltage VG and drain current ID, and after application of gate stress, the characteristic curve shifts as shown in 7a.
本発明は上記した欠点に渇みなされたものでその目的は
ゲート絶縁膜を二層構造とし、ゲート雪掻側の第１の絶
縁層と、この第１層上に形成した第２の絶縁層のそれぞ
れの光学ギャップＥｌ、Ｅ２をＥｌ＞Ｅｚとなるように
することで闇値シフトが少く、電界効果移動度の低下し
ない立上り特性の優れた高速なａ−３ｉＴＦＴを得んと
するものでその手段はスタガード形又は逆スタガード形
薄膜トランジスタのゲート電極と非晶質活性層間に第１
及び第２の絶縁層を形成してなることを特徴とする半導
体装置によって達成される。The present invention has been made to solve the above-mentioned drawbacks, and its purpose is to provide a gate insulating film with a two-layer structure: a first insulating layer on the gate side, and a second insulating layer formed on the first layer. By setting the respective optical gaps El and E2 such that El>Ez, we aim to obtain a high-speed a-3i TFT with small dark value shift and excellent rise characteristics without deterioration of field effect mobility. The means includes a first electrode between the gate electrode and the amorphous active layer of the staggered or reverse staggered thin film transistor.
This is achieved by a semiconductor device characterized by forming a second insulating layer.
本発明のＴＰＴの一つは基板上に予めゲート電極を形成
し、このゲート電極上に光学ギャップＥ１の第１の絶縁
層を形成するが、該第１の絶縁層のバンドギャップ中に
捕獲準位が存在し、この捕獲準位の深さと光学ギャップ
Ｅ１との間には相関関係があり、光学ギャップＥ１がａ
−３ｉの光学ギャップＥｇに近いほど蓄積電子が捕獲さ
れ、そのためにＴＰＴ特性に於いて闇値シフトを生ずる
。In one of the TPTs of the present invention, a gate electrode is formed in advance on a substrate, and a first insulating layer with an optical gap E1 is formed on this gate electrode. There is a correlation between the depth of this trap level and the optical gap E1, and the optical gap E1 is a
The closer the optical gap Eg of -3i is, the more accumulated electrons are captured, which causes a dark value shift in the TPT characteristics.
従ってＥｌ＞Ｅｇとなるように第１層の絶縁層を形成す
る。ところが第１の絶縁層の光学ギャップＥ１が大きく
なってストイキオメトリ （ｓｔｏｉｃｈｅ−ｏｍｅ
ｔｒｙ）と云われる化学口論的組成に近づくと絶縁層／
ａ −Ｓ ｉ膜の活性層中にストレスが掛り表面準位
が形成されるために電界効果移動度の低下を招く、そこ
で第２の絶縁層の光学ギャップＥ２をＥｌ＞Ｅｚ＞Ｅｇ
となる様に選択し１活性層のａ−３ｉ膜との整合性を改
善するようにしたａ −３ｔＴＦＴを提供するものであ
る。Therefore, the first insulating layer is formed so that El>Eg. However, the optical gap E1 of the first insulating layer becomes large and the stoichiometry
When approaching a chemical composition called try), the insulating layer/
Stress is applied to the active layer of the a-Si film and surface states are formed, leading to a decrease in field effect mobility.Therefore, the optical gap E2 of the second insulating layer is set as El>Ez>Eg.
The purpose of the present invention is to provide an a-3t TFT which is selected so as to improve the compatibility with the a-3i film of one active layer.
以下２本発明の一実施例を＠ｉ図について詳記する。 Two embodiments of the present invention will be described in detail below with reference to the @i diagram.
第１図は逆スタガード形ａ−３ｉＴＦＴを示すもので先
ず絶縁性の基板としてはガラス基板１を洗浄しゲート電
極膜としてＣｒ、 ΔＬＭｏ。FIG. 1 shows an inverted staggered a-3i TFT. First, a glass substrate 1 as an insulating substrate is cleaned, and a gate electrode film is made of Cr or ΔLMo.
ＮｉＣ４の膜を形成し、レジストマスクを用いてフォト
エツチング等でゲート電極パターンを形成しゲート電極
６を得る。A NiC4 film is formed, and a gate electrode pattern is formed by photoetching or the like using a resist mask to obtain the gate electrode 6.
次にゲート電極６の形成された絶縁性の基板１の上にシ
ラン（ＳｔＨａ）とアンモニア（ＮＨ３）の混合ガスを
用いてグロー放電で分解して第１の絶縁層であるゲート
酸化膜３を形成する。Next, a gate oxide film 3, which is a first insulating layer, is formed on the insulating substrate 1 on which the gate electrode 6 is formed by using a mixed gas of silane (StHa) and ammonia (NH3) and decomposing it by glow discharge. Form.
上記したゲート酸化膜３はＳｉＮｘであるがＳｉＯ２、
ＳｉＣ，５ｉＯＮ、 Ａ ｅ ２０３等でもよ（。The gate oxide film 3 described above is SiNx, but SiO2,
Even SiC, 5iON, Ae 203, etc. (.
ＳｉＯ２の場合は５ｔ）ｌａと０２の混合ガスをそれぞ
れグロー放電で分解する。このときの第１の絶縁層（Ｓ
ｉＮ ｘ ）の光学ギャップＥ１となる様に形成する。In the case of SiO2, 5t) The mixed gases of la and 02 are each decomposed by glow discharge. At this time, the first insulating layer (S
iN x ) to form an optical gap E1.
この条件としては基板１の温度２００°〜３００℃。As for this condition, the temperature of the substrate 1 is 200° to 300°C.
Ｎ Ｈｖ ／ ＳｉＨａの反応ガス圧０．１〜１０Ｔｏ
ｒｒ 、 ｒ４パワー０．０２〜０．３ Ｗ／ ｃ
ｉ 、ガス流量比Ｎ Ｈ１／ Ｓ Ｈ４＝ １〜４が
好ましい。この時の第１の絶縁層の光学ギャップＥ１は
成膜条件を変えることによりＥ１＝３〜７ｅｖとなる。N Hv / SiHa reaction gas pressure 0.1-10To
rr, r4 power 0.02~0.3 W/c
i, gas flow ratio N H1/S H4 = 1 to 4 is preferred. At this time, the optical gap E1 of the first insulating layer becomes E1=3 to 7ev by changing the film forming conditions.
次に真空状態を破ることなく、連続して第２の絶縁層８
を形成する。第２の絶縁層８の光学ギャップＥ２はＥｌ
＜Ｅｚの関係になるように前記成膜条件を変えて選択す
る。この時の光学ギャップとしては２＜Ｅｚ＜５ｅｖ程
度に選択するを可とする。これら第１及び第２の絶縁層
３．８の形成後に引き続いてａ−３ｉ膜２を活性層とし
て堆積させる。Next, the second insulating layer 8 is continuously applied without breaking the vacuum state.
form. The optical gap E2 of the second insulating layer 8 is El
The film forming conditions are changed and selected so as to satisfy the relationship <Ez. The optical gap at this time can be selected to be approximately 2<Ez<5ev. After the formation of these first and second insulating layers 3.8, an a-3i film 2 is subsequently deposited as an active layer.
これは５ｉＩ（ａガスをグロー放電で分解して堆積させ
る。ａ−３ｉ膜をフォトエツチング等でバターニングし
た後で、ソース、ドレイン電極レジストパターン形成後
にリンをドープしたａ−Ｓｉ膜ｎ＋ａ−３に膜９をグロ
ー放電分解法で形成し、更にソース及びドレイン電極４
，５をバターニングする。ソース及びドレインにはＡ！
！、Ｔｉ、Ｃｒ又ＮｉＣｒが用いられる。This is deposited by decomposing 5iI (a gas by glow discharge. After patterning the a-3i film by photoetching etc., and forming a resist pattern for the source and drain electrodes, an a-Si film n+a-3 doped with phosphorus is formed. A film 9 is formed by a glow discharge decomposition method, and a source and drain electrode 4 is further formed.
, 5 is buttered. A for source and drain!
! , Ti, Cr or NiCr are used.
第２図にａ −Ｓ ｉ Ｔ Ｆ Ｔの閾値電圧シフト及
び電界効果移動度μｅ ｉ（の第１の絶縁層ＳｉＮ ｘ
依存性を示す。同図で縦軸左側は、ゲート電圧■ ＝３
０ｖ、ドレイン電圧■。−５Ｖを印加して１分印加後の
ゲートスト
側は電界効果移動度ｐ ｅ ｆｆ （ｃｌｌｌ，／ Ｖ
， ｓｅｅ））を示すものであり．横軸ばＮＨ３／Ｓｉ
Ｈａを示している。先ず従来の第１の絶縁層であるゲー
ト絶縁層３だけの場合のμｅｆｆの変化は特性曲線１０
に示す様に大きく変化するが２層構造とすると特性曲線
１１に示すようにその変化は少ない。特性曲線にはΔ■
を示すものである。第１の絶縁層３の光学ギャップをＥ
ｌ−３〜７ｃｖに選択したとき。FIG. 2 shows the threshold voltage shift and field effect mobility μe i (of the first insulating layer SiN x
Show dependencies. In the same figure, the left side of the vertical axis is the gate voltage ■ = 3
0v, drain voltage ■. After applying −5 V for 1 minute, the field effect mobility p e ff (clll, / V
, see)). Horizontal axis: NH3/Si
It shows Ha. First, the change in μeff in the case of only the gate insulating layer 3, which is the conventional first insulating layer, is shown by characteristic curve 10.
As shown in the characteristic curve 11, there is a large change, but in the case of a two-layer structure, the change is small as shown in the characteristic curve 11. The characteristic curve has Δ■
This shows that. The optical gap of the first insulating layer 3 is E
When selecting l-3 to 7cv.
この絶縁層にはバンドギャップ中に捕獲準位が存在し、
この捕獲準位の深さと光学ギャップＥ１には相関があっ
て、光学ギャップＥ１がａ−３ｉの光学ギヤノブＥｇに
近いほど蓄積電子が捕獲され。This insulating layer has a trap level in the band gap,
There is a correlation between the depth of this capture level and the optical gap E1, and the closer the optical gap E1 is to the optical gear knob Eg of a-3i, the more accumulated electrons are captured.
ＴＰＴ特性に於いて闇値がシフトする。よって第１の絶
縁層３の光学ギャップＥ１をＥ＋＞Ｅｇとなる様に選択
する。然し第１の絶縁層３の光学ギヤノブＥ１が大きく
なり、化学量論的組成の膜に近づくと絶縁層／ ａ−３
ｉ活性Ｎ３中にス１〜レスが加わって表面準位が形成さ
れ電界効果移動度μｅｆｆが低下する。故に第１の絶縁
層３の上に第２の絶縁層をシラン（ＳｉＨ４）とアンモ
ニア（Ｎ Ｈ３）との混合ガスを用いて光学ギヤ、プＥ
。Darkness value shifts in TPT characteristics. Therefore, the optical gap E1 of the first insulating layer 3 is selected so that E+>Eg. However, as the optical gear knob E1 of the first insulating layer 3 becomes larger and approaches a film with a stoichiometric composition, the insulating layer/a-3
Stresses 1 to Stress are added to the i-active N3 to form surface states, and the field effect mobility μeff is reduced. Therefore, a second insulating layer is formed on the first insulating layer 3 using a mixed gas of silane (SiH4) and ammonia (NH3) to form an optical gear.
.
となる様に、即ちＥ １＞ Ｅ ２ ＞ Ｅ ｇに選択
することで第２Ｎはａ Ｓｔ膜の活性Ｎ２との整合性
が改善されて第２図特性曲線１１の様に電界効果移動度
μｅｆｆば低下せず、スインチング特性が高速なａ−３
ｉ ＴＦＴを得ることが可能となる。In other words, by selecting E 1 > E 2 > E g, the consistency of the second N with the active N2 of the a St film is improved, and the field effect mobility μeff is increased as shown in the characteristic curve 11 in Figure 2. a-3, which has high speed switching characteristics without any deterioration
i TFT can be obtained.
第３図は本発明を第５図に示したスタガード形ａ−３ｉ
ＴＦＴに通用した側断面図を示すものでガラス基板１の
洗浄、透明導電薄の蒸着、ドレ・イン、ソース雪掻しジ
ストパターン形成後、リンドープミー８ｉ膜（ｎ＋ａ−
３ｉ）９とソース、１゛レイン電極５，６を形成し、プ
ラズマＣ，Ｖ Ｄでａ−５ｉ膜形成して次に真空を破る
ことなく連続して更に第１及び第２の絶縁層３．８を形
成後にゲー・上電極６をパターン形成してスタガード形
ａ−３ｉＴＦＴが形成される。Figure 3 shows the staggered type a-3i shown in Figure 5.
This is a side cross-sectional view commonly used for TFTs. After cleaning the glass substrate 1, depositing a transparent conductive thin film, forming drain/in, and source snow removal resist patterns, a phosphorous-doped 8i film (n+a-
3i) Form 9, source and 1' rain electrodes 5 and 6, form an a-5i film with plasma C and VD, and then continuously form the first and second insulating layers 3 without breaking the vacuum. After forming the gate electrode 6, a staggered type a-3i TFT is formed by patterning the gate electrode 6.
本発明は以上の如く構成させたのでゲーＩ−ストレス印
加後の闇値シフトを減少させることが出来ａ−３ｉ電界
効果移動度も低下しないａ−８ｉＴＰＴが提供出来る。Since the present invention is constructed as described above, it is possible to provide an a-8i TPT that can reduce the dark value shift after application of the GeI stress and that does not reduce the a-3i field effect mobility.
第１図は本発明のａ−３ｉＴＦＴ（逆スタガード形〕の
側断面図。
第２図はａ−３ｉＴＦＴ特性のゲート絶縁膜依存性を示
す特性図。
第３図は本発明のａ−３ｉＴＦＴ［逆スタガード形〕
第４図は従来のａ−３ｉＴＦＴ平面図。
第５図は第４図のΔ−Ａ断面図。
第６図は従来のａ−３ｉ Ｔ Ｆ Ｔ側断面図〔スタガ
ード形〕
第７図はａ−３ｉ ＴＦＴのＶＣ−ＩＤ特性図である。
■ ・ ・ ・ 基１反
２・・・ａ Ｓｉ膜
３・・・ゲート絶縁層（第１絶縁層）
４・・・ドレイン電極
５・・・ソース電極
６・・・ゲート電極
８・・・第２の絶縁層
９・・・ｎ＋ａ−３ｉ膜
本沁ＮＡ ｑθ−５ｉＴＦ７”イ仰］書生面図（七しス
ダヵード形）第１図
；
ａ−５ｉＴＰＴＭ性の作−トぜ９噂」央イ六Ｊ覧性第２
図
お応門め０−５ｉＴＦＴ４則嶋−面図（スダカ゛−ド躬
）第３図
ａ−９ｉＴＦＴ ４ｆｆｉ７
第４図
５ソース電極
、ｌ−Ａ’町面図 （ズダカ“−ド升う）第５図Fig. 1 is a side sectional view of the a-3i TFT (inverted staggered type) of the present invention. Fig. 2 is a characteristic diagram showing the dependence of the a-3i TFT characteristics on the gate insulating film. Fig. 3 is the a-3i TFT of the present invention [ [Reverse staggered type] Fig. 4 is a plan view of a conventional a-3i TFT. Fig. 5 is a sectional view taken along the Δ-A line in Fig. 4. Fig. 6 is a sectional view of the conventional a-3i TFT [staggered type] Fig. 7 is a VC-ID characteristic diagram of the a-3i TFT. ...Source electrode 6...Gate electrode 8...Second insulating layer 9...n+a-3i film qθ-5iTF7'' illustration] Draft surface view (seven card shape) Fig. 1 ; a-5iTPTM Sex Works - Toze 9 Rumors” Central Iroku J View Part 2
Figure 0-5 iTFT 4 Norishima - Side view (Sudaka card board) Figure 3 a-9i TFT 4ffi7 Figure 4 figure
Claims (7)
タのゲート電極と非晶質活性層間に第１及び第２の絶縁
層を形成してなることを特徴とする半導体装置。(1) A semiconductor device characterized in that first and second insulating layers are formed between a gate electrode and an amorphous active layer of a staggered or inverted staggered thin film transistor.
ンを主成分とする第１の絶縁層と第２の絶縁層を形成し
、活性層を含む非晶質半導体層形成後はソース・ドレイ
ン電極を形成してなるスタガード形薄膜トランジスタよ
りなることを特徴とする特許請求の範囲第１項記載の半
導体装置。(2) A first insulating layer and a second insulating layer containing silicon as a main component are formed on the gate electrode formed on the insulating substrate, and after forming an amorphous semiconductor layer including an active layer, a source/drain layer is formed. 2. The semiconductor device according to claim 1, comprising a staggered thin film transistor formed with electrodes.
電極上に活性層を含む非晶質半導体層形成後にシリコン
を主成分とする第１及び第２の絶縁層を形成してゲート
電極を形成してなる逆スタガード形薄膜トランジスタよ
りなることを特徴とする特許請求の範囲第１項記載の半
導体装置。(3) After forming an amorphous semiconductor layer including an active layer on the source and drain electrodes formed on the insulating substrate, first and second insulating layers containing silicon as a main component are formed to form a gate electrode. 2. The semiconductor device according to claim 1, comprising an inverted staggered thin film transistor.
２の絶縁層の光学ギャップをＥ＿２としたときＥ＿１＞
Ｅ＿２の関係を満たす絶縁層であることを特徴とする特
許請求の範囲第１項記載の半導体装置。(4) When the optical gap of the first insulating layer is E_1 and the optical gap of the second insulating layer is E_2, E_1>
The semiconductor device according to claim 1, characterized in that the insulating layer satisfies the relationship E_2.
含むことを特徴とする特許請求の範囲第１項記載の半導
体装置。(5) The semiconductor device according to claim 1, wherein the insulating layer is mainly composed of silicon and contains nitrogen (N).
てドナーとなる非晶質半導体層を形成してなる事を特徴
とする特許請求の範囲第１項記載の半導体装置。(6) The semiconductor device according to claim 1, wherein an amorphous semiconductor layer containing silicon as a main component and serving as a donor is formed on the upper surface of the amorphous active layer.
イン電極用レジスト・パターンを用いてソース・ドレイ
ン電極を形成してなることを特徴とする特許請求の範囲
第７項記載の半導体装置。(7) A semiconductor device according to claim 7, wherein source/drain electrodes are formed from the amorphous semiconductor layer and the metal layer using a resist pattern for source/drain electrodes. .
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP60214025A JPH084143B2 (en) | 1985-09-27 | 1985-09-27 | Semiconductor device and manufacturing method thereof |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP60214025A JPH084143B2 (en) | 1985-09-27 | 1985-09-27 | Semiconductor device and manufacturing method thereof |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS6273770A true JPS6273770A (en) | 1987-04-04 |
| JPH084143B2 JPH084143B2 (en) | 1996-01-17 |
Family
ID=16649026
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP60214025A Expired - Fee Related JPH084143B2 (en) | 1985-09-27 | 1985-09-27 | Semiconductor device and manufacturing method thereof |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH084143B2 (en) |
Cited By (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH01268060A (en) * | 1988-04-20 | 1989-10-25 | Fujitsu Ltd | Thin film transistor |
| US4951113A (en) * | 1988-11-07 | 1990-08-21 | Xerox Corporation | Simultaneously deposited thin film CMOS TFTs and their method of fabrication |
| US5041888A (en) * | 1989-09-18 | 1991-08-20 | General Electric Company | Insulator structure for amorphous silicon thin-film transistors |
| US5065202A (en) * | 1988-02-26 | 1991-11-12 | Seikosha Co., Ltd. | Amorphous silicon thin film transistor array substrate and method for producing the same |
| US5221631A (en) * | 1989-02-17 | 1993-06-22 | International Business Machines Corporation | Method of fabricating a thin film transistor having a silicon carbide buffer layer |
| US5320973A (en) * | 1986-07-11 | 1994-06-14 | Fuji Xerox Co., Ltd. | Method of fabricating a thin-film transistor and wiring matrix device |
Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS58182270A (en) * | 1982-04-16 | 1983-10-25 | Sanyo Electric Co Ltd | Manufacture of transistor |
-
1985
- 1985-09-27 JP JP60214025A patent/JPH084143B2/en not_active Expired - Fee Related
Patent Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS58182270A (en) * | 1982-04-16 | 1983-10-25 | Sanyo Electric Co Ltd | Manufacture of transistor |
Cited By (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5320973A (en) * | 1986-07-11 | 1994-06-14 | Fuji Xerox Co., Ltd. | Method of fabricating a thin-film transistor and wiring matrix device |
| US5065202A (en) * | 1988-02-26 | 1991-11-12 | Seikosha Co., Ltd. | Amorphous silicon thin film transistor array substrate and method for producing the same |
| JPH01268060A (en) * | 1988-04-20 | 1989-10-25 | Fujitsu Ltd | Thin film transistor |
| US4951113A (en) * | 1988-11-07 | 1990-08-21 | Xerox Corporation | Simultaneously deposited thin film CMOS TFTs and their method of fabrication |
| US5221631A (en) * | 1989-02-17 | 1993-06-22 | International Business Machines Corporation | Method of fabricating a thin film transistor having a silicon carbide buffer layer |
| US5041888A (en) * | 1989-09-18 | 1991-08-20 | General Electric Company | Insulator structure for amorphous silicon thin-film transistors |
Also Published As
| Publication number | Publication date |
|---|---|
| JPH084143B2 (en) | 1996-01-17 |
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