JPS6273659A - Manufacture of thin-film transistor device - Google Patents

Abstract

PURPOSE:To load both a first TFT and a second TFT in a consolidated manner by the small number of processes by forming openings for contacts to required sections in source and drain electrode sections and a first gate electrode for first and second transistors. CONSTITUTION:A first gate electrode 11 for a first TFT is shaped, a first gate insulating film 2 and an a-Si film 3 are deposited continuously, and the a-Si film 3 for a second TFT section is annealed by beams. Source 24, 25 and drain electrodes 124, 125 for the first and second TFTs are formed by N<+> a-Si films 4 and high melting-point metals 5, and the source and drain electrodes for the second TFT are annealed by means to shape a-Si and the Si films in the first and second TFTs to an insulator region. A second insulating film 6 is deposited, contact openings are bored to required sections, and a gate electrode for at least the second TFT is shaped by a metallic film. Accordingly, the inverted-stagger type a-Si TFT and the beam-annealed TFT can be formed through a simple process.

Description

DETAILED DESCRIPTION OF THE INVENTION <Industrial Application Field> The present invention provides a method for manufacturing amorphous silicon (A-81) on the same insulating substrate.
) A method of molding a TPT device having a thin film transistor (TPT) and a TPT with an energy beam annealed 7J191 thin film.

<Summary of the invention> First TPT with K a -3j on an insulating substrate and second TFτ with beam annealing and 7'e i9 i &ζ
(1) 11 of the j-th TFT
Formation of gate electrode (2) First gate insulating film, a-81
t3) A-81i beam annealing of the second TpT section (4) Na-8i film, high melting point metal source of the first and second TPT. Complete drain electrode formation (5) 2nd
TPT source and drain electrode gold beam annealing (6
) Form Ml, a-131 and S1 films of the second TPT in the island region (7) Deposit the second gate insulating film (8)
Contact opening (9) At least the second TP with gold vA film
The process consists of forming a gate electrode of T. Reverse stagger, -
Type a-81T F T beam annealed TFT can be formed in one simple step.

<Conventional technology> A-31TPT is a large-surface removable substrate that can be easily fabricated at low temperatures.
It is being used for night crystal display devices. But career change! Since 1111 is low, there is a limit to high-speed operation, and a-
131'l'FT matrix? It is difficult to incorporate driving peripheral circuits on the same board using the A-81TPT.

One way to increase the speed of a-81TPT is to beam-anneal the a-81 film with a laser or the like.
There are problems with the following points when integrating with 1TXPT. +
11 a-BIT F'r is easy to create an inverted stagger type with the gate electrode on the bottom (substrate side), but during beam annealing, considerations such as reflection from the bottom gate electrode, heat dissipation, etc.
It tends to be uneven. (2) Na-8i, etc., used as part of the source and drain electrodes have a relatively high resistance; Not used as part of a pole. (3) There is a method of na-β1t-beam annealing that alleviates the problem in (2), but since the source and drain electrodes of a-11TPT are usually two layers of na-81 metal, the process There is a compatibility issue. <4') Combined with the problem in (3), the number of masks becomes 7 to 8, which is a large number. (5) If low melting point glass is used for the substrate, cracks etc. will occur in the substrate during beam annealing of the S1 film directly above it.

<Problem to be solved by the invention> Tsukasa Honmi was made to solve one problem on the board, and both the reverse stagger WSL-8L TPT (91T FT) and the beam annealed TFT (second TPT) are low in money. It provides all manufacturing methods that can be mixed in the number of steps.

<Tth means for solving the problem> Formation of a first gate electrode on the tth TFT l''i insulating substrate, deposition of the first gate insulating film 5a-8i, na-81 layer, gold i
[Formation of source and drain electrodes using K, selective etching of the ^-81 film, deposition of second insulating film, and contact opening.

It is made by the process of forming gold 4 wiring. On the other hand, the second 'r
lP'r is the process of interposing the first gate insulating film between -IJs- temporary and crystallizing the a-8i film by beam annealing, and the process of crystallizing the a-8i film by interposing the first gate insulating film between -IJs-temporary and the source/drain, IE electrode type Iy, rear metal film and na -81 The film is formed simultaneously with the first TPT, including a step of full beam annealing, a step of providing a gate electrode during the final metal wiring formation, and a step of using the second insulating film as the gate insulating film. The second insulating film ri is also used as a gate insulating film on the front surface side of the first TPT, and a second gate electrode on the front surface side is provided at the time of forming the gold.1<. marking line.

Effect> The first gate insulating film is interposed between the substrate and the a-8i film,
8i, beam annealing is effective when the two substrates are low melting point glasses. Damage to the ERI substrate due to heat dissipation from the melted 9A-8T film can be completely prevented, and it is effective if the thickness of the first gate insulating film is three times or more that of the A-8I film. Beam annealing of the na-8i film metal film 2-no film can diffuse the impurities in the na-8111% into the st Vx below and crystallize the Kna-81 film to lower the resistance. On the other hand, the metal film is less than 1uuo℃.
It is necessary that the metal be a high melting point metal. However, it is desirable to prevent the NA-81 film from melting during beam annealing so that impurity diffusion does not occur more than necessary. Second
By providing the gate electrode, the first TPT can be made into a dual-gate type, and it is now possible to increase the driving ability and obtain a continuous light effect. .

Example More drawings? The present invention will be described in detail using the following.

a. Example 1. Manufacturing process (Fig. 1) Fig. 1 shows a-8j, T P T (TF
TI ) and T with beam annealed TFT (TFT2)
It is a 9-U surface view along the manufacturing process of a PT device. 11)
J(a) is glass, quartz. Insulating film coated
The first gate electrode 11 is entirely formed on an insulating substrate 1 such as the like, and has nine cross sections. The first gate electrode 11 is made of Cr, Mo.

Derivatives such as W, Ta, ITO, etc. are used.

Figure 1(b) shows that the first gate is dead! ! Film 2, a high-resistance semiconductor IT film (e.g. A-8I film) 5t is successively deposited, and the TFT
A-31giJ3f beam annealing is performed on the portion 2 to crystallize it, forming a solid second channel region 115, which is in a solid state. FiSiOx, 8j, Nx on the first gate insulation 2
The smell etc. is i ft-a -81 membrane 13 is a-8i i
H'p a-811F alloy is used and plasma C
Deposited by VD or photo-CVD, for example 20uO ~
It has a thickness of 5ouo^, sou~2uσ. In the beam annealing, scanning annealing using a laser beam or an electron beam is used to melt and recrystallize the a-8i metal. If necessary, a small amount of B or the like is added to the a-8i film 3 in advance, or ions are implanted before or after beam annealing.

Figure 1(c) shows a low-resistance semiconductor layer such as an NA-81 film.
4 and a high melting point metal film 5 were successively deposited, and selective continuous etching was performed to form 14° 114 between the source regions of TFTs 1 and 2, drain regions 15 and 115, source electrodes 24 and 124, and drain electrodes 25 and 125'i. It weighs 7 tons. Furthermore, the source region electrodes 114, 124 and the drain region' poles 115, 125 of TFT2 are beam annealed, and
Impurities in the a-Eli film 4 form the second channel region 115.
It has been selectively diffused within. The na-3i film 4 contains P and As.
N-type non-containers such as are added. The high melting point metal film 5 is
Cr, Mo.

W, Ta, Ti, etc., all of which have melting points of 10UU°C or higher, are used. Beam annealing was performed on gold@films 5 and n
This is done to such an extent that a-B i Q 4 does not dissolve, thereby preventing impurities from diffusing more than necessary and suppressing unnecessary reactions.

For the selective formation of each source/drain region '1, a technique such as a lift-off method can be used in addition to continuous etching, but this will be omitted. g1 figure (d) ld, TF'l'1 and 2
The remaining &-81 film or the crystal S1 film is selectively etched to form the ye'M plane. 41(a) a, after depositing the second gate pattern 6, contact openings are formed in safe areas, and the second gate electrode 117, source contacts 954, 154 of TFT1 and 2 are formed by selective etching of the entire metal film deposition. ．．
Drain wiring 1935, 135 etc. are made of gold and completed to show nine-state gold.

The second gate insulating film 6 can be made of Japanese cedar, facing the first gate insulating film 2, and the metal film is made of mirror, Al/high melting point metal, or the like. The above process can be carried out by performing the mask process in the main manufacturing process.

b. Example Z Liquid crystal display screen] Manufacturing process (Figure 2) No. 2
1'21 i'! 214(a) shows the manufacturing process sequence of applying the present invention to the TPT base plate for liquid crystal display. At the same time as the example of FIG. - After deposition of 8i film 5, TPT2
Beam annealing the part, and further n a-3i J
, high melting point gold fii EJK engineering fl, TFTl and 2 source regions 14, 114, source' = JtJ 24° 124
S drain region 15, 115, drain electrode 25, 1
25 was formed. FIG. 2(c) shows TlT1
Following the selective etching to shallow the a-8ilpJ3 and stgrts of 2, the first gate resistor 2 is also etched in the same shape by dry etching, etc., resulting in a T-shaped pattern.

This Vc makes it easier to form contact holes on the Cτ 1 gate electrode 11 and the pixel II electrode 6 in the next step. 211(d) deposits a K2 gate insulating film 6, provides a contact hole, and forms the gold 4 film to connect the source wiring 35, etc. to the second gate'1 pole 117 of TPT2, the pixel electrode 16 of TFTl, etc. ? The setup is elaborate. At the same time, an electrode 21 made of four gold films can be provided on the TPTI channel region 3, and in addition to functioning as a single-light film,
By connecting the first gate electrode 11 with the first gate electrode 11, it can be used as the F surface dividing gate 1, etc.

First gate electrode 11 and pixel: All examples shown in which the electrode 16 is provided only with a transparent conductive film can be made into a 21 film with a gold film, and the gold film on the pixel electrode 16 is shown in FIG. It can be removed in state (c).

C0 example construction Liquid crystal display device structure (Fig. 5) Fig. 5 shows the structure of a liquid crystal display device using the manufacturing method of the present invention. This is an example of a nine-sided structure of a board. First TFTlVi, a-8
It is used as an II element switch having 1[3't, and has 16 1i4i element 1 poles with a transparent conductive film Kj on the first gate insulating film 2. The second TPT2 is beam annealed and
1 film 113, drain electrode 25 of 'I'F'll
drain connected to; source auxiliary arrangement 144'i having a pole 125 and formed simultaneously with the pixel electrode 16;
I'm growing up. As in this example, the wiring between the sources or drains of TFTs 1 and 2 is of na-8
I sniff and its beam annealing is nine Si! 'i Transparent conductive μ that can be used in part and used for the pixel electrode 16
A history can be traced to the wiring of Ryomoike. d. Actual power example 4. Liquid crystal display f structure (Fig. 4) Fig. 4 is a cross section of the 'rFT substrate for a night crystal display device using the same sickle as in Fig. 3, and connects the first gate electrode 11 of TFTl and the drain electrode 125 of TPT2. This is nine examples. In this example, TFTl
A surface gate electrode 21 is provided and short-circuited with the first gate 'r4 pole 11, and is formed simultaneously with the 'rF'r2 drain electrode 125 and the pixel electrode 16, and is short-circuited via a drain auxiliary wiring 145. However, the second gate insulating film 6 on the pixel electrode 16 is removed at the contact opening factory.

<Effects of Square Steel> As described above, according to the present invention, it is possible to easily mount the inverted staggered foil 1'r F T, which is optimal for a-8iTFTK, and the second TPT, which is easy to beam annealing. The flat resistive semiconductor layer formed in each TFTQ) channel region and the low-resistance semiconductor layer in the source and drain regions, as well as the four high-melting films on both regions, can be formed at the same time. There are few advantages. The first gate insulating film also serves as a plaster film between the semiconductor film and the substrate during beam annealing.

^-81 film based on the present invention as the first TPT? Although we have described an example of use, another application is possible for polycrystalline S1 films and other semi-2s materials. Ma7jn channel TPT as well as P
This also applies to channels.

[Brief explanation of drawings]

Figures 1(a) to (e) show the actual manufacturing method of the present invention.
A sectional view of the container along four examples. Figure 2 (→~(d) is a cross section of 7 according to an embodiment of another manufacturing method. Figures 5 and 4 show that the present invention has a T F' T device using the manufacturing method. This is a cross-sectional diagram for example. 1...Substrate 2...First gate insulating film 5...A-31 sliding door 4- = na-8i 1lA 5. ...High melting point gold mold 6...Second gate insulation pattern 11...First gate electrode 3.115...Channel region 14,114.
...Source region 15.115...Drain region 24.124.
...Source electrode 25.125...Drain 1 rod 117...
...Second gate' electrode 21...Surface 1 electrode 16...Pixel electrode and above The present invention (according to the TFT device manufacturing process) Manufacturing process 1 Presentation 1 Town plan Figure 2 Figure 3 Figure 7 Manufacturing method according to the present invention and IC TPT device used Figure 4

Claims (4)

[Claims] (1) In manufacturing a thin film transistor device having at least a first thin film transistor and a second thin film transistor on an insulating substrate, (a) a first step of forming a first gate electrode of the first transistor on the substrate; (b) a second step of successively depositing a first gate insulating film and a high resistance semiconductor thin film; (c) a third step of annealing at least the second transistor portion of the high resistance thin film with an energy beam; and (d) a third step of annealing the first and high resistance semiconductor thin films. A fourth step (e) of selectively forming the source and drain electrodes of the second transistor on the high-resistance thin film from the bottom using a low-resistance semiconductor thin film containing an impurity of one conductivity type and a high-melting point conductive film; a fifth step (f) of annealing the source and drain electrode portions with an energy beam and diffusing one conductivity type impurity in the low resistance thin film into the high resistance thin film; and (f) channel regions of the first and second transistors and the source. and a sixth step of selectively leaving the high-resistance thin film including the drain electrode portion in an island-like region (g) a seventh step of depositing a second gate insulating film (h) the source and drain of the first and second transistors. Eighth step (i) of forming contact openings in necessary portions of the electrode portion and the first gate electrode: depositing and selectively etching a metal film to provide at least the gate electrode of the second transistor and the first gate electrode wiring; A method for manufacturing a thin film transistor device comprising a ninth step. (2) The method for manufacturing a thin film transistor device according to claim 1, wherein at least a portion of the first gate insulating film exposed in the sixth step is removed using the island region as part of a mask. (3) Manufacturing the thin film transistor device according to claim 4 or 2, wherein in the ninth step, the fourth gate wiring extends over the second gate insulating film on the channel region of the first transistor. Method. (4) In the annealing in the third step, the high resistance thin film is melted and recrystallized, and in the annealing in the fifth step, the low resistance thin film and the high melting point conductive film are not melted. A method for manufacturing a thin film transistor device according to any one of the above.