JPS6257255A - Manufacture of compound semiconductor device - Google Patents

Abstract

PURPOSE:To prevent deterioration in characteristics due to stress, by using protecting films, wherein a film that imparts tensile stress to a GaAs semiconductor substrate and a film that imparts compression stress to the substrate are laminated, as the surface protecting films of the GaAs substrate at the time of annealing, thereby reducing the effective stress of the GaAs substrate. CONSTITUTION:Ions are implanted in the surface of a compound semiconductor 1. An insulating film 12 imparts tensle stress to the semiconductor substrate 1. An insulating film 13 or a conducting film imparts compression stress to the semiconductor substrate 1. Protecting films are formed by a laminated structure of the film 12 and the film 13. After the formation of the protecting film 12 and 13, heat treatment is performed. Thereafter parts, where electrodes 6 and 7 are to be formed at the surface of the semiconductor substrate 1 corresponding to said protecting films 12 and 13, are removed. For example, an N-channel 2 is formed by activation using an Si<+> ion implantation method and annealing in the surface in the GaAs substrate 1. Then, a WSi gate 5 is formed. Therefore, a part other than source and drain gates is covered with photoresist 10. The source and drain regions are formed by the ion implantation method in a self-aligning mode. Then the SiO2 film 12 is deposited by a sputtering method. The SiO2 film 13 is deposited by a chemical vapor deposition method at a normal pressure.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Application of the Invention] The present invention relates to a method of manufacturing an If-V group compound semiconductor device, and particularly to a method of manufacturing a semiconductor device suitable for large-scale integrated circuits using GaAs.

[Background of the invention]

In an integrated circuit using a GaAs semiconductor as a substrate, a MES-FET using a metal-semiconductor contact Schottky barrier in a gate portion is used as a board component. As shown in the cross-sectional view of FIG. 1, this FET consists of an n-type channel layer 2 formed by ion implantation into a substrate 1, an n-type source region 3, a drain region 4, and gates formed on their respective surfaces. Electrode 5. Source electrode 6. A drain electrode 7 and a source electrode 6 through the channel layer 2. It is operated by controlling the electrode flowing between the train electrodes 7 by an electric field applied to the gate electrode 5.

FIG. 2 shows the process of forming a conventional MES-FET on a GaAs substrate. That is, as shown in FIG. 2(a), first, an n-type channel layer 2 is formed on a QaAs substrate 1, and then a gate 5 made of a high melting point metal is formed.

W as the high melting point metal.

Ti-W alloy, W-Si alloy, W-AΩ alloy, tungsten nitride WN, etc. are used. Next, as shown in (b), 2×10 13 Si+ ions 8/Cl 112 are implanted by the ion implantation method to form source and drain regions. According to this method, the source and drain regions are formed in a self-aligned manner with respect to the channel layer.
ET can be created. Next, as shown in (c), <5jn2
．． After laminating the insulating film 9 such as Si3N4, 700~9
Annealing is performed at 00° C. to activate the ion implantation region.

Further, source and drain electrodes 6.7 are formed as shown in (d) to complete the MES-FET. In (c), the reason for covering the insulating film 9 is to prevent Ga and As on the surface of the GaAs substrate from evaporating and changing the quality of the crystal during high-temperature annealing at 700 to 900°C. .

In the above-mentioned conventional technology, the GaAs surface protection insulating film 9 shown in FIG. It has been reported that silicon dioxide, silicon nitride, aluminum nitride, and a laminated structure film or composite film thereof formed by a method or the like is used (see US Pat. No. 405,841.3, etc.).

In all of these reported insulating films, internal stress is generated in the insulating film depending on the manufacturing method or the manufacturing conditions, and compressive or tensile stress is exerted on the semiconductor substrate. There is a problem in that this stress causes peeling of the insulating film during high-temperature annealing or deterioration of FET characteristics due to abnormal diffusion of impurity elements added into the GaAs substrate.

[Purpose of the invention]

An object of the present invention is to provide a method for manufacturing a compound semiconductor device having a protective film that does not effectively apply stress to a GaAs substrate during annealing.

[Summary of the invention]

In order to achieve the above object, the present invention provides Ga
The present invention is characterized in that a protective film in which a film that exerts tensile stress and a film that exerts compressive stress are stacked on the GaAs semiconductor substrate is used as the As substrate surface protective film. As a result, G
a A, s It becomes possible to reduce the effective stress exerted on the substrate and to reduce the deterioration of characteristics due to stress.

[Embodiments of the invention]

As a method of activating the ion implantation layer of a compound semiconductor, the surface of the compound semiconductor is coated with a highly heat-resistant protective film, and then
It is well known that the so-called cap annealing method, which is annealing at a high temperature of 00 to 900° C., is the simplest and most effective method.

Highly heat resistant materials that can be used for compound semiconductors include 5i02.
Al11203. Si3N4. AflN, RN.

Insulators such as SiC, W, Ta, Hf,
Mo, Nb.

Refractory metals such as Zr, Cr, V, and Ti, and nitrides, oxides, carbides, borides, silicides, and the like of the refractory metals can be considered.

When these highly heat-resistant materials are formed into a thin film and adhered onto a compound semiconductor substrate, the stress exerted by the thin film on the compound semiconductor substrate varies depending on the manufacturing method and manufacturing conditions. Tables 1 and 2 show the results of our experiments regarding this. Table 1 shows the types of materials that give tensile stress to the GaAs substrate among the highly heat-resistant materials, their manufacturing methods, and typical manufacturing conditions, along with the magnitude of the tensile stress expressed in relative values. Table 2 shows G among the high heat resistant materials.
The types of materials, manufacturing methods, and typical manufacturing conditions that can withstand compressive stress with respect to the aA s substrate are shown together with the magnitude of the compressive stress expressed as a relative value.

Table 1 High heat resistant materials a... that exert tensile stress on GaAs substrates
- Sputtering method b... Plasma-induced vapor phase chemical growth method Table 2 GaAs It also serves as a protective film against contamination on the surface of a highly heat-resistant material that exerts compressive stress on the substrate. Therefore, among the materials having compressive stress or tensile stress, the material first laminated on the GaAs substrate-1] needs to be an insulator. Due to this necessity, the combinations of materials with compressive stress and materials with tensile stress are as follows.

Table 3 However, in combinations A and B, if a conductive material such as a refractory metal or a refractory metal silicide, nitride, or boride is used for the second layer, electrical connections between the elements will not be established when the element is completed. For separation, the used second layer material must be removed.

Moreover, the combination of B is the first J attached to the GaAs substrate.
The material f1 is formed by vapor phase chemical growth, but the thin film formed by this method has weak adhesion to the GaAs substrate or high melting point metal gate, and the material used for the second layer is If the tensile stress is large, the film may peel off. In combination A, the first layer of material deposited on the GaAs substrate and the high melting point metal gate has a strong adhesion force because it is formed by sputtering or plasma-induced vapor phase chemical growth. , does not cause the problem described with the combination B above, and is the best. The sputtering method or the combination of the plasma-induced air surface materials 2 is performed as follows.

The film thickness of each layer is determined from the relationship d, F, -d2F2=0. For example, if 5jO2 (50 nm) formed by the sputtering method shown in Table 1 is used for the first layer, and 5jo2 formed by the vapor phase chemical growth method shown in Table 2 is used for the second layer, the film thicknesses will be as follows.

Embodiments of the present invention will be described in detail below with reference to the drawings.

In the embodiment, GaAs is used as the semiconductor substrate. The amount of ion implantation is 40KeV acceleration voltage, and when forming an enhancement type FET], 8X1012
3.6 x 1.012 pieces/cm 2 for depression type FETs.

Activation annealing is performed in hydrogen at 800° C. for 15 minutes. Next, high-melting point metal W was sputtered using a sputtering method.
S i x (x = 0, 6) with a thickness of 300n
m, and using phosphorography technique and fluorine gas (CF
4. CHF3. A W Si x gate 5 is formed by a dry etching method using NF3, 5F6). Next, as shown in (b), the thickness of the area other than the source train part is 1
．． It was coated with a 6 μm photoresist 10 and was deposited by ion implantation at an acceleration voltage of 75 KeV and 2×]O”.
Si+ ions are implanted at a density of 1/Cm2 to form source/drain regions in a self-aligned manner.

I made this condition. This sputtered film is GaAs
The stress exerted on the substrate is tensile stress, and using the relative stress expression in Table 1, it is d□·F,=60X]2. Next, this 5i02 film 1 is grown by atmospheric pressure vapor phase chemical growth method.
Deposit 3. The film thickness d2 of this S'02 film 13 is shown in Table 2.
Using the relative compressive stress of , it is determined that As a result of combining the above two types of films, the stress acting on the GaAs substrate is
Table 12 Approximately -1 according to the relative expression method of stress used in the explanation of Table 2,
5 to +1.5 (- indicates compressive stress, 10 indicates tensile stress)
This was significantly reduced compared to 4 to 20 in the conventional method.

Next, the step shown in (d) will be explained. It can be seen that the ohmic so-called short gate effect can be reduced by forming the source and drain electrodes 6 and 7 made of AuGe/Ni/A11 using lithography technology. In addition, FIG. 5 shows the same sample as in FIG. 4 above.
It shows the relationship between gate breakdown voltage and gate width. As shown by the dotted line 17, in the conventional method, a FET with a large gate width has a very low breakdown voltage of about 1 V, whereas according to the present invention, as shown by a solid line 16, the breakdown voltage of an FET with a large gate width is significantly lower. It can be seen that this has been improved.

Example 2 The manufacturing process procedure of this example is shown in FIGS. 6(a) and 6(b). After forming the channel layer 2, the source/drain regions 3 and 4, and the high melting point gate 5 in the same manner as in Example 1 (a) and (b), the layer was formed to a thickness of 1 by plasma-induced vapor phase chemical growth.
Deposit 50 nm of 5i3N418. The deposition conditions were as follows: 4% Sj, H4 diluted with N2 was used as the reaction gas, the pressure was 0.5 Torr, and the substrate temperature was room temperature. W at this time
The film thickness was Sjx+8. In this way, when Si3N4 deposited by plasma-induced vapor phase chemical growth method and W Si x (x -0, 6) formed by sputtering method are deposited, with the above film thickness combination, Ga A s
The stress exerted on the substrate was in the range of -2.0 to +0.5, which was significantly reduced.

Next, after forming the cap films 18 and 19, annealing is performed in N2 at 800° C. for 20 minutes to activate the source/drain regions. Furthermore, after removing the WSjX (X=0.6) layer 19 deposited to reduce the stress of the cap film by a radical transport chemical dry etching method using CF4 gas, the film shown in FIG. As shown, AuGe
Source/drain electrodes 6 and 7 made of /Ni/Au are deposited and alloyed to complete the FET.

This method is also similar to that explained in Example 1.
[Effect of the Invention] According to the present invention, instead of W S i x (x = 0, 6) in Table 2, a tensile film is Using a protective film consisting of a layered film that applies stress and a film that applies compressive stress,
Since the stress effectively exerted on the GaAs substrate can be significantly reduced, F E due to abnormal diffusion of impurities caused by stress
This has the effect that fluctuations in the threshold voltage of T and deterioration of gate breakdown voltage do not occur.

[Brief explanation of the drawing]

Figure 1 is a cross-sectional view of MES-FET (7), and Figures 2 (a), (b), (c), and (d) are MES by the conventional method.
- Diagrams showing the FET manufacturing process, Figure 3 (,) (b) (C
)(d) and FIGS. 6(a) and (b) are M according to the present invention.
E S-F T:! : Production of T 2 [Diagram showing the culm, 4th
5 and 5 are diagrams showing the effects of the present invention. 1... GaAs substrate, 2... Channel layer, 3... Relationship between gate width and breakdown voltage of source FET, 17... Relationship between gate width and breakdown voltage according to conventional method. =15= 躬7Fig.

Claims (1)

[Claims] 1. A step of implanting ions into the surface of a predetermined compound semiconductor substrate, a protective film having a laminated structure of an insulating film that exerts tensile stress on the semiconductor substrate and an insulating film or conductive film that exerts compressive stress on the semiconductor substrate. 1. A method for manufacturing a compound semiconductor device, comprising the steps of forming a protective film, heat-treating the protective film after forming the protective film, and removing a portion of the protective film where an electrode is to be formed on the surface of the semiconductor substrate.