JPS6254898A - Sense amplifier circuit - Google Patents

Abstract

PURPOSE:To simplify a circuit and to enable the titled circuit to respond rapidly by connecting to the positive side of the power source the drain of a PchMOS transistor connected to source side, that of a NchMOS transistor whose source side is connected to the negative side of the power source, that of a memory group consisting of NchMOS transistors, and the gate input part of an inverter. CONSTITUTION:The potential at a node 3 is made of level Vss in the initial state by a Nch transistor 8. An input circuit operates, and a Pch transistor 7 begins to operate, and thus precharging begins. When a sense amplifier circuit of a dummy completes sufficient charging of the dummy, the precharge of the sense amplifier circuit of the principal circuit ends, and the transistor 7 turns OFF. The voltage level of the node 3 is compared by the Pch transistors 9 and 10. And a latch circuit in the stage after a node 6 latches the output data value of the node 6. On ending of the said latch, the Nch transistor 8 begins to turn ON, and the level of the node 3 is returned to its initial state.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a sense amplifier circuit used in semiconductor memory devices and the like.

[Summary of the invention]

The present invention uses a PahMO whose source side is connected to the power supply e side.
8) The drain of the transistor, the drain of the NChMOS transistor whose source side is connected to the power supply e side, and the Nch
The object of this invention is to create a semiconductor memory device capable of high-speed response using a sense amplifier configured by connecting the drain of a memory group composed of MOS transistors and the gate input section of an inverter.

[Conventional technology]

Since the conventional sense amplifier circuit has a complicated circuit as shown in FIG. 3, it is not suitable for high-speed response; it also increases the size of the semiconductor memory device, causing an increase in cost. Furthermore, since control circuits and the like become more complex in proportion to sense amplifier circuits, etc., a simple sense amplifier circuit has been desired. [Problems and Objectives to be Solved by the Invention] Problems to be Solved by the Invention The point is the complexity of the conventional sense amplifier circuit and the accompanying complexity of the sense amplifier circuit control circuit. Therefore, in the present invention, a semiconductor memory device capable of high-speed response is created using a simple sense amplifier circuit. The purpose is to

[Means for resolving interlude points]

The drain of the Pch MO3) transistor whose source side is connected to the power supply side, and the Nch MO transistor whose source side is connected to the power supply e side.
A semiconductor memory device is manufactured using a sense amplifier circuit characterized in that the drain of a chMO3h transistor, the drain of a memory group composed of NChMOS transistors, and the gate input part of an inverter are connected.

[For production]

When the sense amplifier circuit as described above is used, the circuit becomes simple and high-speed response is possible.

Furthermore, since the control circuit of the sense amplifier circuit becomes simple, the storage device itself becomes smaller, and it is also possible to reduce costs.

〔Example〕

Embodiments of the present invention will be described below based on the drawings. In FIG. 1, the potential at the node 30 is brought to the level of Vss by the N ch ) transistor 8 in the initial state. The input circuit operates, the Pah transistor 7 starts operating, and precharging begins. When the dummy sense amplifier circuit completes sufficient charging of the dummy, the precharging of the sense amplifier circuit of this circuit ends. That is, the Pch transistor 7 is turned off. At the end of the precharge, the voltage level of the node 6 has already been rated by the PCh transistor 9 and the N ah ) transistor 10, and the output data value of the node 6 is latched by the latch circuit after the node 6'. At the end of the latch (OL==I, OW level), the Nch transistor 8 starts to turn on, and the level of the node 5 is returned to the initial state. A circuit similar to that shown in FIG. 1 is also used for the dummy sense amplifier circuit. In this manner, the present invention has a very simple configuration because the sense amplifier circuit is constructed using only two inverters and a latch circuit. In addition, if the size of the Langstaff (P ah ) is increased, the 3N resistance during charging will be reduced, and the sensing time will be faster.

In other words, speeding up can be achieved simply by increasing the size of the PCh transistor. Further, speeding up can also be achieved by lowering the frequency rate level of the comparator formed by the Pch transistor 9 and the Nch transistor 10. FIG. 2 shows a graph of changes in the voltage level of node 6 over time. From t=0, precharging starts simultaneously for both the dummy circuit and the main circuit. Then, in the dummy circuit, at the end of charging (t=T-), the Pch transistor 7 in FIG. 1 turns OFF'? However, the level of node 4 changes from LOW to 1 (instead of iGH, the /-doro data is latched, and the /-doro level is returned to the initial state. △T in Fig. 2 indicates that the dummy circuit has finished charging. Indicates the delay time inside the circuit from the time the judgment is made until the node 4 changes ◇ In the sense amplifier circuit, when t==T+△T, the memo IJ
The voltage level of node 3 in FIG. 1 must be completely separated from the comparator level in the case of OFF and the case of memory ON.

Therefore, all the memo IJOIF in the semiconductor storage device
The dummy charging curve must be below the charging curve of F, like the dotted line curve in Figure 2. All memory ON charging curves must exceed the comparator level until t==T+△T. It is necessary that there be no.

Considering the above, the ON resistance of the memory, P a
h) Ranjistaft size, Pch) Langista 9,
It is necessary to determine the comparator level value of the comparator constituted by Nch) transistor 10, other floating M capacity 1, etc.

〔Effect of the invention〕

The effect of the present invention is that by simplifying the sense amplifier circuit in a semiconductor memory device, a semiconductor memory device capable of high-speed response can be realized.

Furthermore, the sense amplifier circuit and its control circuit portion occupying the semiconductor memory device are reduced, making it possible to reduce the cost of the memory device itself.

Furthermore, as semiconductor memory devices become more miniaturized in the future, sense sensitivity will be required, and the use of this circuit provides a circuit configuration that can sufficiently handle the miniaturization.

The sense amplifier circuit of the present invention can be used in ROM (Read Only Memory), KPROM (Erasable Programmable Read Only Memory), EEPROM (Electrically Erasable Programmable Read Only Memory), and the like.

[Brief explanation of the drawing]

FIG. 1 is a sense amplifier circuit diagram according to an embodiment of the present invention. FIG. 2 is a Vt curve diagram of node 3 in FIG. 1. FIG. 6 is a conventional sense amplifier circuit diagram. 1... Power supply V DD 2... Precharge control terminal 4... Data latch circuit control terminal 5...
...Power supply Vss 7.9...PchMO8) Transistor 8.10
...lJohMO8) Ransistor 11...
...Memory group 12.14...Clocked inverter 13.1
5... Inverter... Power supply vDD 2... NAND circuit with clocked gate 3.4
...Memory group 5.6...Pch for precharging) transistor or more

Claims (1)

[Claims] The drain of the PchMOS transistor whose source side is connected to the power supply ■ side, the drain of the NChM@O@S transistor whose source side is connected to the power supply ■ side, and the NchM@
A sense amplifier circuit characterized in that the drain of a memory group composed of O@S transistors is connected to the gate input section of an inverter.