JPS6254472A - Nonvolatile semiconductor memory device - Google Patents

Abstract

PURPOSE:To enable a voltage of the same magnitude to be applied to a tunnel oxide film using the same high-voltage pulse by causing an overlapping portion to exist between the word line for selecting the MOS-type memory transistor and the floating gate of the MOS-type memory transistor. CONSTITUTION:A floating gate 1 extends under a word line 4, and a overlapping portion 12 exists between the floating gate 1 and the word line 4. By this, a capacitance CWL is newly formed between the word line 4 and the floating gate 1. Such a structure can be made without etching the floating gate 1 with self-alignment of a control gate 2 except the portion wherein the floating gate 1 forms a memory transistor 8. With this, a voltage of the same magnitude can be applied to the first insulating film using the same high-voltage pulse, at the time of injecting electrons into the floating gate and of removing electrons from the floating gate.

Description

[Detailed Description of the Invention] [Industrial Application Field] This invention is an electrically erasable/writable nonvolatile memory (E
EPROM).

[Prior Art] FIG. 5 shows, for example, 15SCCDigestofTec
Hnical Papers I), 152 (19
80) is a plan view showing a conventional EEFROM memory cell shown in FIG. In the figure, 7 is an active region, and a control gate 2 is formed above the floating gate 1. A tunnel region 3 is formed between the active region 7 and the floating gate 1. A bit line 5 is formed above the active region 7, and 6 is a contact region between the bit line 5 and the active region 7. A word line 4 is formed to intersect with a bit line 5 with an interval between the floating gate 1 and the control gate 2. A MOS type memory transistor 8 is formed in the active region 7 . 20 is a 1-bit memory cell.

6. FIG. 6(A) is a sectional view taken along the line AA in FIG. 5. In the figure, n+ type active! '1lt
70 is formed. On the silicon substrate 21 and n+
A field oxide film 22 for isolating elements is formed on the active region 70, and a floating gate 1 is formed on this field oxidation film. The floating gate 1 has a recess, and the field oxide film 22 becomes thinner below the recess, and the gate oxide film 23. A tunnel tunneling film 24 having a thickness of about 100A is formed.

This 1-channel oxide pattern 24 becomes the tunnel region 3 shown in FIG. A poly-poly oxide film 25 is formed on the floating goo 1 to 1, and a control gate 2 is formed on the poly-poly oxide film. Floating gate 1. Poly-poly oxide film 25. An oxide film 26 is formed to cover the control gate 2. Within this oxide film 26 there is a floating gate 1. A word line 4 is formed at a distance from the control gate 2. Cro is the volume 1 between the floating gate 1 and the n+ active li head region 70 at the bottom of the tunnel sequence 3. , C2· is the capacity between the control gate 2 and the floating gate 1.

FIG. 6(B) is a sectional view taken along the line BB of FIG.

In FIG. 6, n-type active regions 71 are formed on a silicon substrate 21 at intervals.
A gate acid (hi waist 23) is placed on the upper d5 and τ1 type active region
is formed. A floating board 1 is formed on this gate 111m23k, and a poly-poly oxide film 25 is formed on top of this floating board 1 to form a gate 2. There is. Also,
Word gravel 4 is formed on gate oxide Il* 23. Gate Shunka theory 23) l coating goo 1~1
．． Polypoly IE]? a film 25. control,'7
'-t2. An oxide film 2G is formed to cover the word line 4, and a bit 15 is formed on this oxide film. Bit line 5 is in contact with n-type active region 71 at contact region 6 . Silicon substrate 21, n-type active region 71, gate oxide film 23, floating gate 1, and poly-poly oxide 1'l! 25 and control gate 2 are MOS
A type of memory transistor 8 is configured. Cr s is the capacitance between the floating gate 1 and the channel portion of the memory transistor 8 (active region of the memory transistor 8).

FIG. 7 is a diagram showing an equivalent circuit of a memory cell of this EEPROM. In the figure, G is the potential of control gate 2, VrG is the potential of floating gate 1, and V
o is the potential of the n+ type active region 70 above the tunnel t[3. Since the floating gate 1 is covered with an oxide film, the potential Vr of the floating gate 1
G is given by the above-mentioned combination of capacitances.

Next, the operation of this EEPROM will be explained.

Information is stored in the memory transistor 8 depending on whether or not electrons are accumulated in the floating gate 1. When electrons are accumulated in the floating gate 1, the threshold of the memory transistor 8 as seen from the control gate 2! The 1ill pressure will be in a high state, and if no electrons are accumulated, it will be in a low state. When reading information from memory 1 to transistor 8, a voltage intermediate between the P1 voltage of the above two states is applied to controller 1 to roll gate 2, so electrons are accumulated in the floating gate. When this happens, the transistor 8 is turned off and the memory pill is selected; that is, when the word line 4 goes to the "H" level, no current flows from the bit line 5. On the other hand, if no electrons are accumulated in floating goo f-1, memory 1 to transistor 8- are turned on.
When word line 4 attains the "H" level, current flows from pins 1 to 5. A sense amplifier (F:A not shown) determines whether current flows in the bit line 5 or not, and makes a determination of ``1°+, ll□''.

Next, the injection of electrons into the floating gate 1 and the removal of electrons from the floating gates 1 to 1 will be explained.

In order to inject electrons into floating gate 1, control gate 2. A high voltage pulse is applied to the word line 4 and the bit line 5 is grounded. As a result, a high electric field is applied to the tunnel oxide film 24, and electrons are tunneled through the tunnel oxide film 24 from the n+ type active region 70 to the floating gate 1. To remove electrons from floating gate 1, bit line 5. A high voltage pulse is applied to the word line 4 and the control gate 2 is grounded. As a result, a high electric field is applied to the tunnel oxide film 24, and electrons are tunneled through the tunnel oxide film 24 from the floating gate 1 to the n+ type active region 70.

Next, the electric field applied to the tunnel oxide film 24 will be explained. Now, Si1. ), and assuming that the control board 21 is grounded, VrG is expressed by the following equation.

Vra=(Vca-Ccr+vo・Cro)/
<Ccr +Crs +Cro) = (1)
When injecting electrons into floating gate 1, Vc
c = VP F (B'R pressure/<)'vs (D potential), V. -〇, the electric field applied to the tunnel oxide film 24 is as follows.

E+-(VPP-C,cr)/'(Ccr+
Cr s −LCro ) ” j, x...(2
) Here, ( is the film thickness of tunnel refining wA24.

K Remove the Dengo from the floating gate (when removing it, V
o, =F F + Vc a-0, so the electric field applied to the saponification crotch 24 is as shown in the following equation.

E” (Vo-Vrc) /'Lg=LVr
P-L(Vrr-Cro>/(Ccr
+Crs+Cro))Co,/L,.

-~'FP ・(Ccr + Cr
s )/(Cc r +C; r s *
When applying a leakage voltage pulse of Crr o ) 'L(, g - (3), 161-), it is better to remove electrons from floating gate 1 i)' than to transfer electrons to loading gate 1. From 6 to 1-
The electric field applied to the channel IJ01H1IA24 is EQ −H+ = (VP p −Or s )
/'(C1r r + cr s + Cro) ・t
o.

... (4) only becomes larger.

[Problems to be Solved by the Invention] Since the conventional EEPROM is configured as described above, when electrons are injected into the floating gate 1-1, and when electrons are removed from the floating gate 1-1, In order to apply the same electric field to the 1-channel oxide film 24, the voltage of the high-voltage pulse during removal may be lowered, or the
There is a problem in that it is necessary to reduce the ion dose m and utilize the voltage drop caused by the depletion layer in this portion.

This invention was made in order to solve the above-mentioned problems.) It is necessary to lower the voltage of the high voltage pulse when injecting electrons into the O-TE/C gate, and to reduce the voltage of the high voltage pulse when injecting electrons into the floating gate. The purpose is to obtain a nonvolatile semiconductor memory device that can apply the same electric field to the tunnel oxide film using the same high voltage pulse during injection and when removing electrons from the floating gate. shall be.

[Means for Solving the Problems] A nonvolatile semiconductor memory device according to the present invention is such that a word line for selecting an MO8 type memory transistor and a floating gate of an MO3 type memory transistor overlap. .

[Function] In this invention, the capacitance between the word line and the floating gate makes it possible to lower the voltage of the high voltage pulse when injecting electrons into the floating gate, and roughly speaking,
The same high voltage pulse can be used to apply the same electric field to the first insulating film (tunnel oxide film) when injecting electrons into the floating gate and removing electrons from the floating gate. Make it.

[Example] Embodiments of the present invention will be described below with reference to the drawings.

In the description of this embodiment, the description of parts that overlap with the description of the conventional technology will be omitted as appropriate.

FIG. 1 is a plan view showing a memory cell of an EEFROM which is an embodiment of the present invention, and FIG.
It is an A-line sectional view. Further, the cross-sectional view taken along the line B--B in FIG. 1 is the same as that in FIG. 6(B). The configuration of this embodiment differs from the configurations of FIGS. 5 and 6(A) and (B) in the following points. That is, floating gate 1 is connected to word line 4.
Extending at the bottom, there is an overlapping portion 12 between the floating gate 1 and the word line 4 . Therefore, a new capacitor CWL is formed between the word line 4 and the floating gate 1. Such a structure can be made by not etching the floating gate 1 with the self-alignment line of the control gate 2 except for the portion where the floating gate 1 forms the memory transistor 8.

FIG. 3 is a diagram showing an equivalent circuit of a memory cell of this EEPROM. In the figure, VVL is the potential of the word line 4.

Next, the electric field applied to the tunnel moltenizer 24 will be explained. The potential Vra of the floating gate 1 is expressed by the following equation.

Vra = (Vc a −Cc r +VVL −
CwL-to Vo + Cro)
/ (Ccr +Cv -to Cr
s + Cro)
... (5) When injecting electrons into the floating gate 1, Vc i -V
w t =VPP, Vo -0tearno, and the electric field [Eili applied to the tunnel oxide film 24 is as follows.

E+ N−Vp p” (Ccr +0wt,
)/ (Cc r+Cv L +Cr s +Cr
o) ・t, x... (6) That is, when the same high voltage pulse is applied, the electric field applied to the tunnel oxide film 24 is C-Ccr+crs
+cro, EIN E+-[((Ccr +0wt)/(C+C
vL))−(Ccr/C)]・(VPP/l) QX=((CFs+'CFo)・CvL/
C・(C+0wt))・(VP
F/[I] ...(7) increases compared to the conventional EEPROM. That is, the same electric field can be applied to the tunnel oxide film 24 with a lower high voltage pulse.

Moreover, when removing electrons from the floating gate 1, Vo = Vw L −VF p , Vca −
0, the electric field applied to the tunneling generator 1i 124 is as follows.

E = (1-(Cwt + Cro)/(C
c re +CVL +Cr t +Cr o ) )・(Vrr
/l) x = ((Cer+Crs)/(Ccr+C
VL +Cr s +Cr o ) ) ・(V F
P / t QX )...(8) Comparing equation (8) with equation (6), if you set CwL=Cr, when electrons are injected into floating gate 1, and when electrons are removed from floating gate 1, At this time, it becomes possible to apply an electric field of the same magnitude to the tunnel oxide film 24 using the same high voltage pulse.

FIG. 4 is a plan view showing a memory cell of an EEPROM according to another embodiment of the invention. This embodiment differs from the structure of the embodiment shown in FIG. 1 in the following points. That is,
A floating gate 1° control gate 2 is also formed above the active region 7 on the side of the memory transistor 8, and a tunnel region 3 is formed below the bit F15. Even with such a layout, the same effects as in the above embodiment can be achieved.

[Effects of the Invention] As described above, according to the present invention, the word line for selecting the MO8 type memory transistor and the floating gate of the MO8 type memory transistor have rounded portions, so that the floating gate It is now possible to lower the voltage of the high voltage pulse when injecting electrons, and it is also possible to use the same high voltage pulse when injecting electrons into the floating gate and removing electrons from floating gate 1. It is possible to apply an electric field of the same magnitude to the insulating IJH (channel oxide film) of 1.

41 drawings lL! Figure 1 is a detailed explanation of this invention.
There is a plan view C showing a memory cell of M.

FIG. 112 is a sectional view taken along line A-A in FIG. 1.

FIG. 3 shows an isometric circuit of a memory cell of an EEPROM according to an embodiment of the present invention. Ii (there is.

FIG. 4 shows an EEPROM which is another practical example of the present invention.
FIG. 2 is a plan view showing a memory cell of FIG.

FIG. 5 is a plan view showing a memory cell of a conventional EEPROM.

FIG. 6 (A> is a sectional view taken along line A-A in FIG. 5, and
Figure (B) is a sectional view taken along the line B-B of the first section and FIG.

The seventh example is a diagram showing an equivalent circuit of a memory cell of a conventional EEE' ROM.

In the figure, 1 is a floating gate, 2 is a control gate 1 to . 3 is the tunnel area, 4 is the word line, 5 is the bit line, 6 is the contag (- area, 7 is the active ft4 area,
70 is an n+ type talking region, 71 is an n-type active region, 8 is a memory transistor, 12 is an overlapping portion, 20 is a memory cell, 21 is a silicon substrate, 22 is a field oxide film, 23
24 is a tunnel saponification film, 25 is a polyethylene film, and 24 is a tunnel saponification film.
The poly fused film 26 is an oxide film.

Note that the same reference numerals in each figure indicate the same or corresponding parts.

Agent Daiwa Masu Yuguan 1 Figure 6: Kotakutaku Kabuto Figure 3 Akira 5 Figure 6 Floor 1: n Bin Chungsheng 9 @ Area No. 7m Procedural amendment (voluntary) 2. Name of the invention Non-volatile 3, Person making the amendment 5, Claims column of the specification to be amended and Detailed description of the invention column 6, Contents of the amendment (1) The claims of the specification should be submitted on a separate sheet. Street.

(2) “And n-type active region 7” on page 3, line 8 of the specification
0 on" is corrected to "other than the active region 7 of".

(3) Correct "at the bottom of word line 4" in line 9 of page 11 of the detailed description to "to the bottom of word line 4."

Above 2, Claim (1) A non-volatile semiconductor memory device including at least one N40S type memory transistor temporarily formed on a semiconductor substrate, wherein the MO8 type memory transistor is formed on the semiconductor substrate. 1 f8 lamina and.

a floating gate formed on the first insulating crotch and storing charge for storing information;

l1jj A second insulating film formed on the floating gate.

a control gate formed on the second insulation ridge and controlling charge injection into the floating gate and charge removal from the floating gate; and a control gate formed on the second insulation ridge and overlapping with the floating gate. and a word line for selecting the MOS type memory transistor.

(2) The nonvolatile semiconductor memory WR according to claim 1, wherein the molded portion is located in a region other than the MO8 type memory 1-transistor area.

Claims (2)

[Claims] (1) A nonvolatile semiconductor memory device including at least one MOS type memory transistor formed on a semiconductor substrate, the MOS type memory transistor comprising: a first insulating film formed on the semiconductor substrate; a floating gate formed on a first insulating film and accumulating charge for storing information; a second insulating film formed on the floating gate; and surrounded by the second insulating film. a control gate for controlling injection of charge into the floating gate and removal of charge from the floating gate; and a control gate formed surrounded by the second insulating film and having a portion overlapping with the floating gate. A nonvolatile semiconductor memory device comprising a word line for selecting a MOS type memory transistor. (2) The nonvolatile semiconductor memory device according to claim 1, wherein the overlapping portion is located outside the area of the MOS type memory transistor.