JPS6251442B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to an image definition detection device that can be used in a focusing point detection device. More specifically, a light emitting unit such as an LED or a semiconductor laser is placed at one of two points that are conjugate to a predetermined position on the imaging plane of an imaging optical system of an optical device such as a camera or movie theater. On the other hand, a self-scanning photoelectric conversion means such as a CCD, a photodiode array, a self-scanning element whose photosensitive part is made of a PN junction and whose storage part and transfer part are made of a CCD, or a self-scanning photoelectric conversion means such as a BBD is used. At the same time, a luminous flux is projected from the light emitting unit through a predetermined aperture, and the luminous flux reflected on the object surface is transmitted through an aperture located at a different location from the aperture on the projection luminous flux side of the imaging optical system. The charge distribution generated in the self-scanning photoelectric conversion means (hereinafter referred to as a sensor array device) is extracted as a time-series signal, and the subsequent signal is input to the self-scanning photoelectric conversion means. A focusing point for detecting the sharpest point of the object image on the imaging plane of the imaging optical system and determining front focus and rear focus states (hereinafter referred to as direction detection) by signal processing by an electronic circuit system; In the detection method, the present invention relates to a method in which when a light beam other than the above-mentioned projected light beam enters the surface of the sensor array device, it is removed by a subsequent electronic circuit system (hereinafter referred to as external light removal). In general, when detecting the sharpness and direction of an object image on the imaging plane using the imaging optical system of an optical device such as a camera, a light beam active detection method is used to project a light beam onto the object from the optical device side. It is known as One of the problems that always arises in realizing such a detection method is the above-mentioned problem of removing external light. An example of an electronic circuit method for removing external light is as follows:
A known method is to modulate the light emitting state of a light emitter and synchronously detect the signal output from the photoelectric receiver to receive only a desired signal. Even with this electrical outside light removal method, most of the effects of illumination light such as AC light sources and sunlight commonly used in homes can be removed. However, the frequency band of the detection signal overlaps to a large extent with the frequency band of the alternating current component of external light, and there are limits to methods such as synchronous detection that separate signals based on their frequency and phase. .

In addition, there is a focus detection method as shown in Japanese Patent Application No. 53-64747, in which light is emitted at two positions that are conjugate to the predetermined imaging plane of an imaging optical system that is adjustable along the optical axis. A light emitting device and a photoelectric receiver are arranged, and after being projected from the light emitter through the imaging optical system, the light reflected by an object and incident on the imaging optical system is detected by the photoelectric receiver. At this time, the focus detection system, which is characterized in that the focus adjustment state of the imaging optical system with respect to the object is detected based on the output of the photoelectric receiver, is completely useless.

According to the external light removal method proposed in the present invention, even in such a focused point detection method, the external light equivalent signal superimposed on the signal envelope output from the sensor array device can be removed extremely well. Moreover, it has the characteristic that there is no attenuation of the required signal output. Until now, in the above-mentioned focused point detection method, the external light is very little, or the reflectance of the object surface irradiated with the projection light beam is uniform and the external light is uniformly distributed. The conditions were so limited that in-focus point detection was possible only in certain cases. This fact results in a significant decrease in the subject distance range in which focus can be detected and in focus detection accuracy under conditions with a lot of external light. The present invention provides an image clarity detection device that expands the range of object distances that can detect direction even in situations with large amounts of external light, and also expands the object distance that can be focused on, thereby making it possible to detect in-focus points with high precision. This is what we provide. The content of the invention will be explained in detail below based on examples.

FIG. 1 is a diagram showing the principle of a focus detection method according to the present invention. Figure b corresponds to the in-focus state, and figures a and c correspond to the front-focus and rear-focus states, respectively. To briefly explain the configuration, 1, 1', 1'' are imaging lenses, 6,
6', 6'' are imaging planes. 5, 5', 5'' are object planes. 2, 2′, 2″ each indicate a light source,
For example, a light emitter such as an LED semiconductor laser can be used.

The light beams emitted by the light sources 2, 2', 2'' are reflected by the A, A', A'' surfaces of the mirrors 4, 4', 4'', respectively, and are transmitted through the imaging lenses 1, 1', 1'' before being photographed. Face 5,
Spot images of the light sources 2, 2', 2'' are projected on the 5', 5''. The light sources 2, 2', 2'' are placed at predetermined positions on the imaging planes 6, 6', 6'', but in reality they may interfere with photographing or observation, so they are placed in a conjugate relationship with this position. , that is, they are arranged in an optically equivalent positional relationship with respect to the mirrors 4, 4', and 4''. Such a conjugate arrangement allows the sensor array device 3,
The same applies to lenses 3' and 3''.The light beams reflected on the subject surfaces 5, 5' and 5'' pass through the imaging lens 1,
1′, 1″ mirrors 4, 4′, 4″ B, respectively.
Reflected by B′, B″ plane, sensor array device 3,
A spot line is projected onto the 3', 3'' plane by the light sources 2, 2', 2''. Next, differences in each of figures a, b, and c will be explained. Among each component, when the imaging lens position is in focus as shown in figure b, the imaging plane 6'
, that is, moving away from the object plane 5'. In such a state, the spot image projected onto the object surface 5' is blurred and shifted. ' is a virtual position at which a spot image on the object plane 5' should be formed in the sharpest state by the imaging lens 1'. The incident light beam forms the sharpest image at the position of mirror 4'.
Sensor array device surface 3′ reflected by B′ surface
The incident image is formed at the top in a blurred state. The dotted lines schematically show the distribution of projected spot images on the object plane 5' and the sensor array device plane 3'. In this way, by unevenly distributing the light emitting and light receiving apertures in the imaging lens from the optical axis, the spot image that is focused on the conjugate point in the focused state corresponds to the position of the imaging lens. The incident images are formed blurred but shifted in opposite directions. Sensor array device 3 is the above-mentioned
These are self-scanning elements such as CCDs, BBDs, photodiode arrays, and even a photodiode as the light receiving section and a CCD as the transfer section.

FIG. 2 schematically shows signal waveforms and timing for explaining the external light removal method according to the present invention. φSH shown in the figure is a CCD shift pulse, which is a pulse used to open and close a transfer gate for transferring signal charges accumulated in a CCD photosensitive section to an analog shift register section. The sensor array device used in the following examples is a CCD, but this is of course not limited to a CCD, and a photodiode array, BBD or photodiode array is used for the photosensitive section, storage section and transfer section. A self-scanning sensor such as one using a CCD can be commonly applied. The _a0 period of φSH shown in FIG. 2 is a charge accumulation period, and the signal charge accumulated in this period is sent out as a time-series signal from the CCD output section in accordance with a predetermined clock in the next readout period. The transmitted signal envelope is schematically shown as Video in the figure. The signals corresponding to the sensor elements i to k in the figure are the portions of the signal envelope that are actually used. In addition, j is a sensor array device surface at a point that is in a conjugate positional relationship with the center of the light source 2, which is set in advance at a predetermined position of the imaging plane 6 shown in FIG. 2
Corresponds to the edge set on the dividing boundary.
i, j, k, and i', j', k' indicate fixed time positions in the transmitted video signal sequence, and i, i', j and
j', k, and k' are shifted by one period of each φSH. Further, the time intervals from i to j are set to be equal. FIG. 2 is a timing chart showing the blinking cycle of a light source, such as an LED. In this figure, the high level section is the lit section, and the low level section is the off section. The LED light from the lighting section a' enters the sensor array device according to the basic principle shown in Fig. 1, and a ₀ shown in Fig. 2
It is accumulated as a signal charge in the interval of . The lighting time a' is set to a time within the accumulation time _a0 . Since the lighting sections are set to be alternating with respect to the accumulation sections, the video signal shown in the figure also appears alternating with respect to the accumulation sections with a delay of one cycle.
In the figure, the video signal envelope a corresponds to this, and the video signal envelopes sent out in the signal selection periods immediately before and after a, for example b, correspond to the light source off period. Figure 2 is a timing chart of the analog switch for reversing the polarity of the integral. FIG. 2 schematically shows the Video signal after polarity inversion. Measurement errors can be suppressed by inputting only the required sections i to k and i' to k' in the video signal envelope to the subsequent integration circuit, and removing unnecessary parts in a time-sharing manner. This is a practically effective means. FIG. 2 shows a signal waveform subjected to such processing. The lighting section and the turning-off section of the light source, the corresponding signal envelopes a and b, and the polarity reversal section
The present invention is characterized in that external light signals are removed by repeating tj' to tj. Comparing the signal envelopes a and b, b corresponds to the section where the light source is turned off, so it is only a signal due to external light. Also, since a corresponds to the lighting section of the light source, a signal in which the signal from the light source is superimposed on the external light signal is sent out. If the sending timings of signal a and signal b are set so short that fluctuations in external light can be ignored, it can be considered that the envelope of the external light signal included in signal a is very similar to that of signal b. Therefore, as shown in Figure 2, from ti to tj, the negative polarity tj to tk
The signal output obtained by integrating the signal from ti' to tj' with positive polarity and the signal output from tj' to tk' with negative polarity is a differential integration signal based only on the signal from the required light source.

It is clear that the above polarity holds true in the same way regardless of whether it is positive or negative, and it is obvious that it may be determined as convenient for the electronic circuit system. According to the present invention, sufficient external light can be removed even in a situation where the external light signal envelope represented by signal b is not uniformly distributed on the sensor array device surface. A focused point detection method to which the external light removal method according to the present invention is applied will be described in detail below using examples.

FIG. 3 is a block diagram of a focused point detection circuit. Further, FIG. 4 discloses the contents of the sequence control circuit shown by the lock 21 in the circuit in FIG. Furthermore, FIGS. 5 and 6 show the timing of various control pulses.

In FIG. 3, a focusing lens 7, a light source 8, a sensor array device 9 and a planned imaging plane 1 are shown.
The spatial arrangement of 0 satisfies the conditions of the basic principle explained with reference to FIG. In the focusing lens 7, for example, the outer periphery of a distance ring of the lens barrel is a gear, and the inner periphery is a helicoid to make the focusing lens portion 7 of the photographic lens movable. That is, when the gear on the outer periphery of the distance ring rotates via the gear due to the rotation of the lens drive motor 27, the focusing lens portion 7 of the photographing lens is transmitted to the focusing lens section 7 by the helicoid so as to extend or retract in accordance with the rotation direction. 11, 12, and 12' are prism mirrors and mirrors arranged so that the light source 8 and the sensor array device 9 are in a conjugate relationship. The structure, arrangement, method, etc. of the driving mechanism of the focusing lens 7, the light source 8, the sensor array device 9, the prism mirror 11, and the mirrors 12, 12' are not particularly limited by the present invention. FIG. 3 shows an example of the configuration in a very schematic diagram and in principle.

In the figure, 13 is an offset adjustment circuit. For example, if a CCD with a PN junction in the photosensitive part is used as the sensor array device 9, and if it uses P-type Si, the Video
In the form of signal output, there is a dark current level at a level about 0.5V to 1.5V below the compensated output level of about +6V to +10V, and a video signal saturation level about 1.2V to 2.0V below. Therefore, such a CCD outputs a video signal proportional to the amount of optical signal in a downward direction, that is, in a negative direction. Furthermore, it corresponds to each picture element.
The video signal has a duty of about 75% (and about 25%).
% interval is a reset interval), and this is output in chronological order. One form of the video signal output method of the sensor array device 9 has been described above, but it will naturally vary greatly depending on the sensor method and also to some extent depending on the device. In the offset adjustment circuit 13 mentioned above,
It plays the role of removing DC offset, preventing saturation of the subsequent electronic circuit system, and increasing the dynamic range. Furthermore, by using an inverting amplifier in the offset adjustment circuit 13, the video signal output can be inverted and treated as a positive voltage signal in the example of the sensor array device 9, if necessary. 14 is a sample and hold circuit. A sensor array device similar to the above example in which the photosensitive part has a PN junction and the transfer part consists of a CCD (hereinafter referred to as PN+CCD)
Since a reset period is required in this case, the video signal becomes a time series signal with a duty of about 75%. In addition, when a MOS type photodiode array is used as a sensor array device, the video signal for each picture element becomes a waveform when a capacitor is discharged, and the duty becomes extremely small. When such a video signal waveform is integrated by the subsequent integrating circuit 18, the output loss is very large.Therefore, only the envelope of the video signal output originally contains information for determining the focusing state. Therefore, it is advantageous to hold the reset period. _The sensor _array device used in _this example of the invention is _a PM +
Since it is a CCD, for example, _φ2 and _φ3 may be sampled by the exclusive OR circuit 30. 15A is an AC amplifier. Further, 16 is a circuit for regenerating the DC component. DC regeneration may be clamped using the timing of the pulse φSH for opening and closing the transfer gate, or if a dark current level is set in the sensor array device, the DC regeneration is generated from the counter after a predetermined bit count from the timing of φSH. The carry may be used for timing for clamping. By using the AC amplifier 15 and the DC component regeneration circuit 16, it is possible to obtain a video signal envelope that has been amplified with the required gain and has the DC offset component strictly removed. However, depending on the circuit configuration, AC amplifier 1
5. Even if the DC component regeneration circuit 16 is removed, there is no significant effect, and similarly, even if only the offset adjustment circuit 13 is removed, the effect is not significantly reduced. 20
is a PN+CCD drive circuit. Figure 5 shows the source clock pulse CLK and the transfer clock _φ1 to _φ4.
Transfer gate opening/closing pulse φSH, reset pulse φ
Shows the timing chart of RS and Video signals. PN+CCD drive circuit 20 in Figure 3
is a circuit mainly for generating such pulses. 17 is an integral polarity inversion circuit. Only the signal in the set integration interval of the video signal envelope is integrated by the subsequent integration circuit 18.
This circuit is used to change the input using a switch and to invert the polarity of the integral. In the integral polarity inverting circuit 17 and the integrating circuit 18, in order to reduce as much as possible the DC offset generated by the electronic circuit system itself, for example, a chopper amplifier is used to obtain an extremely stable integral signal with very little change over time. I can do it.

In FIG. 3, 21 is a sequence control circuit. Further, FIG. 4 discloses the sequence control circuit 21 as a specific example, and FIG. 6 is a timing chart showing the timing relationship of pulses for performing sequence control. 3 in Figure 4
4, 37, 40 are counters. Counters 34, 37, are loaded by. 3
3 is an inverter for obtaining an inverted signal of φSH. 36 and 38 are preset digital switches. In step 36, the starting point of integration is set. When the counter 34 counts from the loaded position to a preset starting point, the counter 34 outputs the carry CR1.
occurs. Also, preset digital switch 3
8 is for setting the center position of the integral interval. Pulse to set center position (=φ ₂ )
As soon as the number is counted, from the counter 37
CR2 occurs. 39 is a digital subtracter. The preset digital switches 36 and 38 are used to set the same number from the integration start point to the center position of the integration interval. The set point produced by digital subtractor 39 sets the end point of the integration interval. After counting the number of pulses (=φ ₂ ) up to the set end point, counter 4
From 0, a Cary CR3 is generated. 35,4
1 and 42 are flip-flop circuits. Each
CR1, CR2, and CR3 are input. The Q of flip-flop 41 is used as a signal to load counter 40. That is, the counter 40 counts from the center position of the integral interval to the number set by the digital subtracter and calculates the carry CR.
Generates 3. Since the F/F1Q output from the flip-flop 35 sets the start of integration, this and the output from the flip-flop 42,
The pulse obtained by ANDing F/ F3Q can be used as a pulse for setting the integration interval. 4
3 is an AND circuit, and the integral interval setting pulse outputted from this is hereinafter referred to as IE. Further, the output F/F2Q of the flip-flop 41 is further inputted to the flip-flop 44. The output F/F4Q of the flip-flop 44 is used as a pulse for inverting the integral polarity. The light source used in the present invention (in this embodiment, an LED is used) is φSH
It is an essential condition that the lights flash alternately. Therefore, in order to implement this, φSH is input to the flip-flop 45 to obtain the pulse output of F/F 5Q.

This F/F5Q is used as a pulse for driving the light source. In this embodiment, the flip-flop 45 is operated in synchronization with the rising edge of φSH.
I am trying to output F5Q. However, it is not necessary to drive the light source under such limited conditions, and the light source drive pulse may be determined so that the light source is turned on from any time point within a predetermined lighting period to any period. In other words, turn the light source on and off in this way.
If a pair of φSH exists over two periods of φSH, the signal due to external light accumulated in the sensor array device during that period is removed and a difference signal due to the required light source is output. The integrating circuit in FIG. 3 outputs a signal obtained by integrating the difference signal from which the external light component has been removed a predetermined number of times. The integral polarity inversion circuit 17 has an analog switch for setting a predetermined integral interval, and is controlled by an integral interval setting pulse IE. Further, an analog switch for reversing the integral polarity is controlled by F/F4Q. The signal output from the integrating circuit 18 is used to determine the focus state, that is, front focus, rear focus, or focus. A positive or negative signal is output depending on whether the pin is the front pin or the rear pin. The position of the focusing lens 7 at the zero cross point is the sharpest in-focus point. Reference numeral 19 denotes a sample-and-hold circuit, which outputs the integrated signal at the time when the signal output from the integrating circuit 18 reaches a predetermined absolute value level or when the ON/OFF pair of signals from the light source is integrated up to a predetermined number of times. It is something to hold. 28 is an absolute value circuit. Further, 28' is a comparator. Vref1 is a reference level and is determined by design specifications. For example, a small amount of the integrated signal level that enables direction detection and discrimination is determined in advance and this level is set.
Set it to Vref1. By setting Vref1 in this way, the direction detection speed can always be set to the shortest time. Further, 29 is a counter. A pulse signal of F/F5Q is input from the sequence control circuit 21 and the number of pulses is counted.
The counter 29 counts a predetermined number of pulses according to design specifications. The count number is determined from the maximum allowable in-focus point detection time, and the capacity of the counter 29 is determined or preset. In this embodiment, the F/F5Q output from the sequence control circuit 21
As mentioned above, is also used as the drive pulse of the drive circuit 22 for driving the light source 8. 31 is an OR circuit. OR of the output of the comparator 28 and the carry output of the counter 29
is taken as the sampling pulse of the sample and hold circuit 19. 32 is a counter for performing one pulse delay. After the sampling is completed, the integrating circuit 18 is reset and a reset pulse is generated to enable the next state of in-focus point detection. Sample and hold circuit 19
The output of
The magnitude relationship between Vref2 and Vref3 (Vref2–Vref3) is determined. If the output level of the sample-and-hold circuit is Vref3 or more and Vref2 or less, it is determined that it is within the focusing range, and a display element such as an LED is detected.
25 and 25' are both lit. Note that 24 is a drive circuit for a display element drive circuit and a focusing lens drive motor 27. Also, the output level of the sample and hold circuit is Vref2,
If it is outside the range set by Vref3, that is, outside the focusing range, only one of the display LEDs 25, 25' lights up corresponding to the front focus or rear focus state. Also, in such a state, the focusing lens driving motor 27 is rotated in the corresponding direction by the motor drive circuit 24, and the focusing lens 7 is rotated in the corresponding direction by the motor drive circuit 24.
is set within the focusing range.

As described in detail above, according to the present invention, the amount equivalent to external light can be efficiently removed from the signal envelope output from the sensor array device. This has the effect of increasing the focusable subject distance and enabling highly accurate focus detection.

[Brief explanation of the drawing]

Figures 1a, b, and c are diagrams illustrating the principle of image definition detection according to the present invention; 3 is a diagram showing an example of the signal processing circuit of the image clarity detection device according to the present invention, FIG. 4 is a diagram showing a specific configuration example of the sequence control circuit in the circuit shown in FIG. 3, and FIGS. 5 and 6. 1 is a diagram showing the timing of various control pulses, etc.; FIG. 1, 1', 1''...imaging optical system, 2, 2', 2''...
...Light emitting means, 3,3',3''...Photoelectric conversion means,
4, 4', 4''... Prism, 5, 5', 5''... Subject, 6, 6', 6''... Planned imaging plane.

Claims (1)

[Scope of Claims] 1. A light-emitting means that is provided at a predetermined image-forming surface of an imaging optical system or a position optically equivalent thereto, and is capable of periodically projecting light through a predetermined portion of the imaging optical system; A self-scanning type that is arranged so that its approximate center is located on the planned imaging plane or a position optically equivalent thereto, and that can output the light intensity distribution of the light incident through other parts of the imaging optical system as a time-series signal. Within each half cycle of the blinking of the photoelectric conversion means and the light emitting means, a signal before the signal from the central part and a signal after the signal from the central part of the time series signal are integrated with opposite polarity, respectively. An image sharpness detection device characterized by comprising an integrating circuit that switches both integral polarities every half cycle, and further adds the integration result every one cycle of the blinking.