JPS624357A - Manufacture of semiconductor device - Google Patents

Abstract

PURPOSE:To improve reproducibility of the configuration and diffusion of impurities into a semiconductor substrate, by forming an impurity diffusing mask on a trench-forming etching mask into a step shape to form a trench, and then by moving it to the surface of the semiconductor substrate by anisotropic etching. CONSTITUTION:After SiO2 1 is grown on the surface of a semiconductor substrate 2, photolithography is done against the SiO2 surface to form a diffusing mask pattern. Thereafter, a pattern of a trench etching mask having a step is formed, and the etching is done by employing it, forming a trench 2a in the semiconductor substrate 2. Next, the SiO2 1 is etched to form an impurity diffusing mask. After a PSG film 3 is grown, heat treatment diffuses N-type impurities to form a diffused region 4 in the trench 2a and in the vicinity of the trench 2a at the same time. Next, HF solution removes the SiO2 1 and PSG 3 respectively.

Description

Detailed Description of the Invention (Field of Industrial Application) The present invention provides a method for manufacturing a semiconductor device that can improve the stability of an Nfil impurity diffusion region in a semiconductor device having a groove capacitor/arm capacitor. It is related to.

(Conventional technology) Conventionally, Guinabatsuku! The structure of a semiconductor device such as MO8RAM that has a Mizaya capacitor is, for example,
It is disclosed in Japanese Patent No. 8-12739.

#13- is a diagram showing a process from forming a groove in a conventional groove type capacitor to diffusing N-ri impurity into the groove. FIG. 3(a) shows a state in which 5iO11 is grown to a thickness of about 1 μm on the semiconductor substrate 2 and photolithography is performed to form a trench etching mask.

Next, in FIG. 3(b), etching is performed to form @2a on the semiconductor substrate 2, and in FIG. 3(c), it is grown by about 22W% (20PSG3t-2000A).

Thereafter, as shown in FIG. 3(d), a heat treatment is performed to diffuse N-type impurity (Pl) from the PSG to the semiconductor surface within the trench 2a, thereby forming a diffusion region 4.

Next, in FIG. 13(e), PSG is used as a diffusion source for N-type impurities and 95too is used as an etching mask.
In FIG. 3(f), a resist 5 is used to mask the impurity diffusion around the groove 2a of the photo ring 2.
The a-th
At rlA (g), resist 5 is removed and groove 2 is
After the formation of groove 2a, the step of diffusing impurities into the groove 2a and into the periphery of the groove 2a is completed.

After that, a dirt insulating film is formed by thermal oxidation, and a conductive polysilicon film is grown to form the state shown in Fig. 3(h). By growing the film to the thickness shown in Figure 3(i), etch-packing it by anisotropic etching, and flattening it, #
The state shown in Fig. 13 (1) is obtained, and after nine turns using photolithography, the shizokuya canopy is completed in the state shown in Fig. 3 (j).

As an example of a semiconductor device having this trench-type capacitor/mother capacitor, a semiconductor memory device is shown in Figure #13 (k3), in which a trench-type capacitor, an element isolation region consisting of a field oxide film 8 and a channel stop impurity diffusion region IO, and a transfer gate electrode are shown. 9 and a trans-gate transistor group consisting of source/drain impurity diffusion regions 11.

(Problems to be Solved by the Invention) However, in the method described above, impurities are not introduced into the groove and around the groove at the same time, and the methods are different, which tends to cause concentration changes, etc. However, the photolithography around the trench was unstable, and the size of the impurity diffusion region around the trench was unstable.

This invention addresses the problems of the prior art,
The object of the present invention is to provide a method for manufacturing a semiconductor device that solves the problems of the impurity concentration change in the trench and around the trench and the instability of the impurity diffusion region around the trench.

(Tth Means for Solving the Problems) The present invention provides a method for manufacturing a semiconductor device in which a trench etching mask with a step difference tV is formed on a semiconductor substrate, a PST is formed by anisotropic etching, and then the semiconductor substrate is A process is introduced in which a groove etching mask is etched on the surface of the substrate to form an A4 turn of an impurity diffusion mask.

(Function) This invention introduces the above-mentioned steps into the manufacturing method of a semiconductor device, so that the material of the groove etching mask is etched by anisotropic etching to form a groove in the semiconductor substrate, and the a4 of the impurity diffusion mask is etched. The turns are formed so as to be in contact with the surface of the semiconductor substrate, and during impurity diffusion, the Nm impurity is automatically diffused into the trench and around the trench, thereby eliminating the above-mentioned problem.

(Example) Hereinafter, an example of the method for manufacturing a semiconductor device of the present invention will be described based on the drawings. FIGS. 1(a) to 311(g) are process explanatory diagrams of one embodiment.

In this figure 1-) to figure I11), figure 3(a)
- The same parts as in FIG. 3 (goods) will be described with the same reference numerals.

First, as shown in FIG.
SiO,1 is grown on the 8108 surface to a depth of about 1.5 μm by CVD, and photoring 2 is performed to form a diffusion mask pattern to a depth of about 0.5 μm from the 8108 surface.

Thereafter, as shown in FIG. 1(b), 9 turns of a groove etching mask having steps are formed, and then 1 turn is formed.
As shown in FIG. 1111(c) K, a trench 2a is formed in the semiconductor substrate 2 by anisotropic etching using this trench etching mask.

Thereafter, by etching the 1,5iO21 by anisotropic etching, the state shown in FIG. 541(d) is obtained, and an impurity diffusion mask is formed. This corresponds to the state shown in FIG. 3(b) of the conventional manufacturing method.

After this, after going through the same steps as in Fig. 3(c), Fig. 3(d), and Fig. 3(→), as shown in Fig. 5111(e), P
A film of SG3 is grown, and as shown in FIG. 1, N-impurity is diffused by heat treatment to simultaneously form a diffusion region 4 in the groove 2& and in the periphery of the groove 2a.

Next, as shown in Figure 1 □□□), S10
The removal of .degree.1 and the removal of PSG3 are performed, respectively, and the step of forming the trench and diffusing the Nm impurity into the trench and around the trench is completed.

112(a) to 12(e) are process explanatory diagrams of other embodiments of the method for manufacturing a semiconductor device of the present invention.

First, as shown in Figure 2(a), after growing Sl011m to about 1 μm on the surface of the semiconductor substrate 20 by CVD, pre-silicon 12 is grown to about 100 OA, and then ST
o, ib to grow 0.5 #m.

Next, in JR2 Figure 1, an impurity diffusion mask arm turn is formed, whereas in the above #11o example, the level difference for forming the impurity diffusion mask/mother turn is largely dependent on the etching conditions. In this second embodiment, since the polysilicon 12 is sandwiched in the middle, it is possible to detect the end point of etching, and the reproducibility of the step difference is greatly improved.

Next, in Fig. JR2 (C), a vine turn of the groove etching mask is formed, and then, in Fig. 2 (d),
Groove formation etching is performed to form a groove 2a in the semiconductor substrate 2.

After that, as shown in Fig. 312(e)K, SLo, 1m.

By etching 1b by anisotropic etching, an impurity diffusion mask mother turn is formed directly on the surface of the semiconductor device 2.

Thereafter, impurities are diffused into the groove a and around the groove by a process similar to that of the first embodiment.

(Effects of the Invention) As described above in detail, according to the present invention, an impurity diffusion mask is formed on a stepwise pattern on a groove forming etching mask, and is moved to the surface of a semiconductor substrate by groove forming diameter anisotropic etching. As a result, the reproducibility of the shape is good and the impurity can be diffused into the semiconductor substrate inside the groove and around the groove at the same time. .

Along with this, the uniformity of the impurity concentration distribution is good.
It is expected that the characteristics of trench type capacitors having impurity diffusion regions will be improved.

[Brief explanation of drawings]

Figures 11(a) to 11(a) to 11(a) are process explanatory diagrams of an embodiment of the method for manufacturing a semiconductor device of the present invention, and Figures 2(a) to 11(a) to 11(a) to 11(a) are process explanatory diagrams of an embodiment of the method for manufacturing a semiconductor device of the present invention. Figure s2 (e) is a process explanatory diagram of another embodiment of the method for manufacturing a semiconductor device of the present invention, jl! 3 (a) to 3 (ld are process explanatory diagrams of a conventional method for manufacturing a semiconductor device. 1, 1 m, 1 b-Si (%, 2... semiconductor substrate, 2a groove, 3... ... PSG, 4... Diffusion region, 1
2...Polysilicon. Patent applicant Oki Electric Industry Co., Ltd. Figure 1

Claims (1)

[Claims] (a) A step of forming a groove etching mask having a step on a semiconductor substrate and forming a groove in the semiconductor substrate by anisotropic etching; (b) After forming the groove, removing the groove etching mask. forming an impurity diffusion mask on the surface of the semiconductor substrate by anisotropically etching the material; (c) growing a PSG film through the impurity diffusion mask; and (d) inside the groove. and a step of diffusing an N-type impurity from the PSG into the semiconductor substrate around the trench.