JPS62274782A - Manufacture of semiconductor device - Google Patents
Manufacture of semiconductor deviceInfo
- Publication number
- JPS62274782A JPS62274782A JP11746486A JP11746486A JPS62274782A JP S62274782 A JPS62274782 A JP S62274782A JP 11746486 A JP11746486 A JP 11746486A JP 11746486 A JP11746486 A JP 11746486A JP S62274782 A JPS62274782 A JP S62274782A
- Authority
- JP
- Japan
- Prior art keywords
- layer
- gate
- metal layer
- ohmic
- silicon oxide
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 14
- 238000004519 manufacturing process Methods 0.000 title claims description 9
- 239000002184 metal Substances 0.000 claims abstract description 55
- 229910052751 metal Inorganic materials 0.000 claims abstract description 55
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims abstract description 21
- 229910052814 silicon oxide Inorganic materials 0.000 claims abstract description 19
- 239000000758 substrate Substances 0.000 claims abstract description 9
- 239000012535 impurity Substances 0.000 claims description 33
- 238000000926 separation method Methods 0.000 claims description 2
- 238000000034 method Methods 0.000 abstract description 21
- 229920002120 photoresistant polymer Polymers 0.000 abstract description 17
- 229910001218 Gallium arsenide Inorganic materials 0.000 abstract description 4
- 239000011248 coating agent Substances 0.000 abstract description 2
- 238000000576 coating method Methods 0.000 abstract description 2
- 238000001459 lithography Methods 0.000 abstract description 2
- 238000000206 photolithography Methods 0.000 abstract description 2
- 239000006185 dispersion Substances 0.000 abstract 1
- 230000008020 evaporation Effects 0.000 abstract 1
- 238000001704 evaporation Methods 0.000 abstract 1
- 238000005530 etching Methods 0.000 description 13
- 230000015572 biosynthetic process Effects 0.000 description 4
- 230000015556 catabolic process Effects 0.000 description 4
- 239000002131 composite material Substances 0.000 description 4
- 238000005229 chemical vapour deposition Methods 0.000 description 3
- 230000000694 effects Effects 0.000 description 3
- 238000000605 extraction Methods 0.000 description 3
- 238000007796 conventional method Methods 0.000 description 2
- 238000005468 ion implantation Methods 0.000 description 2
- 238000002955 isolation Methods 0.000 description 2
- 125000006850 spacer group Chemical group 0.000 description 2
- 238000000992 sputter etching Methods 0.000 description 2
- 241000430525 Aurinia saxatilis Species 0.000 description 1
- 229910018885 Pt—Au Inorganic materials 0.000 description 1
- -1 Silicon ions Chemical class 0.000 description 1
- 238000002679 ablation Methods 0.000 description 1
- 239000003795 chemical substances by application Substances 0.000 description 1
- 229910052681 coesite Inorganic materials 0.000 description 1
- 150000001875 compounds Chemical class 0.000 description 1
- 229910052906 cristobalite Inorganic materials 0.000 description 1
- 230000006866 deterioration Effects 0.000 description 1
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 description 1
- 239000010931 gold Substances 0.000 description 1
- 229910052737 gold Inorganic materials 0.000 description 1
- 150000002500 ions Chemical class 0.000 description 1
- 210000003127 knee Anatomy 0.000 description 1
- 239000007788 liquid Substances 0.000 description 1
- 238000001451 molecular beam epitaxy Methods 0.000 description 1
- 238000005268 plasma chemical vapour deposition Methods 0.000 description 1
- 229910052710 silicon Inorganic materials 0.000 description 1
- 239000010703 silicon Substances 0.000 description 1
- 239000000377 silicon dioxide Substances 0.000 description 1
- 235000012239 silicon dioxide Nutrition 0.000 description 1
- 229910052682 stishovite Inorganic materials 0.000 description 1
- 229910052905 tridymite Inorganic materials 0.000 description 1
- 238000007740 vapor deposition Methods 0.000 description 1
Landscapes
- Electrodes Of Semiconductors (AREA)
- Junction Field-Effect Transistors (AREA)
Abstract
Description
【発明の詳細な説明】
３、発明の詳細な説明
〔発明の目的〕
（産業上の利用分野）
本発明はゲート電極ならびにオーミック電極等を自己整
合によって形成する方法に関し、特にＧａＡｓＦＥＴに
好適するものである。Detailed Description of the Invention 3. Detailed Description of the Invention [Object of the Invention] (Field of Industrial Application) The present invention relates to a method of forming gate electrodes, ohmic electrodes, etc. by self-alignment, and is particularly suitable for GaAsFETs. It is.
（従来の技＃？）
■−Ｖ族半導体化合物を利用した半導体素子としてＧａ
ＡｓＦＥＴもしくはＧａＡｓ１Ｃ等が実用化されている
が、このＧａＡｓＦＥＴの製造方法を第２図ａ−ｅ及び
第３図ａ−ｅにより説明する。(Conventional technique #?) ■-Ga as a semiconductor element using V group semiconductor compound
AsFET, GaAs1C, etc. have been put into practical use, and a method for manufacturing this GaAsFET will be explained with reference to FIGS. 2 a-e and 3 a-e.
第２図にはＮ中層すなわち高濃度不純物領域をゲートに
対して自己整合的に形成する例を示し、第３図はオーミ
ック金属層をゲートに対して自己整合的に設ける方法を
示す。FIG. 2 shows an example in which an N medium layer, that is, a high concentration impurity region is formed in self-alignment with the gate, and FIG. 3 shows a method in which an ohmic metal layer is formed in self-alignment with the gate.
第２図ａに示すようにＧａＡｓ基板２０にエピタキシャ
ル成長法で低濃度不純物領域Ｎ−２１ならびに高濃度不
純物領域Ｎ−２２を順次堆積後、その表面を被覆するフ
ォトレジスト層２３にはＦＥＴのゲート予定位置が開口
した穴明はパターンを第２図すに示すように形成する。As shown in FIG. 2a, after a low concentration impurity region N-21 and a high concentration impurity region N-22 are sequentially deposited on a GaAs substrate 20 by an epitaxial growth method, a photoresist layer 23 covering the surface is used as a gate for an FET. The holes with open positions form a pattern as shown in Figure 2.
次いでこのフォトレジスト２３をマスクとして等方性食
刻法により高濃度不純物領域２２を溶除して低濃度不純
物領域２１を露出させて窓を設けこぎにゲート金、＠２
４を蒸着し、更にこの開口内に堆積したゲート金属以外
はフォトレジスト層２３をスペーサとするいわゆるリフ
トオフ法によって除去するが、この状態を第２図Ｃの断
面図に示す。Next, using this photoresist 23 as a mask, the high-concentration impurity region 22 is removed by isotropic etching to expose the low-concentration impurity region 21 and a window is formed.
4 is vapor-deposited, and further, the portion other than the gate metal deposited in the opening is removed by a so-called lift-off method using the photoresist layer 23 as a spacer, and this state is shown in the cross-sectional view of FIG. 2C.
前記等方性食刻工程により高濃度不純物領域２２にはゲ
ート金属２４を囲むテーパ部が形成される。Through the isotropic etching process, a tapered portion surrounding the gate metal 24 is formed in the high concentration impurity region 22.
次にオーミック電極２５の設置に当って、このゲート金
属２４を保護するフォトレジスト層２３′ を第２図ｄ
に示すように形成後全面にオーミック電極用金属を蒸着
しこのフォトレジストＭ２３′ に堆積したオーミック
電極用金属をリフトオフ法によって除去してＦＥＴを完
成する。この断面図を第２図ｅに示した。Next, when installing the ohmic electrode 25, a photoresist layer 23' that protects the gate metal 24 is applied as shown in FIG.
As shown in FIG. 3, after the formation, an ohmic electrode metal is deposited on the entire surface, and the ohmic electrode metal deposited on the photoresist M23' is removed by a lift-off method to complete the FET. This cross-sectional view is shown in FIG. 2e.
次にオーミック金属をゲートに対して自己整合的に設置
する例を第３図により説明するが第２図との同一部品に
は同一の番号を付ける。Next, an example in which an ohmic metal is installed in a self-aligned manner with respect to a gate will be explained with reference to FIG. 3, and the same parts as in FIG. 2 are given the same numbers.
この例はいわゆるサイドウオールをゲート金属の側面に
被着する型を示すもので、特に高濃度不純物領域とゲー
ト金属間の距離を調整可能として逆バイアス時の耐圧劣
化ならびに耐圧向上を狙ったものであることは良く知ら
れている。Ｇ ａ Ａ ｓ半導体基板２０の表面からそ
の内部に向けて低濃度の不純物を導入して第３図ａに示
すよようにＮ−領域即ち、低不純物濃度領域２１を形成
してから、所定の位置にゲート金属２４を蒸着法により
堆積する。This example shows a type in which a so-called sidewall is attached to the side surface of the gate metal, and the distance between the high-concentration impurity region and the gate metal can be adjusted in particular, with the aim of reducing breakdown voltage deterioration and improving breakdown voltage during reverse bias. One thing is well known. After introducing low concentration impurities from the surface of the GaAs semiconductor substrate 20 into the inside thereof to form an N- region, that is, a low impurity concentration region 21 as shown in FIG. A gate metal 24 is deposited at the position by vapor deposition.
次にステップカバレージの良好な絶縁膜例えばプラズマ
ＣＶＤ（ｃｈｅｍｉｃａｌ Ｖａｐｏｕｒ Ｄｅｐｏｓ
ｉｔｉｏｎ）膜２６を第３図すのように被覆し１次に異
方性食刻法例えばＲＩ Ｅ （Ｒｅａｃｔｉｖｅ Ｉ
ｏｎ Ｅｔｃｈｉｎｇ）によってゲート金属２４の側面
にサイドウオール２７を形成する。更に、第３図Ｃに示
すようにフォトレジスト２３’ 、サイドウオール２７
およよびゲート金属２４をマスクとして珪素イオンを半
導体基板２０にイオン注入法によって導入して高濃度不
純物領域２２を形成し、引続きオーミック金属２５を全
面に被覆する。この結果ゲート金属層２４ならびにサイ
ドウオール２７の頂面にもこのオーミック金属２５が被
着されこれをいわゆるエッチバック法によって除去する
。Next, an insulating film with good step coverage, such as plasma CVD (chemical vapor deposition)
tion) The film 26 is coated as shown in FIG.
A sidewall 27 is formed on the side surface of the gate metal 24 by on etching. Furthermore, as shown in FIG. 3C, a photoresist 23' and a side wall 27 are
Silicon ions are introduced into the semiconductor substrate 20 by ion implantation using the gate metal 24 as a mask to form a high concentration impurity region 22, and then the entire surface is covered with an ohmic metal 25. As a result, the ohmic metal 25 is deposited on the top surfaces of the gate metal layer 24 and the sidewalls 27, and is removed by a so-called etch-back method.
具体的には前述のイオン注入工程時に使用したフォトレ
ジスト層２３′に代えて新たにフォトレジスト２３゛″
を第３図ｄのように被覆しこれをＲＩＥ法によってゲー
ト金属層２４ならびにサイドウオール２７が露出するま
で除去する。この露出したオーミック金属２５はイオン
エツチングによって除去してソース、ドレインとして機
能する高濃度不純物領域毎にオーミック金属を形成し、
又この金属上のフォトレジストは０□アツシヤ等によっ
て除去して第３図ｅのＦＥＴを形成する。Specifically, a new photoresist layer 23'' was used in place of the photoresist layer 23' used during the ion implantation process described above.
is coated as shown in FIG. 3d, and removed by RIE until the gate metal layer 24 and sidewalls 27 are exposed. This exposed ohmic metal 25 is removed by ion etching to form an ohmic metal in each high concentration impurity region that functions as a source and a drain.
The photoresist on this metal is removed by a 0□ assher or the like to form the FET shown in FIG. 3e.
（発明が解決しようとする問題点）
第２図ａ−ｅに示したＧａＡｓＦＥＴの製造方法ではオ
ーミック金属層２５とゲート金属層２４の間隔を第２図
すに示すようにリソグラフィ技術によるマスク合せによ
って実施しているので、その合せズレが生じ易く安定し
た素子特性が得られない難点があった。(Problems to be Solved by the Invention) In the GaAsFET manufacturing method shown in FIGS. 2a-e, the distance between the ohmic metal layer 25 and the gate metal layer 24 is determined by mask alignment using lithography technology as shown in FIG. Since this method is implemented, there is a problem that misalignment easily occurs and stable device characteristics cannot be obtained.
又、第２図ａ〜ｅに例示したサイドウオールを形成した
ＧａＡｓＦＥＴにあってはフォトレジスト層によって平
坦化工程を施してからエッチバックを行うが、ゲート金
属層の露出と同時にこのＲ４Ｅ処理を中止するいわゆる
ジャストエツチング（Ｊ ｕｓｔ Ｅ ｔｃｈｉｎｇ）
が仲々難かしくその終了点（Ｅｎｄ Ｐｏ１ｕｔ）を検
出するのが困難であった。本発明はこの難点を除去した
半導体装置の製造方法に関し、簡便で歩溜りの良い製造
方法を提供することを目的とする。In addition, in the case of GaAsFETs with sidewalls formed as shown in FIGS. 2a to 2e, etchback is performed after a planarization process is performed using a photoresist layer, but this R4E process is stopped at the same time as the gate metal layer is exposed. So-called just etching
It was difficult to detect the end point (End Poult). The present invention relates to a method of manufacturing a semiconductor device that eliminates this difficulty, and an object of the present invention is to provide a method of manufacturing a semiconductor device that is simple and has a high yield.
（問題点を解決するための手段）
この発明はゲート電極及びオーミック引出し電極を自己
整合法を利用して形成するが、その具体的手段としては
■−■族半導体基板に低濃度不純物領域を設け、これを
被覆する高濃度不純物領域に積層した珪素酸化物層の異
方性食刻によって孔部を設け、露出した低濃度不純物領
域にゲート金属を形成するリセス構造とした。このゲー
ト金属の形成に先立って高濃度不純物領域には珪素酸化
物層を設け、これの選択的除去によって得られるパター
ンにオーミック金属層を形成し、このオーミック金、＠
層に間挿した珪素酸化物層の除去的オーミック金属層端
をオーバハング構造とし、この孔部に堆積するゲート金
Ｒ層に段切れを発生させ。(Means for Solving the Problems) In the present invention, the gate electrode and the ohmic lead-out electrode are formed using a self-alignment method, and the specific method is to form a low concentration impurity region on a ■-■ group semiconductor substrate. A hole is formed by anisotropic etching of the silicon oxide layer laminated on the high-concentration impurity region covering the high-concentration impurity region, and a recessed structure is formed in which gate metal is formed in the exposed low-concentration impurity region. Prior to the formation of this gate metal, a silicon oxide layer is provided in the high concentration impurity region, and an ohmic metal layer is formed in the pattern obtained by selectively removing the silicon oxide layer.
The ends of the removed ohmic metal layer of the silicon oxide layer interposed between the layers are formed into an overhang structure, and a step break is generated in the gate gold R layer deposited in this hole.
オーミンク金属に積層するゲート金属層を引出し電極と
して利用する。The gate metal layer laminated on the Ohmink metal is used as an extraction electrode.
（作用）
ｍ−ｖ族半導体基板には低濃度不純物領域と高濃度不純
物領域を順次被着し、その表面を覆うＣＶＤ珪素酸化物
層を選択的に除去し、この結果ゲート形成予定位置に残
った珪素酸化物層の周りにオーミック金属層を形成する
。このゲートの形成予定位置に残った珪素酸化物層を異
方性食刻工程によって溶除してリセス構造にすると共に
低濃度不純物領域を露出させ、この食刻によるダメージ
を除去するためにライトエツチングを行う。この結果オ
ーミック金属層端にはいわゆるオーバハング構造が形成
され次いで被覆するゲート金属層はこの部分で段切れを
起して高濃度不純物領域及びリセス構造に被着する。こ
の高濃度不純物領域に積層したゲート金属層はオーミッ
ク金属の引出し電極として利用し、又リセス構造に被着
するゲート金属層とは自己整合によって同時に形成され
る。(Operation) A low-concentration impurity region and a high-concentration impurity region are sequentially deposited on the m-v group semiconductor substrate, and the CVD silicon oxide layer covering the surface is selectively removed. An ohmic metal layer is formed around the silicon oxide layer. The silicon oxide layer remaining at the location where the gate is to be formed is removed by an anisotropic etching process to form a recessed structure, and the low concentration impurity region is exposed, and light etching is performed to remove the damage caused by this etching. I do. As a result, a so-called overhang structure is formed at the end of the ohmic metal layer, and the covering gate metal layer then breaks off at this portion and adheres to the high concentration impurity region and the recess structure. The gate metal layer laminated in this high concentration impurity region is used as an ohmic metal lead electrode, and is formed simultaneously with the gate metal layer deposited on the recessed structure by self-alignment.
この結果ゲートとオーミック金屑間の距離が極めて小さ
いのでＦＥＴとしてのソース電極即ち高濃度不純物領域
の直列抵抗が小さく、更にリセス構造を採用したので表
面空乏層の影響が抑制され、ゲート耐圧を向上する。As a result, the distance between the gate and the ohmic gold dust is extremely small, so the series resistance of the source electrode, that is, the high concentration impurity region, as an FET is small.Furthermore, the adoption of a recessed structure suppresses the effects of the surface depletion layer, improving gate breakdown voltage. do.
（実施例）
第１図ａ ” ｈに示す製造工程により本発明を詳述す
る。(Example) The present invention will be explained in detail with reference to the manufacturing process shown in FIGS.
ＧａＡｓ半導体基板１には分子線エピタキシィ法等によ
って低濃度不純物領域Ｎ−２および高濃度不純物領域Ｎ
＋ ３を厚さ０．３ｔｍ及び０．５ａｍ積層する。A low concentration impurity region N-2 and a high concentration impurity region N are formed on the GaAs semiconductor substrate 1 by molecular beam epitaxy or the like.
+3 is laminated to a thickness of 0.3tm and 0.5am.
この工程としては、各領域を所定の厚さに゛堆積してか
らドーズ量１〜３ Ｘ １０” ｃｍ−” と５×１０
°■２のＳｉイオンをイオン注入してＮ−ならびにＮ÷
領領域した。In this process, each region is deposited to a predetermined thickness, and then the dose is 1 to 3 x 10"cm-" and 5 x 10 cm.
By implanting Si ions of °■2 into N- and N÷
It was territory.
この断面図を第１図ａに示す０次にこの表面に被覆した
厚さ約０．４．のＣＶＤ珪素酸化物層４に被着するフォ
トレジスト層５を利用してオーミック電極用の窓明けを
いわゆるフォトリソグラフィ技術によって行うがその断
面を第１図すに示す。This cross-sectional view is shown in FIG. 1a. The thickness of the coating on this surface is about 0.4 mm. Using the photoresist layer 5 deposited on the CVD silicon oxide layer 4, a window for the ohmic electrode is formed by a so-called photolithography technique, the cross section of which is shown in FIG.
引続いてこの窓に露出した珪素酸化物層４を溶除して現
われた高濃度不純物領域３にオーミック金属６としてＡ
ｕ Ｇ ｅを０．２４ ＮｉＯ，３，ｎからなる複合
金属層を蒸着する。この結果第１図Ｃにみられるように
フォトレジスト層５・・・頂面にはこの複合金属層が被
着するが、これらをこのフォトレジスト層をスペーサと
してリフトオフし、引続いて前述のゲート形成予定位置
に被着する珪素酸化物層を溶除し、次の素子分離工程に
移行する。Subsequently, the silicon oxide layer 4 exposed in this window is melted away, and A is applied as an ohmic metal 6 to the high concentration impurity region 3 that appears.
A composite metal layer consisting of 0.24 NiO,3,n is evaporated. As a result, as shown in FIG. 1C, this composite metal layer is deposited on the top surface of the photoresist layer 5, which is lifted off using this photoresist layer as a spacer, and then the above-mentioned gate The silicon oxide layer deposited on the planned formation position is dissolved away, and the process moves to the next element isolation step.
この工程としては第１図ｄに示すように、オーミック金
属層６及びその中心部分に被着した珪素酸化物層４部分
をフォトレジストマスク５′で被覆してからＧ ａ Ａ
ｓ半導体基板１及びニーに被着した高ならびに低濃度
不純物領域２，３からなる素子分離領域７をＨ，ＰＯ，
＋Ｈ，Ｏ，＋Ｈ，Ｏ等方性食刻液によって溶除してメサ
型の素子領域１１を形成する。第１図ｄに図示した点線
は形成する素子領域を示すもので、フォトレジスト層５
′を除去して第１図ｅに示すように新たなフォトレジス
トマスク５′をこの素子領域側面とオーミック金属層６
に形成してから前記ゲート形成予定位置に残存する珪素
酸化物層４の穴明けを実施するにの珪素酸化物層４はＢ
ｃｌ、ガスを利用する異方性食刻即ちＲＩ Ｅ （Ｒ
ｅａｃｔｉｖｅ Ｉｏｎ Ｅｔｃｈｉｎｇ）によって高
濃度不純物領域３に達するまで行う。In this step, as shown in FIG. 1d, the ohmic metal layer 6 and the silicon oxide layer 4 deposited on the center thereof are covered with a photoresist mask 5', and then G a A is applied.
s The element isolation region 7 consisting of the high and low concentration impurity regions 2 and 3 attached to the semiconductor substrate 1 and the knee is heated with H, PO,
A mesa-shaped element region 11 is formed by ablation using +H, O, +H, O isotropic etching liquid. The dotted lines shown in FIG. 1d indicate the element regions to be formed, and the photoresist layer 5
' is removed and a new photoresist mask 5' is applied between the sides of this device region and the ohmic metal layer 6, as shown in FIG. 1e.
After forming the silicon oxide layer 4, the silicon oxide layer 4 remaining at the gate formation position is drilled.
cl, anisotropic etching using gas, or RIE (R
(active ion etching) until reaching the high concentration impurity region 3.
この食刻ダメージ層を除去するために前記素子分離工程
に適用した等方性食刻液によって軽く食刻する。 この
ライトエツチング（ｌｉｇｆｔ ｓｔｃｈｉｎｇ）によ
ってオーミック金属層端ａにはヒサシができたいわゆる
オーバハング構造が第１図ｆに示すように形成され、次
いでゲート金属層９をこのオーミック金属層６上に蒸着
する。このゲート金属としてはＴｉ −Ｐｔ −Ａｕ（
０，１趨−０，，２４−０，３４）をこの順に堆積した
複合層を採用するが、この蒸着層は前記オーバハング構
造のために二Ｎで段切れを起しゲート層形成予定位置の
孔部８にこの複合金属からなるゲート金属層９が堆積し
高濃度不純物領域３に隣接する構造となる。In order to remove this etching damage layer, it is lightly etched using the isotropic etching solution used in the element separation process. By this light etching (ligft stitching), a so-called overhang structure with a canopy is formed at the end a of the ohmic metal layer, as shown in FIG. This gate metal is Ti-Pt-Au (
A composite layer is adopted in which layers 0,1-0,,24-0,34) are deposited in this order, but due to the overhang structure, this deposited layer is broken at 2N, and the gate layer is formed at the planned position. A gate metal layer 9 made of this composite metal is deposited in the hole 8 to form a structure adjacent to the high concentration impurity region 3.
前記オーミック金属層に積層したこのゲート金属層９′
はその引出し電極層として利用し、最終的にはパッシベ
ーシミン層１０としてプラズマＳｉＯ２（今後Ｐ−３ｉ
Ｏと記載する）を０．５μｓ程度被覆してＦＥＴを完成
する。This gate metal layer 9' laminated on the ohmic metal layer
will be used as the extraction electrode layer, and will eventually be made of plasma SiO2 (P-3i
(denoted as O) for about 0.5 μs to complete the FET.
このゲート金属層９及び引出し電極層９′には適当な位
置に電極を形成するのは当然であるが、図面では省略し
た。It is a matter of course that electrodes are formed at appropriate positions on the gate metal layer 9 and the extraction electrode layer 9', but these are omitted in the drawings.
（発明の効果）
このように本発明では１回のリングラフィ工程によって
ゲートとソースドレイン領域が決められるので、精度良
くゲートとオーミック間隔が調整でき、したがってバラ
ツキの少ないＦＥＴ特性が小滴り良く得られる。(Effects of the Invention) In this way, in the present invention, since the gate and source/drain regions are determined by a single phosphorography process, the gate and ohmic spacing can be adjusted with high precision, and therefore FET characteristics with little variation can be obtained with good droplets. .
更に、ゲートとオーミック領域間隔が極めて狭いので、
ソースの直列抵抗（Ｒｓ）が小さく、又リセス構造を
採用しているため表面空乏層の影響も小さくゲト耐圧が
向上する利点がある。Furthermore, since the distance between the gate and the ohmic region is extremely narrow,
The series resistance (Rs) of the source is small, and since the recessed structure is adopted, the effect of the surface depletion layer is small and the gate breakdown voltage is improved.
更に又、ゲート電極形成と同時にオーミック引出し電極
も形成できるので工数を従来より少なくできる。Furthermore, since the ohmic lead electrode can be formed at the same time as the gate electrode, the number of steps can be reduced compared to the conventional method.
第１図ａ ＝ ｈは本発明に係るＦＥＴの製造工程を示
す断面図、第２図ａ−ｅならびに第３図ａ〜ｅは従来の
製造工程毎の断面図である。
代理人 弁理士 井 上 −男
第 １１！１
第 ３ 図
＠ ２ 図FIG. 1 a=h is a sectional view showing the manufacturing process of an FET according to the present invention, and FIGS. 2 a-e and 3 a-e are sectional views showing each conventional manufacturing process. Agent Patent Attorney Inoue - Male No. 11!1 Figure 3 @ Figure 2
Claims (1)
域を順次積み重ね、この積層体表面に被着する絶縁物層
を選択的に除去して露出する前記高濃度不純物領域にオ
ーミック金属層を被覆後、素子分離工程によって得られ
る素子領域の前記オーミック金属層間に残る前記珪素酸
化物層を除去して前記低濃度不純物層を露出すると共に
前記オーミック金属層にオーバハング構造を形成し、こ
のオーミック金属層及び露出した前記低濃度不純物領域
にゲート金属層を被覆することを特徴とする半導体装置
の製造方法。A low-concentration impurity region and a high-concentration impurity region are sequentially stacked on a semiconductor substrate, and the insulating layer adhering to the surface of this stack is selectively removed to coat the exposed high-concentration impurity region with an ohmic metal layer. The silicon oxide layer remaining between the ohmic metal layers in the element region obtained by the separation step is removed to expose the low concentration impurity layer, and an overhang structure is formed on the ohmic metal layer, and the ohmic metal layer and the exposed silicon oxide layer are removed. A method of manufacturing a semiconductor device, characterized in that the low concentration impurity region is covered with a gate metal layer.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP11746486A JPS62274782A (en) | 1986-05-23 | 1986-05-23 | Manufacture of semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP11746486A JPS62274782A (en) | 1986-05-23 | 1986-05-23 | Manufacture of semiconductor device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS62274782A true JPS62274782A (en) | 1987-11-28 |
Family
ID=14712328
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP11746486A Pending JPS62274782A (en) | 1986-05-23 | 1986-05-23 | Manufacture of semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS62274782A (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5043776A (en) * | 1988-06-28 | 1991-08-27 | Nec Corporation | Semiconductor device having compound semiconductor FET of E/D structure with high margin |
-
1986
- 1986-05-23 JP JP11746486A patent/JPS62274782A/en active Pending
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5043776A (en) * | 1988-06-28 | 1991-08-27 | Nec Corporation | Semiconductor device having compound semiconductor FET of E/D structure with high margin |
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