JPS62199121A - Decoder - Google Patents

Abstract

PURPOSE:To attain the correction of an accurate offset voltage without providing an exclusive comparator by using a decoding buffer amplifier in common use as a comparator so as to discriminate an output code of an LPF. CONSTITUTION:With switches 5-7 turned on, an analog voltage in accordance with the decoding rule is generated from an input digital signal by an input register 1 and an analog voltage generating circuit 2, impedance conversion is applied by a buffer amplifier and a high frequency component is eliminated by an LPF4. Then an offset voltage from a pseudo offset voltage generating circuit 10 is subtracted via an analog adder 11 and the result is outputted. The sign of the offset voltage is discriminated via an amplifier 3 acting like a comparator while the buffer amplifier connection is interrupted by the connection of switches 8, 9. Thus, the buffer amplifier is used in common as a comparator and no exclusive comparator is provided to apply accurate offset voltage correction.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a decoder that decodes a digital signal into an analog signal, and more particularly to a decoder that has a function of internally compensating for offset voltage generated by a circuit.

[Conventional technology]

Conventionally, a decoder that decodes a digital signal into an analog signal consists of an input register that stores an input digital signal, an analog voltage generation circuit that generates an analog voltage according to the decoder from the output of the input register, and an analog voltage generation circuit. Many are used that consist of a four-way filter that performs impedance conversion on the output of the buffer amplifier, and a low-pass filter that removes the high frequency components of the buffer amplifier.

In such a decoder, a circuit as shown in FIG. 2 has been conventionally used to compensate for the offset voltage generated in the buffer amplifier and low-pass filter.

In FIG. 2, l is an input register, 2 is an analog voltage generation circuit, 3 is a buffer amplifier, and 4 is a low-pass filter. Further, 10 is a pseudo offset voltage generation circuit, which generates a voltage equal to the offset voltage generated by the buffer amplifier 3 and the low-pass filter 4, and an analog adder 11 generates a pseudo-offset voltage from the output voltage of the low-pass filter 4. Compensate for offset voltage by subtracting the voltage. Furthermore, the generation of the pseudo offset voltage.

Assuming that the input digital signal arrives with equal probability of positive and negative signals, the sign of the output of the decoder is determined by the comparator 12, and when the observation probability at the sample time of positive and negative signs deviates from i, that deviation is determined by the decoding This is an offset voltage generated within the device. Therefore, a pseudo offset voltage can be generated by sampling the sign of the comparator 12 at appropriate timing every time the input digital signal is updated, integrating it over a long period of time, and creating an analog voltage corresponding to this.

[Problem that the invention seeks to solve]

However, according to the above-mentioned conventional technology, the comparator 12 is required in the feedback path for offset voltage compensation, and therefore there is a drawback that the offset voltage generated by the comparator itself cannot be compensated for. The decoder of the present invention includes an input register that stores an input digital signal, a voltage generation circuit that generates an analog voltage according to the decoder from the output of the input register, and a a buffer amplifier that performs impedance conversion, a low-pass comparator that removes harmonic components of the output of the buffer amplifier, a means for switching to determine the sign, and a means that integrates the sign output and converts it into an analog voltage. , and means for subtracting from the output of the low-pass filter.

[Embodiments of the invention]

Next, a decoder according to the present invention will be explained with reference to the embodiment shown in FIG. In the same figure.

1 is an input register, 2 is an analog voltage generation circuit.

3 is a buffer amplifier, 4 is a low-pass filter, 5 to 9 are switches, 10 is a pseudo offset voltage generating circuit, and 11 is an analog adder.

In normal decoding operation, switches 5, 6 and 7 are connected and 8 and 9 are open. As a result, the buffer amplifier 3 is connected as a buffer, so that the voltage converted from a digital signal to an analog signal in accordance with the decoder in the analog voltage generation circuit 2 is transmitted to the low-pass filter 4. The output of the low-pass filter 4 is sent to the analog adder 1
1, the pseudo offset voltage from the pseudo offset voltage generation circuit 10 is subtracted from the decoder output.

In this case, the pseudo offset voltage is generated at a timing when the connection between the buffer amplifier 3 and the low-pass filter 4 is cut off, such as when the input register data is updated. Switches 5.6 and 7 at that point are open and 8 and 9 are connected. Therefore, the buffer amplifier 3 is disconnected from the buffer and acts as a comparator to determine the sign of the output of the low-pass filter 4. Note that the operation of generating the pseudo offset voltage using this code is the same as that of the conventional technique shown in FIG.

〔Effect of the invention〕

As is clear from the above description, according to the present invention, the sign of the output of the low-pass filter can be determined by changing the connection of the decoding buffer amplifier and using it as a comparator.

It is possible to accurately compensate for the offset voltage without providing a dedicated comparator, and the effect of improving performance and economy is significant.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing the configuration of an embodiment according to the present invention;
FIG. 2 is a block diagram showing an example of the configuration of a conventional decoder.

Claims (1)

[Claims] 1. An input register that stores an input digital signal, a voltage generation circuit that generates an analog voltage according to the decoder from the output of the input register, a buffer amplifier that performs impedance conversion on the output of the voltage generation circuit, and In a decoder comprising a low-pass filter that removes harmonic components of the output of a buffer amplifier, and obtaining a decoded output from the output side of the low-pass filter, means for opening the feedback path of the buffer amplifier and switching to a comparator. and means for switching to add the output of the low-pass filter to the comparator to determine the sign; and means for integrating the sign output and converting it into an analog voltage, and subtracting it from the output of the low-pass filter. , a decoder that compensates for offset voltages of the buffer amplifier and the low-pass filter.