JPS62154172A - Processor for vector instruction - Google Patents

Abstract

PURPOSE:To attain the optimum processing for vector instructions with the scalar data use to an operand by changing an arithmetic processing means after checking the value of the scalar data. CONSTITUTION:When a scalar data indicating bit 31 or 32 of an operand is equal to the value '1' which indicates the scalar data, the scalar data of the relevant operand is sent to the scalar check circuits 41 and 42 for check of such values like '0', '1', etc. The output checking results of both circuits 41 and 42 are delivered to a vector arithmetic processing changing circuit 50 together with the types of vector arithmetic which are held by an arithmetic designating register 10. The circuit 50 checks whether the vector arithmetic processing can be changed or not. If said arithmetic processing change is possible, the circuit 50 uniforms the contents of the vector arithmetic processing change to an arithmetic part via a signal line together with a vector arithmetic processing change request.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a vector instruction processing device, and particularly to a vector instruction processing device that uses scalar data as an operand. The present invention relates to a vector instruction processing device that enables high-speed processing of vector operations by changing the .

[Conventional technology]

Conventionally, when processing a vector instruction of Vl (I) x V2 (1) - V3 (1), this type of vector instruction processing device has conventionally
), the vector elements corresponding to operand 2 (V2) are sequentially read from the storage device, the arithmetic unit repeatedly executes a predetermined operation as many times as the number of elements to be sequentially processed, and the result of the operation is stored as operand 3 (V3). They are sequentially stored in the address locations corresponding to operand 3 (■3) on the device.

Even when operand 2 (V2) is a vector instruction Vl(1)XA2-V3(+) indicating scalar data, the above-described process is repeatedly executed as many times as the number of elements to be processed. In other words, whether all vector elements are used for the operands or scalar data are used for the operands, the processing of the predetermined vector operation specified by the vector instruction word is simply executed repeatedly for the number of elements to be processed. It was only.

[Problems that the invention attempts to solve]

The conventional vector instruction processing device described above simply repeatedly executes a predetermined vector operation specified by a vector instruction as many times as the number of elements to be processed, even if scalar data is used as an operand. Therefore, for example, operand 2 (V2) is a vector instruction Vl (+) However, even in cases where this method is used, there is a drawback that the processing performance of vector operations cannot be easily improved.

In view of the above-mentioned points, an object of the present invention is to provide a vector instruction processing device that can optimize the processing of vector instructions that use scalar data as operands, and can maximize the performance of vector instructions. be.

[Means for solving problems]

The vector instruction processing device of the present invention is an arithmetic processing device that sequentially reads a plurality of vector elements from a storage device and repeatedly executes common arithmetic processing, and includes a type code holding unit that holds a code specifying a type of vector operation; A scalar data check means for checking the value of scalar data when scalar data is specified as an operand, a code for specifying the type of vector operation, and a result of the scalar data check means to change the processing of the vector operation. and processing change means for changing the process.

〔Example〕

Next, the present invention will be explained with reference to the drawings.

FIG. 2 is a block diagram showing an example of the configuration of the entire arithmetic processing device including the vector instruction processing device of the present invention. This arithmetic processing unit includes an instruction control unit 1 that reads and decodes instructions and performs address calculations, a buffer control unit 2 that performs address conversion from logical addresses to real addresses and memory access control, and an arithmetic operation unit that performs instruction operations. 3, a control storage unit 4 which controls each control unit, a vector instruction control unit 5 which is a main part of the vector instruction processing device of the present invention, and which controls the main storage 7, system control and diagnostic control. It consists of a system control device 6 and a main storage device 7.

Note that symbols L1 to L15 are signal lines that connect the above-mentioned parts or devices.

Here, an outline of processing of normal instruction words other than vector instructions will be explained using FIG. The instruction word is stored in the main memory 7, and is sent to the main memory 7 by the instruction control unit 1 via the buffer control unit 2 and the system control unit 6.
A command word is taken into the command control unit 1 from the command line. The instruction word taken into the instruction control unit 1 is decoded by the instruction control unit 1 and the operand address is calculated, the operand is read out by the buffer control unit 2, and then sent to the arithmetic unit 3.
The operation of the instruction is executed.

In the case of a vector instruction as well, the instruction control unit 1 takes in the instruction word and decodes the instruction word as in the case of a normal instruction word.

FIG. 3 is a diagram showing the vector instruction format in the vector instruction processing device of this embodiment.

The instruction code (OP) 201 is an instruction code given in the same way as a normal instruction word, and is C7 in this embodiment.

The vector instruction code (VOP) 205 is a vector operation type code (addition, subtraction, multiplication, division, inner product operation, etc.).
. . . ), a flag (Sl) 207 and a flag (S2) 208 that designate scalar data as an operand.

Flags 207 and 208 correspond to operands 1 and 2, respectively, and when 0 indicates that the operand is a vector element, and when 1 indicates that the operand is scalar data.

Vector descriptor address command base registration number (BR)
203 indicates a base register number, and an adder 230 adds the base address 209 of the vector descriptor address of the contents of this base register and the relative displacement address 204, and specifies the storage address of the vector descriptor address. Ru. In this embodiment, three vector descriptor addresses for operand 1, operand 2, and operand 3 are stored.

Vector descriptor addresses 210 and 211 respectively specify 8 corresponding scalar data 219 and 220 when the corresponding operand is scalar data, and specify vector descriptors 210 and 211 when the corresponding operand is a vector element.

Whether an operand is scalar data or a vector element is indicated by flags 207 and 208, which designate scalar data as the operand, respectively.

There is no scalar data corresponding to operand 3, and vector descriptor address 212 specifies vector descriptor 3. Each of vector descriptors 1.2 and 3 contains the start address 213. of the vector element of the corresponding operand.
215 and 217 and vector element distance 214.21
6 and 218.

For example, considering the case of vl(+)xV2(1)-V3(1), Vl(1), V2(1) and V3
(1) correspond to operands 1.2 and 3, respectively. The start address 215 of the vector element of operand 2 indicates the start address of the vector element of V2 (1), and the distance between vector elements 216 indicates the interval between vector elements of operand 2 that are consecutively arranged at a certain interval. , Therefore, the address obtained by adding the inter-vector element distance 216 to the start address 215 of the vector element indicates the address of the vector element of operand 2 to be used next.

The same applies to operand 1 and operand 3.

FIG. 1 is a block diagram showing in more detail the vector instruction control section 5 which constitutes the main part of the vector instruction processing device of the present invention. This vector instruction control unit 5 has an operation specification register 10
, vector address data registers 11 and 12, vector address register 13, vector element distance registers 21, 22 and 23, scalar data instruction bit 3
1 and 32, scalar data check circuits 41 and 4
2. Vector arithmetic processing change circuit 50, vector buffers 61 and 62, registers 71 and 72, adder 80
, register 81 and selectors 31 to S7.

Vector address data registers 11 and 12 and vector address register 13 store the start address of the vector element and the address of the vector element generated sequentially in advance when the operand is a vector element, and the scalar data when the operand is scalar data. This is a register held for the corresponding operand.

Vector element distance registers 21, 22 and 23 are
This register holds the distance between vector elements corresponding to the start address of the vector element of each operand.

The operation designation register 10 is a register that holds an operation designation part 206 indicating the type code of vector operation.

Scalar data specification bits 31 and 32 are flags 207 and 20 that specify scalar data as operands.
These registers each hold 8.

Scalar data check circuits 41 and 42 are circuits that check the values of scalar data of operands 1 and 2, respectively.

The vector operation processing change circuit 50 receives the output results of the scalar data check circuits 41 and 42 and the operation specification register 1.
This circuit changes the vector operation processing based on the vector operation type code (operation designation part 206) held at 0.

The adder 80 is an address adder that sequentially adds distances between vector elements corresponding to the start addresses of vector elements to sequentially generate addresses of preceding vector elements.

Register 81 is an interface register that receives the address of the vector element generated by adder 80.

Vector buffers 61 and 62 are buffer memories that hold vector elements of preceding operands 1 and 2 read from main memory 7, respectively.

Registers 71 and 72 are interface registers that hold vector elements of operands 1 and 2 read from vector buffers 61 and 62 or scalar data of operands 1 and 2 held in vector address data registers 11 and 12. .

Selectors 81 to S7 are selectors that select input signals as necessary.

Next, the operation of the vector instruction processing device of this embodiment configured as described above will be explained.

First, we will explain the operation in the normal case where operands 1.2 and 3 both indicate vector elements, such as Vl(N x V2(r) = V3(+). In this case, scalar data instruction bits 31 and 32 are both 0.

To pre-read the vector element of operand 2,
The start address 215 of the vector element of operand 2 held in the hector address data register 12 is passed through the selector S4 and the adder 80, and the register 81
, and a request to continue reading the first vector element of operand 2 is sent from the register 81.

Next, in order to generate a read request for the vector element of operand 2 to be read, the start address 215 of the vector element of operand 2 held in the vector address data register 12 and the start address 215 of the vector element of operand 2 held in the vector element distance register 22 are required. The vector element distance 216 of operand 2 is selected by selectors S4 and S5, respectively.
A read request for the vector element of operand 2 to be added and read next by the adder 80 is generated and sent to the register 81 via the selector S2.
The value of the vector address data register 12 is updated via the vector address data register 12.

Thereafter, the adder 80 sequentially adds the address of the vector element of operand 2 in the vector address data register 12 and the vector element distance 216 of operand 2 held in the vector element distance register 22 in the same manner. A read request for the vector element of operand 2 is sequentially generated and sent from the register 81.

A request to continue reading the vector element of operand 2 sent from the register 81 is sent to the buffer tui section 2 via the signal line L3, and the corresponding vector element of operand 2 is read out from the main storage device 7.

The above operation is performed only when the scalar data instruction bit 32 is 0. The generation and sending of requests are the same for operands 1 and 3.

The vector elements of operands 1 and 2 read from the main memory 7 are transferred to the signal line L via the buffer control unit 2.
3 to the vector instruction control unit 5, and stored in vector buffers 61 and 62, respectively.

The vector elements of operands l and 2 stored in vector buffers 61 and 62 are transferred to selector S6, respectively.
The data is read out to the registers 71 and 72 via S7, and supplied to the arithmetic unit 3 via the signal line L4, where a predetermined arithmetic operation specified by the arithmetic operation specification section 206 is performed.

At the same time, vector elements of operands 1 and 2 to be used next are read from vector buffers 61 and 62 to registers 71 and 72, respectively, and are sequentially supplied to calculation unit 3.

The calculation results are sequentially stored in the corresponding address locations of the main storage device 7 under the control of the buffer 1 control unit 2 and the system control device 6 that have received the request for the vector element of the operand 3.

By repeating the above process as many times as the number of elements to be processed, the vector operation specified by the operation specification part 206 in the instruction word is completed.

Note that the operation specification part 206 in the instruction word is
The calculation unit 3 is notified of the decoding of the vector instruction word at step.

Next, the operation when operand 2 is scalar data as in Vl(1)XA2=V3(1), that is, when scalar data instruction bit 311J<O and scalar data instruction bit 32 is 1, will be described.

The operand data held in the vector address data register 12 is controlled by the scalar data instruction bit 32.
The scalar data 220 of operand 2 is sent to the scalar data check circuit 42, and the value of the scalar data 220 of operand 2 is checked. The output result of the scalar data check circuit 42 is sent to the vector operation processing change circuit 50 together with the vector operation type code held in the operation designation register 10.

The vector arithmetic processing change circuit 50 checks whether or not the vector arithmetic process can be changed. If the process can be changed, a vector arithmetic process change request is sent and the vector arithmetic process is changed. The contents are notified from the vector arithmetic processing change circuit 50 to the arithmetic unit 3 via the signal line L4.

Now, Vl(1) where operand 2 is scalar data
In the vector instruction of XA2=V3(+), the scalar data chenok circuit 4
Assume that the output result of checking the value A2 of the scalar data 220 of the operand 2 in step 2 is 0.

In this case, the main memory 7 of the vector element of operand 1
The start address 217 of the vector element of operand 3 held in the vector address register 13 and the inter-vector element distance 218 of operand 3 held in the inter-vector element distance register 23 are suppressed. The adder 80 sequentially adds the addresses via selectors S4 and S5, and the addresses of the vector elements of operand 3 are sequentially generated. The addresses of the vector elements of operand 3 are sequentially supplied to buffer control unit 2 via register 81 and signal line L3.

The arithmetic unit 3 generates O, which is the result of the vector operation, and communicates with the buffer control unit 2, which received the request for the vector element of the operand 3, and the system system? By controlling with the il device 6,
The vector operation results 0 are sequentially stored in the corresponding address locations of the main storage device 7, and the vector operation is completed.

In a vector instruction such as AIXV2(+)=V3(1) or A1+V2(1)-V3(r), the same processing as described above is performed when it is detected that the value of A1 is 0.

others, Vl(1)XA2=V3(1).

AIXV2(1)-V3(1).

In a vector instruction such as Vl(1)÷A2-V3(f), if it is detected that the values of AI and A2 are 1, then Vl(1)=V3(1
) or changed to V2(+)-V3([) hector transfer command.

In multiplication and division vector operations where scalar data is used as an operand, if the value of the scalar data is 2'' and a force < 1 is encountered, a shift operation is used instead of the multiplication and division vector operations. Subject to change.

Next, a vector instruction of SR+ΣAlxA2=SR (inner product operation) in which operands 1 and 2 are both scalar data will be described. SR is a scientific operation register. In this case, the values of SCAR to data indication bits 31 and 32 are both 1.

Under the control of scalar data instruction bits 31 and 32, scalar data Al and A2 held in vector address data registers 11 and 12 are sent to scalar data check circuits 41 and 42, respectively, and the values of scalar data A1 and A2 are checked. Ru.

Now, assume that the results of checking the values of scalar data A1 and A2 are both not 0. The output results of the scalar data check circuits 41 and 42 are stored in the operation specification register 1o.
It is sent to the vector operation processing change circuit 5° along with the vector operation type code held in the vector operation processing change circuit 50, and the vector operation processing change request is sent to the vector operation processing change circuit 50 via the signal line L4. Department 3 will be notified.

At the same time, scalar data A1 and A2 of operands 1 and 2 held in vector address data registers 11 and 12 are read out to registers 71 and 72 via selectors S6 and S7, respectively, and vector operation processing change circuit 50 The signal is supplied to the arithmetic unit 3 under the control of. Selectors s6 and S7 are directed toward vector address data registers 11 and 12, respectively, due to the value 1 of scalar data instruction bits 31 and 32.

The arithmetic unit 3 that has received the scalar data A1 and A2 of the operands l and 2 is connected to the vector arithmetic processing change circuit 50.
According to the new vector arithmetic processing process shown by, first the AlXA2 arithmetic is performed, and the result is multiplied by the value of the number of elements to be processed.

Next, the result obtained from the above operation and the scientific operation register SR
and the result is stored in the scientific operation register SR, and the vector instruction is completed.

If the vector data check circuit 41 or 42 detects that the value of one of the scalar data A1 and A2 is O, the vector arithmetic processing change circuit 50 immediately terminates the vector instruction.

The above-mentioned example is a basic example, and the vector arithmetic processing change circuit 50 prepares various vector arithmetic processing change patterns that can improve the performance of vector instructions that use scalar data as operands. .

VIH)xA where the above operand 2 is scalar data
2=V3(1), if the vector operation processing is not changed, the request for successive vector elements of operand 1 is held in the hector address data register 11, as in normal vector instruction processing. It is generated by the adder 80 sequentially from the start address 213 of the vector element of the operand 1 stored in the operand 1 and the inter-vector element distance 214 of the operand 1 held in the inter-vector element distance register 21, and sent to the buffer control unit 2 via the register 81. The vector elements of operand 1 are sequentially read out from j171 and 7.

In parallel with this operation, the scalar data instruction bit 32 controls the selector S7 to select the scalar data 2 of the operand 2 held in the vector address data register 12.
20 is read into register 72.

When the vector elements of operand 1 begin to be stored in the hector bus sofa 61, operand l is
The vector element of operand l and the scalar data 22 of operand 2 are read out to the register 71.
0 is supplied to the calculation section 3, and a predetermined calculation specified by the calculation specification section 206 is performed.

At the same time, the vector element of operand 1 to be used next is read from the hector bath sofa 61 to the register 71, and the vector element of operand 1 and the scalar data 220 of operand 2 are sequentially supplied to the calculation unit 3.

The operation results are sequentially stored in the corresponding address locations of the main storage device 7 under the control of the buffer control unit 2 and the system control device 6, which have received a request for the vector element of the operand 3, which is sent out in the same way as the operand 1. .

〔Effect of the invention〕

As explained above, the present invention includes a scalar data checking means for checking the value of scalar data, and a processing changing means for changing the processing of a vector operation based on a code specifying the type of vector operation and the result of a scalar data change circuit. By providing this, it is possible to optimize the processing of vector instructions that use scalar data as operands, and there is an effect that the performance of vector instructions can be improved to the maximum.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing in detail a vector instruction control unit that is a main part of a vector instruction processing device according to an embodiment of the present invention, and FIG. 2 is a calculation process including the vector instruction processing device according to an embodiment of the present invention. FIG. 3, a block diagram of the entire device, is a diagram showing the vector instruction format in the vector instruction processing device of this embodiment. In the figure, l...Instruction control unit, 2...Buffer control unit, 3...Arithmetic unit, 4...Control storage unit, 5...Vector instruction Control unit, 6...System control device, 7...Main storage, lO...Operation designation register, 11, 12...Vector address data register, I
3...Vector address register, 21, 22.
23・Vector element distance register, 31, 32...
Scalar data instruction bits, 41, 42...scalar data check circuit, 50...vector arithmetic processing change circuit, 61, 62...vector buffer, 80...adder, ? 1.72.8 register, 81-S7 selector, 201 ・ ・ ・ ・ instruction code, 203 ・ ・
...Base register number, 204 ...Relative displacement address, 205 ...Vector instruction code, 206 ...Arithmetic specification part, 207.208 ...Flag specifying scalar data, 209 ... Base address of vector descriptor address, 210.211.212 ・Vector descriptor address, 213.215,217 ・Start address of vector element, 214.216,218 ・Distance between vector elements, 219.220 ... Scalar data , 230
...It is an adder.

Claims (1)

[Scope of Claim] An arithmetic processing device that sequentially reads a plurality of vector elements from a storage device and repeatedly executes common arithmetic processing, comprising a type code holding means that holds a code specifying a type of vector operation, and a scalar operand. a scalar data checking means for checking the value of the scalar data when data is specified; and a process change for changing the processing of the vector operation based on a code specifying the type of the vector operation and the result of the scalar data checking means. A vector instruction processing device comprising: means.