JPS62149163A - Manufacture of complementary mos integrated circuit - Google Patents

Abstract

PURPOSE:To decrease the number of masks, by forming an element isolating region and a gate electrode, and performing the ion implantations of high and low energies through said regions by using one mask. CONSTITUTION:Element isolating region 2 is formed on an n-type silicon substrate 1 by a selective oxidation method. Then, a gate oxide film 3 is grown, and a gate electrode 4 is formed. Thereafter, the p-channel side is covered with a first ion implanting mask 5. In order to form an n-channel MOS transistor on the n-type substrate, a p-type well 6 is formed by boron implantation at sufficiently high energy. Thereafter, by using the same mask 5, boron ions are implanted for threshold voltage control and a channel doped part 7 is formed, and arsenic is implanted in order to form n<+> source and drain regions 8. Then, a channel doped part 10, p<+> source and drain regions 11, a p<+> region 13, an interlayer film 14 and a wiring 15 are formed.

Description

[Detailed Description of the Invention] [Industrial Application Field] The present invention relates to a method for manufacturing complementary MOS integrated circuits (CMOS), and in particular, reduces the number of masks required for manufacturing and realizes a 0MOS with higher performance than conventional ones. Regarding a new manufacturing method that can be used.

[Conventional technology]

In order to realize 0MOS, it is necessary to form a well, and a method has been proposed in which high-energy ion implantation is performed to bury a high-temperature region inside the substrate to realize a well structure with a lower surface roughness. .

As a conventional technology, the 1981 International Conference on Solid State Devices (I
international Electron 1)e
vices meetin? ) digest pp, 3
46-348 5tephenR, Combs
) Published by K.

[Problem that the invention seeks to solve]

In the conventional manufacturing method described above, after forming the well, N1
(Since the gate electrode and source/drain region of the JS transistor are formed, the ion implantation mask must be patterned each time to form the channel dog and source/drain region that can be used for both threshold voltage and voltage. Therefore, if well formation is included, at least three or four lithography steps are required, which makes the manufacturing method complicated.

[Failure to solve the problem]

In the complementary M (JSS collective circuit manufacturing method of the present invention), after forming the gate electrodes of the first and second conductivity type MOS transistors, the K+1 first conductivity type MIJ8 transistor region is covered with a first ion implantation resistant mask. After performing ion implantation for doping the substrate portion of the second conductivity type MOS and forming source/drain regions of the second conductivity type MOS, and removing the first ion implantation resistant mask, the second conductivity type MOS -yos transistor region is covered with a second ion implantation resistant mask, and ion implantation is performed to add impurities to the substrate portion of the 14th voltage type MOS transistor and to form source/drain regions.

That is, after forming the element isolation region and the gate electrode, K,
Through these regions, well and channel doping is performed by high-energy ion implantation, and source/drain regions are formed by low-energy ion implantation using one mask.

In a preferred embodiment of the invention, channel doping ion implantations are performed multiple times at different energies.

〔Example〕

Next, the present invention will be explained with reference to the drawings.

1+a) to tc) are cross-sectional views of an element according to an embodiment of the present invention.

In the explanation of this embodiment, a case of OMOS in which a p-well is formed on an n-type substrate will be explained.

When forming an n-well on a p-type substrate, it is sufficient to simply change the substrate to p-type and n-type.

In FIG. 1fa), an element isolation region 2 is formed on an n-type silicon substrate 1 by, for example, a selective numbering method.

As an alternative to the selective parallelization method, a groove separation with a depth comparable to the thickness of the thin film can be used. Next, a gate oxide film 3 is grown,
The gate electrode 4 is formed of polycrystalline silicon, a two-layer film of polycrystalline silicon and silicide, silicide, or metal.

Next, as shown in Figure 1(b), the %P channel side is
Cover with an ion implantation mask 5. For example, a photoresist film or aluminum is used as the mask material. In order to form an n-channel (Dog) run sister on an n-type substrate, a 9F well 6 is formed by boron implantation. Boron implantation is performed through the device isolation region and the gate electrode. At this time, since the peak concentration position of boron exists inside the silicon substrate, it is necessary to perform ion implantation with sufficiently high energy. For example, if the thickness of the oxide film in the element isolation region is 05 μm, and the gate electrode is made of polycrystalline silicon with a thickness of 05 μm, the implantation energy is 300 K.
A counterfeit voltage of eV 8 degrees or higher, preferably 500 KeV to IMeV, is required.

Using the same mask 5, channel doping 7 by boron implantation for threshold voltage control and arsenic or phosphorus implantation for forming n+ source/drain regions 8 are performed. By forming the P well 6 shallowly, a desired threshold voltage can be obtained without channel doping 7.

In such a case, channel doping can be omitted. However, channel doping is generally required.

The implantation conditions are such that when ions are implanted through the gate electrode 4, the peak position of the impurity is located near the silicon surface. Furthermore, since this channel dog also functions as a channel stopper in the element isolation region, it is desirable that the peak position of impurities be located near the silicon surface even in the element isolation region. For example, if polycrystalline silicon with a thickness of 0.5 μm is used as the gate electrode and the oxide film thickness of the element isolation region is 0.5 μm, boron implantation may be performed at about 200 KeV. At this time, in the source/drain regions, a peak of boron concentration exists at a distance of approximately 05 μm from the silicon surface.

Therefore, arsenic or phosphorus ions are implanted so that the junction depth of the source and drain is varied by about 0.2 μm. Since the source/drain n+p junction does not exist in a location with a high boron concentration, the junction capacitance can be reduced. CM (The operating speed of J8 is mainly determined by the charging and discharging time to the main capacitor,
Reducing the junction capacitance is advantageous for increasing speed.

Next, as shown in FIG. 1C, the first ion implantation mask 5 is removed and the n-channel side is covered with a second ion implantation mask 9.
cover with A photoresist film, aluminum, or the like is used as the mask material. Since an n-type substrate is used, normally n
There is no need to form wells. If an n-well is effective for improving latch-up resistance and soft error resistance due to α glands, phosphorus ions are implanted at an energy higher than 700 KeV, for example. In the channel dope 10, when ion implantation of phosphorus is performed through the gate electrode, it is desirable that the impurity peak position exists near the silicon surface. For example, in the case of polycrystalline silicon with a thickness of 0.5 μm as the gate electrode, phosphorus ions are implanted at an energy of about 400 KeV.

At this time, if the oxide film thickness in the element isolation region is 0.5 .mu.n1, the peak concentration of phosphorus exists in the vicinity of the silicon forgiving film interface in the element isolation region, so that it also functions effectively as a channel stopper. P source/drain region 11
In this case, the peak concentration of phosphorus exists at +FlO, 5 μm from the silicon surface. Therefore, the source/drain 11
If, for example, BP is implanted to form a junction with a thickness of about 0.2 μm, the P''n junction will be present at a location with a low surface roughness, so that the junction capacitance can be reduced.

Next, as shown in FIG. 1 d), the area other than the contact area of the p-well 6 is covered with a third ion implantation mask, and the p-well 6 is covered with a third ion implantation mask.
To form region 13, 12 polons are ion-implanted.

Next, as shown in FIG. 1(e)K, an interlayer film 14 is grown and contacts are formed in ffM15, which will be described later.

Thereafter, an integrated horizontal circuit can be realized using a normal CMOS process.

Another embodiment of the invention is shown in FIG. FIG. 2(a) shows an SOI substrate having a three-layer structure of silicon 11/silicon dioxide 12/silicon 13, and FIG.
), and corresponding parts have the same reference numbers! . Since each transistor is completely electrically isolated from other transistors, there is no need to form a contact portion to ground the well region.

FIG. 3 shows the impurity distribution in the channel region, source/drain/region, and element isolation region of an n-channel MOS transistor. In this example, pEl is 600Ke
V at l
2 boron, AS for source and drain, 7QKe
2×IQ”c!IL-”2 ions are implanted at V. The substrate used is an n-type substrate doped with phosphorus in the form of lXIQl'' (m3).

The surface 11 was implanted with high energy boron at 600 KeV.
An ideal impurity distribution with a low value of 1 is achieved. In the source/drain regions, since the channel dope penetrates, the n+ source/drain formed by arsenic implantation forms a junction in the low concentration portion. Therefore, the junction capacitance is reduced. Small junction capacitance is advantageous for high speed operation. In the element isolation region, a sufficiently high surface concentration is obtained by channel doping, and the generation of nuisance channels is prevented.

In the embodiment shown in FIG. 1, a p-well is formed in an n-type substrate. The present invention is not limited to this, and even when forming a p-well and an n-well on an n-type substrate, or a p-well and an n-well on a p-type substrate, it is only necessary to change the ion implantation as appropriate.

In the manufacturing method of the present invention, channel doping is performed through the gate electrode. Therefore, variations in the gate electrode film directly vary the threshold voltage.

To solve this problem, multi-channel doping is performed.

Multi-channel implantation with different energies allows channel doping to be resistant to variations in gate electrode thickness. FIG. 4 shows a comparison of the effects of variations in gate electrode film thickness on the threshold voltage in the cases of -times implantation and triple implantation. With triple implantation, the threshold voltage variation is significantly improved.

〔Effect of the invention〕

As explained above, the present invention can achieve 0M using only 7 masks.
OS can be manufactured. Furthermore, since the storage volume of the source/drain diffusion layer is reduced, the operating speed is increased. Further, in the well according to the present invention, since the impurity peak occurs once inside the substrate, the total amount of impurities in the well can be larger than in the conventional well. Moreover, since the well is shallow, there is little lateral spread. Therefore, it is advantageous for miniaturization and has the effect of high latch-up resistance.

By using the manufacturing method according to the present invention, a high-speed, high-density 0MOS can be realized in a short manufacturing process.

[Brief explanation of drawings]

FIG. 1 is a cross-sectional view of an element for explaining the present invention in detail, FIG. 2 (ta) and tb) are cross-sectional views showing other embodiments of the present invention, and FIG. The impurity distribution diagram of 0MOS, FIG. 4, is a graph which is sufficient to explain the present invention in detail. 1...N-type/recon substrate, 2...Element isolation region, 3...Gate formation film, 4...
・Gate electrode, 5...First ion implantation mask, 6
...p-well, 7...channel dope, 8...n+ source drain/, 9...
...Second ion implantation mask, 10...Channel doping, 11...P+ source/drain, 1
2...Third ion implantation mask, 13...
・P+ region, 14... Interlayer film, 15...
・Marriage. Agent Patent Attorney Shinkan Uchihara t Figure ELL $ 2 Figure! Siribon Kaedama (斥) (μBO)

Claims (3)

[Claims] (1) Complementary MO consisting of a first conductivity type and a second conductivity type MOS transistor on one main surface of a single crystal silicon substrate
In forming the S integrated circuit, after forming the gate electrodes of the first and second conductivity type MOS transistors, the first conductivity type MOS transistor region is covered with a first ion implantation resistant mask, and the second conductivity type MOS transistor region is covered with a first ion implantation resistant mask. A process of adding impurities to the substrate of a type MOS transistor and performing ion implantation for forming a source/drain region, and after removing the first ion implantation resistant mask, implanting the second conductivity type MOS transistor region into a second ion implantation resistant mask. A method for manufacturing a complementary MOS integrated circuit, comprising the step of covering with an implantation mask and performing ion implantation for doping a substrate portion of the first conductivity type MOS transistor and forming a source/drain region. (2) The thickness of the gate electrode and the thickness of the element isolation region of the complementary MOS integrated circuit are determined by the range in the gate electrode and the thickness in the element isolation region when boron or phosphorus is ion-implanted with a certain energy. A method for manufacturing a complementary MOS integrated circuit according to claim 1, wherein the range is approximately the same as the range of . (3) Ion implantation for adding impurities to the substrate portions of the first and second conductivity type MOS transistors is performed multiple times at different energies.
) A method for manufacturing a complementary MOS integrated circuit according to item 1.