JPS62111872U - - Google Patents
Info
- Publication number
- JPS62111872U JPS62111872U JP23986U JP23986U JPS62111872U JP S62111872 U JPS62111872 U JP S62111872U JP 23986 U JP23986 U JP 23986U JP 23986 U JP23986 U JP 23986U JP S62111872 U JPS62111872 U JP S62111872U
- Authority
- JP
- Japan
- Prior art keywords
- substrate
- memory
- pack case
- memory elements
- circuit
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 230000002093 peripheral effect Effects 0.000 claims 2
- 239000000758 substrate Substances 0.000 claims 2
- 230000037431 insertion Effects 0.000 claims 1
- 238000003780 insertion Methods 0.000 claims 1
- 230000013011 mating Effects 0.000 description 1
Landscapes
- Credit Cards Or The Like (AREA)
Description
第１図ａは本考案の１実施例に係るメモリカー
ドの平面図、第１図ｂは第１図ａの側面図、第１
図ｃは第１図ａのメモリカードに対して切欠き位
置が異なる場合の本考案の実施例の平面図、第２
図ａは装置本体側接続部の平面図、第２図ｂは第
２図ａの接続部に対してピン位置が異なる場合の
装置本体側接続部の平面図、第３図は正常嵌合状
態における本考案のメモリカードの平面図、第４
図および第５図はそれぞれ誤実装時におけるメモ
リカードの平面図である。
１，１′…メモリカード、２…基板、３，３′
…フレーム、４…接続接栓、５，５′…切欠き部
、６，６′…装置本体側接続部、７…接栓受口、
８，８′…ピン。
FIG. 1a is a plan view of a memory card according to an embodiment of the present invention, FIG. 1b is a side view of FIG. 1a, and FIG.
Figure c is a plan view of an embodiment of the present invention in which the notch position is different from that of the memory card in Figure 1a;
Figure a is a plan view of the connecting part on the device main body side, Figure 2 b is a plan view of the connecting part on the device main body side when the pin position is different from the connecting part in Figure 2 a, and Figure 3 is a normal mating state. 4th plan view of the memory card of the present invention in
FIG. 5 is a plan view of the memory card when it is incorrectly mounted. 1, 1'... Memory card, 2... Board, 3, 3'
... Frame, 4... Connection plug, 5, 5'... Notch, 6, 6'... Device main body side connection part, 7... Connection socket,
8, 8'...pin.
Claims (1)
るメモリ回路を基板上に形成し、前記基板に前記
メモリ素子とのリードライトデータバスおよび前
記周辺回路の制御信号線を配置した接続接栓を設
け、前記基板をパツクケースで包囲してパツク化
したメモリカードにおいて、前記パツクケースに
装置本体への誤挿入防止用係止手段を形成したこ
とを特徴とするメモリカード。 A memory circuit having a plurality of memory elements and their peripheral circuits is formed on a substrate, a connection plug is provided on the substrate in which a read/write data bus with the memory elements and a control signal line of the peripheral circuit are arranged, and the 1. A memory card in which a board is packaged by surrounding it in a pack case, characterized in that the pack case is provided with a locking means for preventing erroneous insertion into an apparatus main body.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP23986U JPS62111872U (en) | 1986-01-06 | 1986-01-06 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP23986U JPS62111872U (en) | 1986-01-06 | 1986-01-06 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS62111872U true JPS62111872U (en) | 1987-07-16 |
Family
ID=30777029
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP23986U Pending JPS62111872U (en) | 1986-01-06 | 1986-01-06 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS62111872U (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US8882018B2 (en) | 2011-12-19 | 2014-11-11 | Sidergas Spa | Retainer for welding wire container and welding wire container with retainer |
-
1986
- 1986-01-06 JP JP23986U patent/JPS62111872U/ja active Pending
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US8882018B2 (en) | 2011-12-19 | 2014-11-11 | Sidergas Spa | Retainer for welding wire container and welding wire container with retainer |
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