JPS6169094A - Graphic processing method and apparatus - Google Patents

Abstract

(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

[Detailed Description of the Invention] [Field of Application of the Invention] The present invention relates to a graphic processing method and apparatus for creating one graphic data, and in particular, to a graphic processing method and apparatus for creating one graphic data, and in particular, to a graphic processing method and apparatus that enables conditional drawing operations for color display, two-gradation display, etc. The present invention relates to a processing method and apparatus.

[Background of the invention]

2. Description of the Related Art Many graphic systems that display characters and figures on a screen such as a CRT display a color or multi-gradation display. In such a system, it is necessary to select which one to display when multiple figures with different colors and gradation data overlap.

In other words, the depth relationship between the figures is determined by how they are displayed in this overlapping area, and different selections result in completely different appearances.

The most convenient conventional method for making this possible is to select the drawing order of figures through software processing. In other words, the drawing is performed in order starting from the figure that should be in the back, and the figure that is closest to the front is drawn last, and in the overlapping area, the figure that was drawn later is drawn in the foreground.However, this method To change the display method, it is necessary to change the software and the drawing order each time, which is time-consuming. Furthermore, since the drawing order is defined, it is difficult to write programs for complex figures.

Furthermore, it is difficult to apply this method to video processing in which only part of a figure is changed sequentially while leaving the background image unchanged.)

For this, the priority level of one figure is memorized and the CRT
A method using dedicated hardware that switches the color data when changing the epidermis to
It is disclosed in the publication No. However, this method has the problem that it cannot handle complex figures because it can only operate on a limited number of coordinate values.

On the other hand, in high-end graphics systems that display three-dimensional figures, the above problem is discussed as the problem of hidden line erasure or hidden surface erasure, for example.

Although it is disclosed in Japanese Patent Publication No. 5G-46026, it requires large-scale hardware and is not easy to implement.

As mentioned above, software methods are inexpensive but have limited functionality and performance, while hardware methods provide high performance but are expensive.

[Purpose of the invention]

The object of the present invention is to provide a graphic processing method and method for high-speed processing of conditional drawing operations on color and gradation data with a relatively simple configuration, with the aim of incorporating it into an LSI that can be applied to systems ranging from inexpensive to high-end systems. The purpose is to provide equipment.

[Summary of the invention]

The features of the present invention for achieving the above object include means for comparing pixel data represented by a single bit or a plurality of bits with other data, and performing an operation between created pixel data and externally read pixel data. and a means for controlling pixel data calculation based on the comparison result.

[Embodiments of the invention]

DETAILED DESCRIPTION OF THE INVENTION Preferred embodiments of the present invention will be described below with reference to the drawings, but first, matters on which the present invention is based will be described.

The matters forming the basis of the present invention will be explained below.

The present invention is as follows.

First, one pixel is represented by (a) one bit, and (b) two bits.

(G) 4-bit expression, (d) 8-bit expression, and (s) 16-bit expression.
(See Figure 9).

Second, it uses pixel addresses. Therefore, this pixel address is composed of address information MAD that specifies the address of one display memory, and one-word address information WAD that specifies the position within one word specified by that address. (See Figure 10).

Third, one word of display data at the display memory address specified by the address information in the pixel address is read from the display memory, and then the display data specified by the one-word address information in the pixel address is read. Only a predetermined bit part of the image data is rewritten and then written again to the corresponding address part of the display memory, so that multiple bit data for one pixel can be processed simultaneously.

Next, examples of the present invention will be described.

Further, in the following description, the same reference numerals indicate the same objects.

FIG. 3 is a block diagram showing an example of a device to which a graphic processing device according to the present invention is applied.

In FIG. 3, the graphic processing device includes an arithmetic device 30 that controls writing, rewriting, and reading of display data in the display memory 13, and a control device i! that controls the arithmetic device 30 in a fixed order. 2o. Further, display data read out from the display memory 13 by the graphic processing device is converted into a video signal by the display conversion device 40 and displayed on the display device 50.

The arithmetic unit 30 sequentially calculates a pixel address consisting of an address in the display memory 13 and information specifying a pixel position in one word of display data in the display memory 13, and displays the pixel address at the calculated pixel address. One word of display data in the display memory 13 is read out from the address information in the display memory 13.The display data thus read out is decoded based on the pixel position designation information at the pixel address. With the information specifying a plurality of bit positions corresponding to the specified pixel position formed by the process, a drawing logic is calculated only for the bits of a predetermined pixel of the display data, and the result of the logical operation is written again to the display memory 13. This is what I did.

Note that 60 is an external computer, and the graphic processing device operates according to control data from this external computer 60.

FIG. 4 is a block diagram showing an embodiment of a graphic processing apparatus according to the present invention.

In the figure, a control device 20 includes a microprogram memory 100 and a microprogram address register 1.
10, a return address register 120, a microinstruction register 130, a microinstruction decoder 200, a flag register 210, a pattern memory 220,
The instruction control register 230 is configured to include an instruction control register 230.

Further, the calculation device 30 is a calculation control device 300.

First-In, First-Out
(FIFO)) Memo IJ400.

Each component is used in normal digital control and does not require any special explanation. However, according to this embodiment, the arithmetic control device 300 includes a logical address arithmetic unit (A unit) 310° and a physical address arithmetic unit (A unit) 310°. A calculation section (B unit) 320 and a color data calculation section (C unit) 330
It is composed of.

The A unit 310 mainly calculates where the drawing point is located on the screen according to the drawing algorithm, the B unit 320 calculates the necessary address of the display memory, and the C unit 330 calculates the color data to be written to the display memory. It is calculated.

FIG. 5 shows an example of the configuration of a display device that displays one pixel with 4 bits, and shows a configuration in which display data specified by the graphic processing device of FIG. 4 is displayed on the display device 50. has been done.

In FIG. 5, Do of the display data DT read out from the display memory 13 based on the address AD command from the graphic processing device (FIG. 4).

D, , D, , D, □ are supplied to a 4-bit parallel-to-serial converter 410 in the display conversion device 40. This converter 41
A video signal VDO is obtained from 0. Similarly, D□ and Dl of one display data DT.

D, ,D, , are supplied to a parallel-to-serial converter 420 in the display conversion device 40, and the video signal VDI is supplied from this converter 420.
Of the 0 display data DT obtained, ,D,,D
Engineering. , D14 to a parallel-to-serial converter 430 in the display conversion device 40, and from this converter 430 the video signal VD2 is supplied.
is obtained. Also, out of 1 display data DT, ,D
,,D 1. Dl, is supplied to a parallel-to-serial converter 440 in the display conversion device 40, and a video signal VD3 is obtained from this converter 440. The video signal VDO-VD3 is sent to the video interface circuit 450 that constitutes the display conversion device 4o, and is sent to the display device 50 after undergoing processing such as color conversion and DA conversion.
will be displayed at

Next, the specific configuration of each unit of the arithmetic and control device 300 will be explained with reference to FIGS. 6 to 8.

Logical address calculation section 3, which is unit A in FIG.
10 is as shown in FIG.
FBUF) 31.01, general-purpose register 3102,
Area management registers 3103 and 3105, area judgment comparator 3104, end point register 3106, end judgment comparator 3107, source latches 3108 and 3109
, an arithmetic logic unit (ALU) 3110, a destination latch (DLA) 3111, a bus switch 3112, read buses (UBA, UBB) 3113 and 3114, and a write bus (WB A) 3115. .

In FIG. 7, the physical address calculation section 320, which is the B unit, has a destination latch (DLB) 32.
01, arithmetic unit (AU) 3202, source latches 3203 and 3204, and offset register 320
5, screen width register 3206, and command register 3
207, general-purpose register 3208, and read bus (UB
B) 3209 and write buses (WB B) 3210 and 1. Furthermore, the general-purpose register 32
08 is the current address register (D
P.H.

DPL) and word unit command address register (RW
PH, RWPL), working registers (T, H.

T2L).

Furthermore, in FIG. 8, the color data calculation unit 330, which is the C unit, includes a barrel shifter 3301, a color register 3302, a mask register 3303, a color comparator 3304, a logical operator 3305, a write data buffer 3306, Pattern RAM buffer 330
7, a pattern counter 3308, a pattern control register 3309, a read data buffer 3310,
Memory address register 3311 and memory output bus 3
312 and a memory input bus 3313. The mask register 3303 consists of a register (CMSK) and a register (GMSK).

The operation of the embodiment configured as described above will be explained.

First, the basic operation of each element will be explained. Control data CDT such as commands and parameters sent from another device such as a central processing unit is written to the memory 400 on the one hand, and directly to the command control register 230 on the other hand.

The register 230 stores various graphic bit modes, and as described later, according to this embodiment, one of five pixel modes can be selected. This selection can be made with the usage data CDT.

The memory 400 is a so-called “First-In, F
irst-Out" (hereinafter also referred to as FIFO) memory.

The instructions stored in the memory 400 are read by the arithmetic control section 300 and stored in a register within the arithmetic control device 300. Further, part of this instruction information CID is transferred to the address register 110.

Address register 110 is microprogram memory 1
00 address is managed, and this address is updated in synchronization with the clock. Microprogram memory 10 according to the address output from address register 110.
0 to 13 as shown in Figure 13.
The command read from the memory 100 consists of 48 bits as shown in FIG. 13, and one of control modes #0 to #7 can be selected. The command is then temporarily stored in the register 130, and via the decoder 200 which operates according to the mode selected by the register 230, a predetermined control signal CcS is generated to control each part of the arithmetic control device 300. Here, the function of each field of the microinstruction shown in FIG. 13 will be explained.

In FIG. 14, rRUJ is an instruction that specifies a register connected to the UBA bus 3113.

rRVJ is an instruction that specifies a register connected to the VBA bus 3114. rRWJ is an instruction that specifies a register into which data on the WBA bus 3115 is written.

rFUNcA J is arithmetic logic unit 3 of A unit
This is an instruction that specifies 110 operations. rsFTJ is a shifter (SPTA) added to the source latch 3108
This is an instruction that specifies the shift mode of . rADF-LJ
is an instruction that specifies the lower 4 bits of the next address to be returned to the microprogram address register 110. r
AcJ is a command that controls the next address after the microphone and mouth commands. rADF-HJ is an instruction that specifies the upper six bits of the next address returned to the microprogram address register 110. Furthermore, the upper 6 bits of the address cannot be updated in each of the microinstructions #4 to #7.

rFUNcB J is an instruction that specifies the operation mode of the arithmetic operation unit 3202 of the B unit. rEC:DJ is an instruction that specifies execution conditions of an operation. rBcDJ is an instruction that specifies branch conditions. rFLAGJ is an instruction that specifies reflection of a flag in the flag register 210. rVJ is an instruction specifying whether or not to test whether access to the display memory 13 is possible. r FIFOj is an instruction that controls reading and writing to the FIFO 400.
rLITERAL J is an instruction that specifies 8-bit literal data. rLcJ is an instruction that specifies the literal data generation mode.

rFFJ is a set of special flip-flops for each part.

This is a command to control reset. "S" is an instruction specifying selection of a code flag. rMcJ is table f
This is a command for controlling reading and writing of the display memory 13. rDRJ is a command that controls scanning of the pattern RAM. rBcJ is an instruction that controls the input path to the arithmetic operation unit 3202 of the B unit.

rRBJ is an instruction to select the read/write register of the B unit.

The micro-instructions include the above-mentioned instructions, by which the control device 20 controls the arithmetic device 30.

Note that the return address register 120 stores the return address of the subroutine. Flag register 210 stores various condition flags. Pattern memory 220 stores basic patterns used for graphic processing.

Now, the operation of storing image data in memory will be explained, but before that, the bit layout of each data used in this embodiment will be explained.

First, the graphic mode will be explained.

In this embodiment, five different operating modes can be selected according to the designation of the graphic bit mode (GBM) stored in the command control register 230.

FIG. 9 shows the bit configuration of one word of the display memory in each mode.

(a) 1 bit/pixel mode (GBM="000") This is a mode used when expressing one pixel with one bit, such as in a black and white image, and one word in the display memory consists of 166 consecutive pixels. The data will be stored.

(b) 2-bit/pixel mode (GBM=OO1) This mode expresses one pixel with 2 bits, and can be used for display of up to 4 colors or 4 gradations. therefore,
One word of the display memory 13 can store data of eight consecutive pixels.

(c) 4-bit/pixel mode (GBM=010) In this mode, one pixel is expressed by 4 bits, and data for four consecutive pixels can be stored in one word of data in one display memory.

(d) 8-bit/pixel mode (GBM=011) In this mode, one pixel is expressed with 8 bits, and data for two pixels can be stored in one word of one display memory.

(e) 16-bit/pixel mode (GBM=100) In this mode, one pixel is expressed with 16 bits, and one word in the display memory corresponds to one pixel data.

Next, pixel addresses will be explained.

FIG. 10 explains pixel addresses corresponding to each mode in FIG. 9. The register 3208 of the physical address calculation unit manages a bit address (physical address) BAD, which is a memory address with four lower bits added. The lower 4 bits of information WAD are used to specify the pixel position within one word, and operate according to each bit/pixel mode.

In the figure, 'skewer' marks indicate bits that are irrelevant to the operation.

FIG. 11 shows the "4 bit/pixel mode" in section (c) above.
This figure shows the spatial arrangement of the display memory as an example. The memory address is assigned as a linear address as shown in the memory map in Figure (A), and the width of the 0 screen displayed as a two-dimensional image as shown in Figure CB) is determined by the screen width register (MW) in Figure 7. ) 3206, and this MW indicates how many bits the width of the screen consists of. Therefore, in the case of 4 bits/pixel mode, MW/4 pixels are displayed in the horizontal direction. Furthermore, since one pixel is displayed using 4 bits, data for one word is displayed as data for four consecutive pixels in the horizontal direction, as shown in FIG. 11(C). The offset generation circuit 2001 in FIG. 7 generates an offset value of "4" and stores it in the offset register. Therefore, it can be seen that in order to move the physical address by one pixel in the horizontal direction, it is sufficient to add or subtract the offset value. Furthermore, to move by one pixel in the vertical direction, the value of the register (MW) 3206 may be added or subtracted.

An example of the bit layout of data used in this embodiment has been described above.

Next, the operation of storing image data in the display memory 13 using these data will be explained.

r Control data CDT such as commands and parameters sent from an external central processing unit is written to the memory 400 on the one hand, and written to the command control register 230 on the other hand. A case will be described in which the designated graphic bit mode (GBM) is, for example, 4 bits/1 pixel -T--1-' (GBM=010).

When the graphic bit mode (GBM) is specified as 4 bits/pixel by the instruction control register 230, one word of data in the display memory 13 is divided into four bits as shown in FIG. It will be treated as such.

CDTs such as commands and parameters from an external central processing unit are stored one after another in the memory 400. The data stored in the memory 400 is taken into the FIFO buffer 3101 by the A unit 310. The operation of the A unit 310 will be explained below. The data taken into this FIFO buffer 3101 is exchanged with an internal bus 3113 and stored in each necessary register. This is transmitted from the bus to the logic operator 3110 via the lease latch 3109.
The signal is inputted to , a predetermined calculation is performed, and the result is temporarily stored in a destination latch (DLA) 3111 . This result is.

It is stored in general-purpose register 3102. This general-purpose register 3102 stores the current coordinate point in the coordinate space.

Current X-Yfiill in general register 3102
is read from one of the read buses 3113 and 3114, and the arithmetic logic unit (A L u ) 31
10 is input. This computing unit (A L u ) 31
10 is stored again in the general-purpose register 3102 via a destination latch (DLA) 3111 and a write bus 3115. These series of operations will be executed according to the instructions of the microprogram shown in FIG.

Furthermore, the data on the write bus 3115 is input to the area management registers 3103 and 3105, and the area judgment comparator 3
104 for comparison. The comparator 3104 determines whether the data on the write bus 3115 is between the minimum value of the X-axis and the maximum value of the X-axis, or the minimum value of the Y-axis and the maximum value of the Y-axis. The determination result is sent to the flag register 210.

Further, the data on the write bus 3115 is stored in the end point register 3106, and is passed through the end point register 3106 to the end point register 3106.
07 is input. In the end determination comparator 3107.

The end points of the X-axis and Y-axis stored in this register 3106 in advance are compared with the data on the write bus 3115, and it is detected whether the end points match the data. The comparison detection result is reflected in the flag register 210.

As described above, comparators 3104 and 3107, arithmetic unit 3
The results of 110 are collected in flag register 210.

The data is then input to the microinstruction decoder 200 and used to change the flow of the microprogram.

As described above, the A unit 310 operates by decoding the x-y coordinate values given by the parameters and interpreting commands such as drawing a line or drawing a circle, respectively.

Next, the operation of the B unit 320 will be explained.

The data interpreted by A unit 310 is stored in register 320.
8 is input. Data in the register 3208 is input to an arithmetic unit (AU) 3202 via a read bus 3209 and a source latch 3204. This computing unit 3202
The result calculated in is the destination latch 320.
1, and each bus 3113.3114.32
It can be output to 09 and 3210. Here, bus 321
0 to the register 3208. The register 3208 consists of two 16-bit 1 word registers.
It has a word structure and stores a physical address in one word with a total of 32 bits. The register 3208 has three types of 32-bit registers and can store three types of data. That is, the register DP of the register 3208 stores the physical address of the actual drawing point corresponding to the current drawing point xY. Therefore, when the XY coordinates of the register 3102 of the A unit 310 move, the physical address of the register DP moves correspondingly. Hibiki f′ Changing the physical address is
In the axial direction, a variably settable predetermined value (offset value x value up to the desired point to be moved) may be added or subtracted to the original physical address, and a predetermined value in the Y@force direction may be added or subtracted. That is, the offset generation circuit 20
Based on the information specified by 01, a constant for moving the pixel address by one pixel in the horizontal direction is set in the offset register 3205. By calculating this constant and data in the arithmetic unit 3202, the physical "address" after horizontal movement is calculated. For example, if the pixel mode is "
In the 1 bit/pixel mode, the constant may be 1, and moving one pixel results in a shift of only one bit. This is “4
In the bit/pixel mode, the constant is 4, and moving one pixel results in a shift of 4 bits.

Further, in order to move vertically by one pixel, the constant set in the screen width register 3206 is calculated, and the movement by one pixel becomes possible.

As described above, the B unit 320 operates to obtain an actual physical address corresponding to the X-Y coordinates determined by the A unit 310.

Next, the operation of the C unit 330 will be explained.

The C unit 330 is connected to the display memory 13 shown in FIG. 11 through an output bus 3312 and an input bus 3313. To the output bus 3312, the C unit 330 first outputs the address information AD, and then outputs the data DT.

First, address information AD passes through B unit 320,
and is written to the memory address register 3311 via the UBB bus 3209;
1 (MARL) and (MARH).

When the memory address stored in this register 3311 is sent to the display memory 13 via the output bus 3312, the display data DT of one word specified in the memory 13 is sent from the display memory 13 via the input bus 3313. is read out. The read display data DT is stored in the read data buffer 3310.

Here, if the display data DT draws a figure, the arithmetic unit 33
Next, microphone information (information specifying which bit of one word is to be masked) from the mask register 3303 is input to the arithmetic unit 3305. In addition, mask information is available from WBB
Register written directly from bus 3201 (CNSK)
, or from a register (GMSK) that stores data generated by address decoder 2002 within one word.

In addition, color information is selected by a color register 3302 and provided to an arithmetic unit 3305. Then, in the arithmetic unit 3305.

A logical operation is performed based on the data DT, mask information, and color information, and the result of the operation is output to the write register 3306. Note that one color information and pattern information are transferred from the pattern RAM 220 to the pattern RAM buffer 330 by being specified by an address signal formed by the pattern counter 3308 and drawing pattern register 3309.
7 is stored. This is taken into the color register 3300 or directly input to the arithmetic unit 3305.

In this manner, the C unit 330 operates to perform conversion processing on color information.

Next, the drawing calculation method will be explained. Figure 12 shows 4 bits/
This is a diagram schematically showing the flow of drawing calculations for one pixel in pixel mode.

Drawing pattern register 3309 and pattern register 3
The pattern RAM 22 is stored by the address specified in 308.
The data read from 0 is stored in the pattern RAM buffer 33.
07 and selects the color register 33o2. In addition, data (C, , C,
, C, , C4) are stored in the read data buffer 3310. Color data and data are each 4-bit color information or gradation information. One bit of pattern information is read from the pattern memory 220, and color register O or color register 1 is selected depending on the data "O" or '1' and is supplied to the logical operator 3305.Memory address register 331
The lower 4 bits of the physical address information stored in 1 are "10 kushiken" in the figure, and this information is obtained by the 1-word address decoder 2002 and the master register 3303 generates mask information GMSK. On the other hand, Mef
The upper field excluding 7th field 'XL'5'3311 (7) Lower 4':' is output as a display memory address, and ill in the display memory 13 is read out.In the logic operator 3305, the mask register 3303 A logical operation is performed only on the part specified by the "1" bit of GMSK, and write data cy is obtained and stored in the write buffer 3306.Here, as for the type of logical operation of the arithmetic unit 3305, the color register Replacement with value, logical operation (A
ND, OR, EOR), conditional drawing (drawing only when the readout color satisfies a predetermined condition), etc., and GM that occurs when the bit/pixel mode is other modes.
Similar calculations are performed, only the SK information is different. Then, the address information AD and data DT are again sent in this order from the address register 3311 and the register 3306 to the output bus 3312 and written to a predetermined address in the display memory 13.

In this way, according to this embodiment, one pixel worth of data can be updated at a time by one read, update, and write process. This makes it possible to draw with high processing efficiency. Also, 16
Even in cases other than bit/pixel mode, multiple pixel data is packed into a 16-bit length for processing, resulting in high memory usage efficiency and high data transfer efficiency between other devices and display memory. In this embodiment, there are five operation modes for different bit lengths per pixel, resulting in a highly versatile configuration. - Next, the above-mentioned conditional drawing method will be explained in detail.

FIG. 1 shows the configuration of a portion related to conditional aggregation in one embodiment of the present invention, and includes the following components. In particular, the color comparator 3304 and the flag register 210 are important parts of the present invention.

(1) Color comparator 3304 Based on the master data from the master register 3303, data for one pixel is extracted from each data from the read data buffer 3310 and the color register 3302 and compared.

(2) Logic operator 3305 Based on the master data from the mask register 3303,
Read data buffer 3310 and color register 3
A logical operation or an arithmetic operation is performed on data for one pixel between each data from 302.

(3) Color register 3302 This is a register group that stores various color information such as drawing color data and comparison color data.

(4) Master register 3303 This is a group of registers that stores mask data (GMSK) corresponding to pixel information and mask data (CMSK) that can be arbitrarily set from the central processing unit or other control device.

(5) Read data balance 3310 This is a register that temporarily stores data read from a memory that stores graphic information.

(6) Write data buffer 3306 This is a register that temporarily stores the calculation result of the logical operator 3305 and outputs it to the memory that stores graphic information.

(7)-According to the number of bits allocated to the address decoder 20021 pixel in the brain, it generates mask data for cutting out data for that one pixel, and the mask register 330
3^ Output.

(8) Flag register 210 Controls the logical operator 3305 according to the comparison result from the color comparator 3304 and the operation mode stored in the command register 3207.

The pixel data comparison and arithmetic processing performed by the color data calculation unit 330 are performed according to instructions from the central processing unit or other control device.

A series of operations when comparing and calculating pixel data operates as shown in the first order.

1i from an external memory (not shown) that stores graphic information.
Read the data of I, read data buffer 3310
to be memorized. The stored 1iI data includes single or multiple pixel data. This data is sent to color comparator 3304. At this time, color comparator 3
304, 1 from memory address register 3311
The address decoder 2002 within one word uses the address information indicating the pixel position within the word and the information indicating the number of bits representing one pixel from the instruction control register 230.
Mask data is generated and sent to the mask register 3303 for storage. Also, according to the control signal, the color register 3
Comparison data is selected from 302 and color comparator 330
Sent to 4. Color comparator 3304 compares comparison data and data from read data buffer 3310 based on mask data from mask register 3303. The comparison result is output to flag register 210. The logical operator 3305 processes the drawing color data selectively output from the read data buffer 3310 and the color register 3302 into the mask register 3.
Based on the mask data from 303, mask processing of one pixel data is performed, and pixel data calculation is performed. This calculation result is stored in the write data buffer 3306 and written to the memory where the original graphic information is stored.

The 1mth embodiment has a function that can efficiently process even when data of one pixel is expressed by multiple bits (multiple colors or multiple gradations), and the graphic bits stored in the instruction control register Five different operating modes can be selected according to the mode settings.

This is as explained in FIG. 9.

FIG. 14 shows, for example, the relationship between the mask data generated by the address decoder 2002 in one word and the bit address output from the memory address register 3311 in the 4-bit/pixel mode.

When comparing or calculating bits 4 to 7 of pixel data, bit address 4 is generated in lower bit 4 of memory address register 3311. in this case.

-The mask generated by the address decoder 2002 in the sea
In the data, tt 1 pp is set only in bits that perform pixel data comparison or calculation, and "0" is set in bits that do not perform pixel data comparison or calculation. That is, when the bit address is "4", the bit address shown in FIG.
) is generated and the mask data is stored in the mask register 33.
It is stored in GMSK 03.

FIG. 2 shows the operation mode of pixel data according to two embodiments of the present invention.
Modes O to 3 are modes in which pixel data operations are performed without comparison, and operation modes 4 to 7 are modes in which pixel data are compared and execution of pixel data operations is determined based on the results. This will be explained in detail below.

(1) Operation-Mode 0 The logical operator 3305 executes arithmetic processing to replace the drawing color data of the selected color register 3302 with the data of one pixel of the drawing point.

(2) Operation mode 1 Similar to operation mode 0 described above, the logical operation "OR" is performed between the color data from the color register 3302 and the data for one pixel of the read data buffer 3310. It is executed by the device 3305.

(3) Operation mode 2 Similar to operation mode 1, logical operation "AND" is performed on one pixel data.

(4) Operation mode 3 Similar to operation mode 1, logical operation "EOR" is executed on one pixel data.

(5) Operation mode 4 This is a mode in which drawing is permitted only for a specific color specified in advance. Selected color register 3302
comparison color data and read data buffer 33
Color comparator 3 compares the drawing pixel data from 10
304. As a result, color register 3302
Comparison pixel data from and read data buffer 331
When 1 pixel data of a drawing point starting from 0 is equal, arithmetic processing of changing 1M for 1 pixel data of a drawing point with the drawing color data from the selected color register 3302 and data from the read data buffer 3310. is executed by the logical operator 3305. If the comparison results are not equal, no pixel data calculation is performed.

(6) Operation mode 5 This is a mode in which drawing is prohibited for a specific color.Similar to operation mode 4, one pixel data is compared in the color comparator 3304, and the results are f', 7,
. L<2b, 2o1. -Wow, caw-.

- Execute a pixel data operation to replace one pixel of the drawing point of the data from the data buffer 3310 and the read data buffer 3310 using the logical operator 3305. If the comparison results at the 0 pixel data comparator are equal, the operation on the pixel data is performed. Don't do it.

(7) Operation mode 6 The color comparator 3304 compares one pixel data of each of the drawing color data from the selected color register 3302 and the color data from the read data buffer 3310. Only when the drawing color data has a larger value than the drawing point data from the read data buffer 3310, the logical operator 330
In step 5, an operation is performed to replace one pixel data of the drawing point from the read data buffer 3310 with one pixel data of the drawing color color data from the color register 3302, and the comparison result shows that the drawing color data is the drawing point before execution of drawing. Color·
If the value is smaller than the data, one-pixel data calculation is not performed, that is, the one with larger color data is given priority in drawing.

(8) Operation mode 7 The color comparator 3304 performs the same comparison operation as in operation mode 6 described above. As a result of the comparison, if the drawing color data from the color register 3302 is a smaller value than the color data before drawing execution from the read data buffer 3310.

A logical operator 3305 generates data for one pixel of a drawing point.

An operation is performed to replace the drawing color data from the color register 3302 with one pixel data. If the comparison result is as described above, pixel data calculation will not be performed, that is, the one with smaller color data will be given priority for drawing.

FIG. 15 illustrates comparison of pixel data by the color comparator 3304 using a 4-bit/pixel mode and bit address 8 as an example.

A mask calculation process is performed on the comparison data from three data: comparison color data 64 degrees from the color register 3302, mask data 65 degrees from the mask register 3303, and color data from the read data buffer 3310. , the mask calculator 60 calculates the mask
Referring to the data 65, a process of cutting out one pixel data represented by a single bit or a plurality of bits for comparing one pixel data is performed.

As a result, the comparison color data 64 is the comparison color 1 pixel data 6
2. The color data before drawing execution from the read data buffer 3310 is the drawing point 1 pixel data 61 before drawing.
Each pixel data is generated as one pixel data. Comparator 63
is the comparative color upper pixel data 62 and the drawing point 1 pixel data 61
It compares the data size, match, and mismatch, and outputs the result to the flag register 210.

FIG. 16 shows an example of pixel data calculation by the logical operator 3305 in the case of 4-bit/pixel search mode and bit address 8.

Logic operator 3305 receives drawing color data 71 . Mask data 70 from mask register 3303, read data buffer 3310
The 0 pixel data operation, which performs pixel data operation according to the control of the flag register 210, using three data from For bits that are Opg, read data and
Write value of buffer 3310 Data buffer 330
Output to 6.

For the mask data bit “1”,
One pixel data "C" at the same bit position of the drawing color data 71 from the color register group and the read data
Similar 1 pixel data of data from buffer 3310 “
u'' and outputs the result ``y'' to the write data buffer 3306.The operation executed here is the operation indicated by the second @, depending on the operation mode.

FIG. 17 shows an example in which drawing processing in operation modes O to 3 is executed using the hardware configuration shown in FIG. 1 showing the embodiment of the present invention. Figure 17(c) to (f)
is shown in FIG. 17(b).

Each operation f performs the drawing process of the figure ' shown in FIG.
This is an example of execution for each mode. Figure 17 (C
) indicates the result of executing pixel data calculation for replacement in operation mode O.

In other words, this indicates that the graphic information of the drawing area has been replaced with the drawing graphic data. Similarly, the same figure (d)
performs an AND operation in operation mode 2, (e)
(f) shows the result of executing an OR operation in operation mode 1, and (f) shows the result of executing an EOR operation in operation mode 3.

FIG. 18 shows operation modes 0 and 4 using the hardware configuration of FIG. 1 showing an embodiment of the present invention.
This shows the results of executing the drawing processing in steps 7 to 7. This figure shows that all the image data before drawing is executed is to sequentially draw blue rectangles represented by the value of the drawing color data rz 3 J# in a black area represented by the data value MO'',
Next, a case will be shown in which a green rectangle represented by a value of drawing color data "1'" and a red rectangle represented by a value of drawing color data "2" are drawn. FIG. 18 Ca') shows the result of drawing in operation mode 0 shown in FIG. In this mode, the last red rectangle drawn remains on the top surface. Figure 18(b) shows color data as comparative color data.
This is the result of setting black represented by the value of data "0" and executing drawing in operation mode 4 shown in FIG. In this example, the comparison color specifies the same data as the background black, and drawing is executed only on the same data as the comparison color. Here, since all of the data to be drawn is inconsistent with the comparison color, the result is that the blue rectangle that was drawn first remains on the top surface. FIG. 4(Q) is an example in which green, which is represented by the value of color data "1", is set as comparison color data and drawing is executed in operation mode 5. This mode is a mode in which drawing is executed only when the comparison color data and drawing point data are not equal, so when drawing the first dominant rectangle or when drawing the second green rectangle, Since the pixel data of the drawing point before drawing is black or green, drawing is executed as is. shi, rudder, third
When drawing a red rectangle, the red rectangle is drawn only in an area other than the green rectangle because pixel data identical to that of green in the comparative color data exists. Similarly, in Figure 18 (d
) shows the results of drawing each rectangle in operation mode 6. This mode is a mode in which drawing is executed only when the value of pixel data to be drawn at a drawing point is larger than the value of the drawing point pixel data before drawing. Therefore, the blue rectangle with the first drawing color data "3" is drawn because the pre-drawing color data of the drawing point is "0" and the drawing color data is larger. When drawing a green rectangle with the second drawing color data "1", drawing is executed only in the area whose value is higher than the value of the color data "1", so drawing is performed only in the black area. When drawing a red rectangle with the third drawing color data "2" without executing drawing in the blue rectangular area, the drawing point pixel data before drawing is "3".
Do not draw in the blue area of ', but draw only in other areas.

As a result, the figure shown in FIG. 18(d) is obtained.

Ce) in the same figure is set to operation mode 7 in the same way.
This is the result of drawing with . This mode is a mode in which drawing is executed only when the pixel data to be drawn is smaller than the drawing point pixel data before drawing. Here, the value of the pixel data before drawing is "0", and the color data to be drawn is u 1 n.

Since the values are large, such as "2" and '3', drawing is not executed, resulting in the following result.

As described in detail above, according to this embodiment, the following various effects can be obtained.In contrast to normal drawing (operation mode O), which is drawn later, has priority. In operation modes 1 to 3, various color mixtures can be performed. In operation mode 4, by specifying a specific background color, the first drawn figure can be displayed preferentially, producing the opposite effect of normal drawing. In operation mode 5, drawing of a specific color can be prohibited, so important information can be masked so that it does not disappear. In operation mode 6.7, since drawing is performed according to a predetermined priority order, the same result can be obtained even if the drawing order is different. By using this function, you can easily create a representation with depth, and it can also be applied to video processing by sequentially updating part of the information of one figure.

FIG. 19 shows another embodiment of the present invention in which comparison is made only for partial fields of one pixel. The same figure (a
) indicates the structure of one pixel data, and 6 display pixel data fields consisting of a display pixel data field and a pixel display control field for displaying on the screen are 4 bits and 16
The 9-pixel display control field that stores color display pixel information stores, for example, a coordinate value in the depth direction (2-column IJI) as attribute information of each pixel.

FIG. 2B shows the configuration of an apparatus for generating mask data for performing pixel comparison on a partial field of one pixel. - The mask data 80 indicating one pixel area from the address decoder 2002 in the sea is ANDed with the data in the field-mask Φ data register 8° indicating a partial field of one pixel, and the color comparator 3304 Create mask data to be input to. Based on the mask data generated here, as explained in FIG. 15, pixel data comparison is performed only for partial fields to control one pixel data calculation.

FIG. 20 shows three-dimensional graphic processing by taking the configuration of one pixel data shown in FIG. 19(a), comparing the pixel data shown in FIG. 19(b), and controlling the drawing process. The system configuration that enables this is shown. In other words, one pixel data is expressed by a combination of two fields: a display pixel field that stores display data and a pixel display control field that stores two coordinate values, of which a pixel display control field stores the Z coordinate value. Hidden surface processing can be performed using the Z-buffer algorithm by making only the comparison operation target and performing the drawing operation only when the two coordinate values are closer to each other.

In this system, pixel data is compared for partial fields of pixel data in a graphic processing device, drawing processing is controlled, one display pixel data is controlled, and one display pixel data is input to a display control circuit.

Displaying on a CRT constitutes a graphic display system that performs three-dimensional graphic processing.

As described above in detail, according to this embodiment, one pixel data is divided into a display pixel field and a pixel display control field, and only for the pixel display control field,
By performing pixel data comparison calculations and controlling drawing processing, there is an effect that a variety of graphic drawing processing such as hidden surface processing becomes possible.

FIG. 21 shows, as an application example of the present invention, the overall configuration of a display system to which the graphic processing device according to the present invention is applied, in which the central processing unit 90, main memory 91, graphic processing device 921 display control 93, image memory 94. Parallel-serial converter 95, display device 96, and other peripheral control devices E97
, consists of. Here, the graphic processing device 92 and the image memory 94 are parts related to the present invention.

The central processing unit 90 controls the entire system,
A bus 90 connected to a central processing unit 90 that performs control processing according to programs and data stored on the main memory.
A main memory 91, a graphic processing device 92, a display control device 93, and other peripheral control devices 97 are connected to a.

Here, the peripheral control device 97 includes various input/output control devices, auxiliary storage control devices, and the like.

The image memory 94 stores information corresponding to each pixel on the screen of the display device 96. The graphic processing device 92 according to the present invention interprets commands transferred via the bus 90a and generates various graphics on the one-image memory 94, and is also a display control device! 93 is the image memory 9
In order to sequentially read out the information on the image memory 94 and display it on the display control device 96, various synchronizing signal generation and readout control of the image memory 94 are performed. Since data is normally read out in parallel from the image memory 64, a parallel to serial converter 95 is used to convert this into a serial video signal.

In this embodiment, graphic information is stored f on one image memory 94.
Let's go □1, various,) engineering ffl! -Fm#tsua. The results obtained are as follows. Furthermore, since the processing mode and color specification parameters can be controlled independently of the generation of each pixel information, it is easy to change the conditions for one color. Therefore, in this application example, the burden on the central processing unit 90 required to change one color condition can be significantly reduced.

〔Effect of the invention〕

As described above, according to the present invention, it is possible to perform conditional drawing according to color and gradation data.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing parts closely related to the conditional drawing method according to the present invention, FIG. 2 is an explanatory diagram of the operation mode, which is a pixel data calculation mode, and FIG. 3 is a diagram to which the graphic processing device according to the present invention is applied. a block diagram showing a device to be used;
FIG. 4 is a block diagram showing an embodiment of a graphic processing device according to the present invention, FIG. 5 is a block diagram showing a display device to which the embodiment is applied, and FIGS. 6 to 8 are diagrams showing the graphics in FIG. 4. FIG. 9 is an explanatory diagram showing the bit layout of display data used in the same embodiment; FIG. 10 is an explanatory diagram showing the bit layout of pixel addresses used in the same embodiment; The figure is a block diagram showing the configuration between the image memory and the display device, FIG. 12 is an explanatory diagram shown to explain the drawing calculation operation of the same embodiment, and FIG. 13 shows the format of the macro instruction used in the same embodiment. The explanatory diagram, Figure 14, shows the bit address and mask in 4-bit/pixel mode.
An explanatory diagram of data, Fig. 15 is an explanatory diagram of pixel data comparison, No. 16 @ is an explanatory diagram of pixel data calculation, Fig. 17 is an explanatory diagram of operation modes 0 to 3 according to the present embodiment,
FIG. 18 is an explanatory diagram of operation modes 4 to 7;
FIG. 19 is an explanatory diagram of partial fields and their comparison; FIG. 20 is a schematic configuration diagram of a three-dimensional figure processing system;
FIG. 21 is an overall schematic diagram showing another embodiment of the present invention. 3303...Color comparator, 3305...Logic operator, 210...Flag register, 80...Field mask data register Agent Patent attorney Katsuo Ogawa ")', 1.:::,',,
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Claims (1)

[Scope of Claims] 1. In an apparatus that performs drawing processing by sequentially calculating pixel positions and reflecting predetermined drawing pixel data in a graphic information storage means, read pixel data from the graphic information storage means; A graphic processing method, characterized in that the drawing process is controlled by a comparison operation between and predetermined comparison pixel data. 2. It has a first means for storing graphic information and a second means for storing predetermined drawing pixel data, and the data read from the first means and the data read from the second means are The device has a third means for performing calculations between the two, and performs drawing processing by writing the calculation results of the third means into the first means, the data read from the first means and the data read from the first means. A fourth means for performing a comparison operation with predetermined comparison pixel data is provided, and the comparison operation by the fourth means leads to the drawing operation in the third means or to the first means. 1. A graphic processing device, characterized in that the writing of the data is controlled. 3. In claim 2, in order to treat the drawn pixel data as predetermined comparative pixel data, the fourth means combines the read data from the first means with the second means. A graphic processing device characterized in that it performs a comparison operation between. 4. In claim 2, a fifth means for storing predetermined comparison pixel data is provided, and in the fourth means, between the read data from the first means and the fifth means. A graphic processing device characterized in that it performs comparison operations. 5. In claim 2, a sixth means for specifying a partial field of one pixel data is provided, and the sixth means is provided.
A graphic processing device characterized in that the comparison operation by the fourth means is performed only for the partial field specified by the means.