JPS6159565A - Interrupt input device of multicomputer system - Google Patents

Abstract

PURPOSE:To use free input data as an interrupt signal without using a leased interrupt card by installing an interrupt input detecting circuit and an interrupt register for plural CPUs and interrupting by respective CPUs with a common interrupt signal. CONSTITUTION:A shared transfer bus 11 system address bus renews an address cyclicly and data of a corresponding process input output device (PI/O) 4 ride on a data bus. When an interrupt address set by an interrupt address setting circuit 13 in an interrupt input device 8 is coincident with an address from an address bus, an interrupt address coincident signal is outputted, input data on the data bus are inputted to an interrupt input detecting circuit 15, a change of the data is detected and an interrupt input signal is written in an interrupt register 16. When an interrupt mask register 17 is in an interrupt permitting condition, an interrupt signal is sent to CPU 1. CPU 1 outputs an address and a reading signal of the interrupt register 16 to the address bus, and interrupts by interrupt information of the interrupt register 16 and a response signal.

Description

[Detailed Description of the Invention] [Field of Application of the Invention] The present invention relates to a multi-computer system, and in particular,
6 Concerning an interrupt input device suitable for interrupt processing [Background of the invention] Conventional devices are disclosed in Japanese Patent Laid-Open No. 58-43054 and Japanese Patent Laid-open No. 58-58-
As described in Publication No. 60334, multiple central processing units (hereinafter referred to as CPUs) and process input/output devices i! (hereinafter referred to as PI
In a multi-computer system in which 10) are connected using a shared transfer bus, PI/○ data is cyclically transferred to each CPU through the shared data bus.

However, no consideration has been given to providing an interrupt input signal to one or more CPUs in common to perform interrupt processing. First, if an interrupt-only card is provided for each CPU, the interrupt information will only be input to the corresponding CPU, and will not be transferred to other CPUs. In addition, if an interrupt-only card is provided that is common to all CPUs, the above-mentioned CPU and
In addition to the shared transfer bus connecting Ilo, an interrupt-only card and all C
Connections are required between PUs. Moreover, there is a problem in that the system cannot be easily changed. Furthermore, when attempting to read an interrupt input signal to the CPU via the shared transfer bus, the CPU must always cyclically access the address of the interrupt-only card. There is now a need for a method that allows signals to be shared by multiple CPUs and that is constructed using simple hardware.

A related method is disclosed in Japanese Patent Publication No. 58-46725, for example.

[Purpose of the invention]

The object of the present invention is to
An object of the present invention is to provide an interrupt input device for sharing an interrupt signal, which is reset after being read by a PU, among a plurality of CPUs operating asynchronously.

[Background of the invention]

In the present invention, an interrupt input detection circuit and an interrupt register are provided for each of a plurality of CPUs, and interrupt information of an arbitrary interrupt address is
This signal is input to the interrupt register of all CPUs or a specific CPU, and each CPU performs interrupt processing using a common interrupt signal.

[Summary of the invention]

FIG. 1 is an overall configuration diagram of an embodiment of the present invention.

In the figure, CPU-Al, CPU-B2. ...CP
U-N3 is a central processing unit that operates asynchronously, PI104
is the process input/output device common to all CPUs, INT-A8
．． INT-B9. ...INT-N10 is an interrupt input device, memory A/5. Memory B.6, . . . memory N.7 are memories that each CPU has individually.

Each CPU I~3 is connected to an interrupt input device INT8~10. by a bus for each CPU. and accesses memories 5-7.

The memories 5 to 7 are interconnected by a shared transfer bus 11 that is separate from the CPU system bus, and a bus control device 12 cyclically transfers data to a common PIlo.

Further, the interrupt input devices 8 to 10 also accept interrupt inputs from the PI 104 via the shared transfer bus 11.

FIG. 2 shows an interrupt input device of the present invention.

The interrupt input device 8 includes an interrupt address setting circuit 13, an interrupt address conveyor circuit 14, and a PI 104, which can arbitrarily set an input address corresponding to input data to be used as interrupt information.
It consists of an interrupt input detection circuit 15 that detects an interrupt input from the CPU, an interrupt register 161 that stores interrupt information, an interrupt mask register 17, and an interface circuit with the CPU.

Normally, input data from PI104 is transferred to common transfer bus 1.
1, the input data corresponding to the specific address set by the interrupt address setting circuit 13 is input to the memory 5, and is also input to the interrupt input detection circuit 15, and is input to the interrupt input detection circuit 15. If a change occurs in the data of the interrupt address (interrupt activation status S), a flag is set in an arbitrary bit of the interrupt register 16. In other words, information on a normal PI card is used as an interrupt signal, and a dedicated interrupt card is not required. Then, if the bit of the interrupt mask register 17 corresponding to the bit of the interrupt register 16 is enabled, a 1 interrupt signal is sent to the CPUI, and the 0 interrupt mask register 17 starts the CPUI interrupt processing. If the bit is in the interrupt disabled state, no interrupt signal will be output and the interrupt information will be ignored.

The operation will be explained with reference to FIG.

In the address bus of the shared transfer bus system, addresses are cyclically updated, and corresponding PI10 data is placed on the data bus. The interrupt address set by the interrupt address setting circuit in the interrupt input device mentioned above,
When the addresses from the address bus match, an interrupt address match signal is output, and the input data on the data bus at that time is input to the interrupt input detection circuit6.Then, a change in data is detected and the PII signal (interrupt 6. If the interrupt mask register is in an interrupt enabled state, an interrupt signal is sent to the CPU.

In response to the interrupt signal, the CPU outputs the address of the interrupt register and the read signal REQ to the CPU system address bus, and outputs the interrupt information of the interrupt register and the response signal AC.
Interrupt processing is performed by K.

〔Effect of the invention〕

According to the present invention, in a multi-computer system composed of a plurality of CPUs and a common PIlo, interrupt information can be shared by a plurality of CPU'Us with a simple hardware configuration6. Any input data can be used as an interrupt signal without using.

[Brief explanation of drawings]

FIG. 1 is a block diagram of an embodiment of the present invention, and FIG. 2 is a block diagram of an embodiment of the present invention.
A hardware configuration diagram of the present invention, FIG. 3 is an explanatory diagram of the operation of the embodiment 6 8...Interrupt input device, 13...Interrupt address setting circuit, 14...Interrupt address conveyor circuit, 15 ...
Interrupt input detection circuit, 16... Interrupt register, 17...
- Interrupt mask register.

Claims (1)

[Claims] 1. An interrupt address setting circuit that can arbitrarily set an interrupt address in a multi-computer system in which a plurality of asynchronously operating central processing units and process input/output devices are coupled using a shared transfer bus. and an interrupt input device consisting of an interrupt address compare circuit, an interrupt input detection circuit to detect interrupts, an interrupt register to store interrupt information, and an interrupt mask register to enable or disable interrupts. An interrupt input device for a multi-computer system, characterized in that the interrupt input device is provided for each of the central processing units.