JPS6150294A - Redundant circuit of semiconductor memory - Google Patents

Abstract

PURPOSE:To reduce the number of spare decoder circuit without losing the resuce efficiency of an inferior memory cell by providing a link element to a brached output line branched to a spare decoder circuit. CONSTITUTION:In case a fault is generated in a block A of a line decoder circuit line elements F1-Fn, -F1-Fn are blown by a laser beam to activate a spare line decoder circuit and a link element Fb connecting to a spare word line WLB is blown. Then, only a spare word line WLA at a block A side is activated so as to rescue a block A. By fusing a link element Fb, a brached output line 3 is floated. Clamp circuits 3, 4, during precharging the line decoder circuit, branched output circuits 2, 3 are kept at an earth potential and during activation thereof, the brached output lines 2, 3 at the block A to be selected are kept to a high level by the output signal of the line decoder circuit and the circuits 3, 4 have the function to keep the branched output line 3 of the non- selected block B at a low level as it is.

Description

DETAILED DESCRIPTION OF THE INVENTION [Technical Field of the Invention] The present invention relates to a circuit configuration of a redundant circuit of a semiconductor memory device.

(Prior Art) Fig. 1 and Fig. 2 show redundant circuits of a conventional semi-quadramid memory device. Fig. 1 shows a row decoder circuit for selecting a row, that is, a lead line, of a semiconductor memory device; 1 is an output line, and FA is a link element.

If there is a defect in the memory cell selected by the word line connected to the link element FA, the link element FA is fused by a laser beam and the defective word line is made unselected.

FIG. 2 shows a spare row decoder circuit, Fl.

Kurei, F2. F2. ..., Fn-1,
F"n-1, Fn, and Fn are link elements. This spare row decoder circuit fuses the word line of the non-selected defective memory cell by melting the link element with a laser beam appropriately according to the defective address. All 2n address signals Al are replaced in the spare row decoder circuit.
, Al, . . . +, An, An are input, and are always unselected when no replacement is required. For replacement, one link element of either the positive signal or the inverted signal of each address is fused with a laser beam according to the defective address, and the word that has become defective and has been deselected by the laser blow of the link element is replaced. This is done by implementing the same address input as the row decoder circuit connected to the line.

FIG. 3 shows waveforms of various parts of the row decoder circuit of FIG. 1 and the second panel. The operation of the row decoder circuit will be explained using FIG. After the RAS signal in FIG. 3(a) changes from high level 10 to low level 11, the address becomes MtF1t, and the address signals An and An in FIG. 3(b) change from low level 12 to high level 13. , the output lines l of all row decoder circuits except the selected row decoder circuit are discharged. The selected row decoder circuit has its output line 1 kept at a high level and the word line drive signal RX shown in FIG. 3 (C1).
When the signal becomes high level 14, the word lines WR and WL are selectively driven. The RXD signal shown in Figure 3 (dl) is a signal that disconnects the row decoder circuit from the word line after the word line is selected. This is a signal for clamping to.

Next, the memory cell array is made up of multiple memory cell array blocks (hereinafter referred to as "blocks" in the car) that are independent of each other.
Let's consider how to use redundant circuits in the case of FIG. 4 shows a block system diagram for explaining how to use the redundant circuit. In FIG. 4, 20a, 20b and 20c are spare word lines, normal word line group and row decoder circuits of block A, 21a, 21b and 2
1c is a spare word line, normal word line group and row decoder circuit of block B, 22 is a spare row decoder circuit connected to spare word line 20a of block A, 23
is a spare row decoder circuit connected to the spare word line 21a of block B.

Conventionally, in order to replace and repair defective memory cells in each block with spare row decoder circuits, it has been necessary to arrange a necessary number of spare row decoder circuits in each block. In the case of Figure 4, each block has one spare word line and only one spare row decoder circuit, but generally when there are n spare word lines, n spare row decoder circuits are required. . Further, the number of defective memory cells that can be repaired is limited to the number of spare row decoder circuits included in each block. The occurrence of defects varies; for example, in FIG. 4, if there are two defects in block A and no defects in block B, the number of chips that can be repaired in block A is at most one, so the chip cannot be repaired. In order to relieve such a case, it is necessary to include two spare row decoder circuits in each block. Therefore, the number of spare row decoder circuits increases. Since the spare row decoder circuit requires twice as many address lines as a normal row decoder circuit, it occupies a large area, which is disadvantageous in terms of chip size.

[Summary of the invention]

The present invention has been made in view of these points, and its purpose is to provide a redundant circuit with a small area for the spare row decoder circuit H;i and with high relief efficiency. be.

In order to achieve such an object, the present invention enables a spare row decoder circuit to be connected to each block.

[Embodiments of the invention]

The present invention will be explained in detail based on examples. FIG. 5 shows an embodiment of a redundant circuit for a semi-dedicated recording device according to the present invention. In FIG. 5, la is a branch point where output line 1 is branched, 2 and 3 are branch output lines connected to spare word 4gwLA and WLB as pre(lif'U selection line), and 4.5
is a clamp circuit to prevent malfunction, and 6 and 7 are to spare word cotton WL.

A transistor for selectively driving WLB, 8°9 is a node for connecting the clamp circuit 4.5 to the branch output line 2.3, and Fa and Fb are on the branch point la side on the branch output lines 2 and 3. It is a link element. The row decoder circuit of FIG.
It is branched into. Branch output lines 2.3 each have link elements Fa and Fb, and are connected to spare word line WLA going to block A and spare word line WLB going to block B (connected to spare word line WLB).

1 order, yu, :,)yo0. Configured row decoder circuit. Regarding the operation, a case where a defect occurs in block A and it is necessary to use a spare word line for relief will be explained. First, depending on the defective address in block A, the T'J7 element F1. F1. F2. F2.
- ++, Fn-1, Fn-1, Fn, - are blown with a laser beam to activate the spare row decoder circuit and also blow the link element Fb connected to the spare word WLB of block B. By doing this, only the spare word line WLA on the block A side is activated, making it possible to repair the block. That is, one spare row decoder circuit can be connected to the spare word lines of either block A or block B. FIG. 6 schematically shows this situation. In FIG. 6, 24 is a spare row decoder circuit that can be connected to either spare word line WLA or WLB. Also, in Figure 6, the 4th
Identical or equivalent parts to those in the figures are given the same reference numerals.

In FIG. 6, there are two connection destinations, blocks A and B, but it is also possible to provide more than two blocks via link elements.

FIG. 7 shows a case where there are two spare row decoder circuits, 20al and 20a2 are spare word lines of block A, 21al and 21a2 are spare word lines of block B, and 25.26 is a spare row decoder circuit. , the output of each spare row decoder circuit 25,26 is connected to blocks A, B via link elements. At this time, the outputs of the two spare row decoder circuits 25 and 26 can be arbitrarily connected to blocks A and B as required.

Next, the operation of the clamp circuits 4 and 5 in FIG. 5 will be explained. When the output line 1 of the row decoder circuit and the branch output line 3 located on the spare word line WLB side from the link element Fb are disconnected by blowing out the link element Fb, the branch output line 3 becomes floating. When the Suhyaku signal goes high to select a word line and the RX signal rises from a low level to a high level, the gate potential of transistor 7 rises due to coupling, causing WLB, which should not be selected, to go to a high level. There is a risk of being transmitted. To avoid this, the clamp circuits 4 and 5 are connected to the branch output line 2.
．． I am preparing for 3. This clamp circuit 4.5 sets the branch output lines 2 and 3 to ground potential when precharging the row decoder circuit, and when activated, connects the branch output line 2 of the selected block A side to the output signal of the row decoder l''l path. The branch output line 3 on the non-selected block B side is kept at a low level (it has a function).

As described above, the spare row decoder circuit of this embodiment allows connection even if a defective memory cell occurs in any block, and has the advantage that the number of spare row decoder circuits can be reduced.

Although the above explanation was given regarding the row decoder circuit,
It goes without saying that the present invention can also be applied to column decoder circuits.

〔Effect of the invention〕

As described above, the present invention branches the output line X51 of the spare decoder circuit and provides a link element on the branched output line, thereby making it possible to connect the pre-0i1i iH selection 35 provided in a plurality of independent memory cell array blocks. ) can be activated arbitrarily, which has the effect of reducing the number of spare decoder circuits without increasing relief efficiency.

[Brief explanation of the drawing]

Figure 1 is a conventional row decoder circuit diagram, Figure 2 is a conventional spare row decoder circuit diagram, Figure 3 is a waveform diagram of each part of the row decoder circuit, and Figure 4 explains how to use the conventional spare row decoder circuit. FIG. 5 is a spare row decoder circuit diagram showing an embodiment of the redundant circuit according to the present invention. FIG. 6 is a block diagram for explaining how to use the embodiment. The figure is a block system diagram for explaining how to use another embodiment. 1... Output line, 1a... Branch point, 2.3...
... Branch output line, 4.5... Clamp circuit, 6.
7...transistor, 8,9...node, 20
a, 21a, 20al, 20a2. ．． 21
al, 21a2... Spare word line, 20b, 21
b...Normal word 1 line group, 20C,
21C...Row decoder circuit, 24.25.26...
...Spare row decoder circuit.

Claims (4)

[Claims] (1) A plurality of preliminary selection lines arranged in a plurality of independent memory cell array blocks and a spare decoder circuit corresponding to the preliminary selection line are provided, and the spare decoder circuit is branched from the output line. a plurality of branch output lines, a link element on the branch point side of the branch output line, and a clamp circuit connected to the branch output line, and the branch output line is connected to the plurality of memory cell array blocks. A redundant circuit for a semiconductor memory device, characterized in that the redundant circuit is connected to a preliminary selection line arranged in each of the plurality of branch output lines, and enables only one of the plurality of branch output lines by cutting off the link element. (2) A redundant circuit for a semiconductor memory device according to claim 1, wherein the preliminary selection line is a preliminary row selection line, and the spare decoder circuit is a spare row decoder circuit. (3) A redundant circuit for a semiconductor memory device according to claim 1, wherein the preliminary selection line is a preliminary column selection line, and the spare decoder circuit is a spare column decoder circuit. (4) During precharging, the clamp circuit discharges the node to a low level, and when activating the spare decoder circuit, maintains the node on the selected preselect line side at high level, and lowers the node on the unselected preselect line side. 2. The redundant circuit for a semiconductor memory device according to claim 1, wherein the redundant circuit is a circuit that maintains a level.