JPS6135018A - Analog switch circuit - Google Patents

Abstract

PURPOSE:To decrease the resistance at conduction by connecting the 2nd analog switch in parallel between terminals of the 1st analog switch placed at an output of an amplifier via a resistor and feeding back a signal from a connecting point between the 2nd analog switch and the resistor to the amplifier. CONSTITUTION:The 1st analog switch 34a is placed between an output of a buffer amplifier 30 and a load 32 and the 2nd analog switch 34b is connected in parallel between terminals of the switch 34a via a resistor 36. Then an output of the amplifier 30 generated at a connecting point between the resistor 36 and the switch 34b is fed back to an inverting input of the amplifier 30. When the switches 34a, 34b are nonconductive, the output of the amplifier 30 is fed back via the resistor 36 to interrupt the supply to the load 32. When the switches 34a, 34b are conducted, the output of the amplifier 30 is fed to the load 32 and fed back and the conductive resistance in the switches 34a, 34b is reduced by parallel connection.

Description

DETAILED DESCRIPTION OF THE INVENTION Field of the Invention This invention relates to an analog switch circuit with reduced resistance during conduction.

2. Description of the Related Art Conventionally, analog switches used for signal switching, sample and hold circuits, etc. are installed between a signal sending means such as a buffer amplifier and a load, as shown in FIGS. Constructed to conduct during sampling.

That is, the analog switch circuit shown in FIG. 5 is used for signal switching, and the analog switch 2 is connected between the output of the buffer amplifier 4 and the load 6. 3 represents an input signal, 5 represents a control pulse, and 7 represents an output signal.

The analog switch circuit shown in FIG. 6 is used as a sample-and-hold circuit, and a transistor 10 controlled by the output of a buffer amplifier 8 is connected, and the emitter of this transistor 10 and a sample-and-hold capacitor 12 are connected. A transistor 14 as an analog switch is installed between them. And buffer amplifier 8
An input voltage 9 is applied to the non-inverting input terminal (+) of the transistor 14, and a sampling pulse 18 is applied to the terminal 16 formed at the base of the transistor 14. A sample voltage of the input voltage 9 is taken out from the output terminal 20.

(A) in FIG. 7 shows a specific circuit configuration example of the analog switch circuit shown in FIG.
A control pulse 26 is applied to a terminal 24 formed on the base of the analog switch 2 shown in the figure.

In this analog switch circuit, when the terminal 24' goes low (L) level and the transistor 22 becomes conductive, an equivalent circuit as shown in FIG. 7(B) is obtained. That is, on the right side of this equivalent circuit, resistor 28 is connected to transistor 2.
．． 2 conduction resistance. The value of this conduction resistance 28 is rO5
The input voltage applied to the non-inverting/inverting input terminal (+) of the amplifier 4 is v9, the resistance value of the load 6 is RL, and the output current flowing through this load 6 is ■. Then, the voltage V0 generated in the load 6 is Vo -V+ ・RL / (R,L-hro)
...(11), and the error voltage ΔV generated between the umisota and the collector of the transistor 22 due to the switching of the transistor 22 is: ΔV= (re / (RL +ro)) ・V
+Uniform ■.・r, ...(2) Problems to be Solved by the Invention As described above, in the conventional analog switch 1IB8, when the analog switch is conductive and the load current flows through it, the load current Riko 4. Voltage drops occur in analog switches, which worsens the distortion rate of the processed signal and increases the sample-and-hold voltage error in the sample hold mode. .

Conventionally, there are methods using MO3 transistors and bipolar transistors (NPN, PNP5) as analog switches, but the conduction resistance of these transistors has large non-uniformity (variation) of about -a, and the magnitude of the flowing current is large. Since the resistance value changes depending on the direction of the current, it is necessary to make the absolute value of the conduction resistance so small that it can be ignored under the usage conditions.

Normally, the conduction resistance of a switching element is proportional to the size (area) of the switching element of a semiconductor integrated circuit, so
Reducing the conduction resistance increases the element area, which results in higher costs.

Therefore, the present invention attempts to suppress the influence of voltage drop due to the four-way resistance of the analog switch.

Means for Solving the Problems This invention installs a first analog switch on the output side of an amplifier, and connects a second analog switch in parallel between the terminals of the first analog switch via a resistor. A connection point between the second analog switch and the resistor provides feedback to the amplifier.

Activating the first and second analog switches simultaneously;
By parallelizing both conduction resistances, the isometric conduction resistance is reduced.

When each analog switch becomes conductive, the second analog switch detects the signal that has passed through the first analog switch and feeds it back to the amplifier.

Furthermore, when each switch is non-conductive, the signal before passing through the first analog switch is fed back to the amplifier via the resistor.

Embodiments Hereinafter, the present invention will be explained in detail with reference to embodiments shown in the drawings.

FIG. 1 shows an embodiment of the analog switch circuit of the present invention.

In FIG. 1, the output section of the buffer amplifier 30 and the load 3
2, a first analog switch 34a is installed between the terminals of the analog switch 34a, and a resistor 36 is connected between the terminals of the analog switch 34a.
The second analog switch 34b is connected in parallel through the resistor 36 and the second analog switch 34b, and the output of the amplifier 30 generated at the connection point between the resistor 36 and the second analog switch 34b is connected to the inverting input terminal (-) of the buffer amplifier 30. They are set to return.

The operation of such a configuration will be explained with reference to FIG.

A signal 33 is applied to the non-inverting input terminal (+) of the amplifier 30, and the first and second analog switches 35a, 35
Opening/closing b is controlled by a control pulse 37, and 39 is an output signal obtained via analog switches 35a and 35b.

When the first and second analog switches 34a and 34b are non-conductive, the output of the buffer amplifier 30 is connected to its inverting input terminal (-) via the resistor 36, as shown in FIG. 2(A). It is fed back and the supply to the load 32 is cut off.

In addition, the first and second analog switches 34a, 34
When b becomes conductive, the output of the buffer amplifier 30 is supplied to the load 32 and fed back to its inverting input terminal (=), as shown in FIG. By paralleling the analog switches 34a and 34b, the conduction resistance can be reduced to a negligible level compared to the case where a single analog switch is installed.

FIG. 3 shows a specific example of the circuit configuration of the analog switch circuit of the present invention, and the same parts as in the embodiment shown in FIG. 2 are given the same reference numerals.

In FIG. 3(A), the transistor 35a.

35b is the first and second analog switch 34a, 3
A common control signal 37 is applied to the base of each transistor 35a, 35b.

FIG. 3B shows an equivalent circuit when both transistors 35a and 35b are in a conductive state.

In this equivalent circuit, the input voltage of the non-inverting input terminal (+) of the buffer amplifier 30 is Vl, the transistor 35a,
The conduction resistance of the resistor 35b is rl, rZ, the resistance value of the resistor 36 is R1, the current flowing through the conduction resistance r is ■1, the conduction resistance r2
The current flowing through the load 32 is 12, and the load current flowing through the load 32 is Io.
(=I+ +I2), the current 1t, Iz is 1l-(R+ +r,) ・Io/((R+ 1r
z ) + rl ) ...(311z = r1
'to / ((R+ +j2)+r+)...
(4) The voltage at the feedback point f becomes equal to the input voltage v1. In this case, the output voltage generated at the load 32 is ■. , vo = ■1-12 ・ ``2 ・ ・ ・
(5), and the error voltage Δ generated in the S resistance r2
V is ΔV=I2 ・r2=r, ・r2 ・I.

/ ((R+ +rz)+-r,) (6). That is, it can be seen that by setting R1) to 11% r2, ΔV can be made extremely small.

Therefore, if the current capacity of each analog switch 34a, 34b satisfies the usage conditions, a highly accurate switching function can be provided without using a transistor whose conduction resistance is extremely low.

FIG. 4 shows a case where the present invention is applied to a sample and hold circuit, and the same parts as in the embodiment shown in FIG. 3 are given the same reference numerals.

The output of buffer amplifier 30 is connected to transistors 38a, 3
The transistor 38a and the transistor 35a are connected in series with their emitters in common, and the transistor 38b and the transistor 35b are connected to the base of the transistor 8b.
The emitters are connected in series via a resistor 36.

A resistor 40 is connected to the base of the transistor 35b, and a sampling pulse 44 is applied from a terminal 42 to each transistor 35a135b.

In addition, the collectors of each transistor 35a, 35b have
A sample and hold capacitor 46 is connected thereto, and an output terminal 48 for taking out a hold output is formed.

According to such a configuration, when the input voltage 43 is applied to the non-inverting input terminal (+) of the amplifier 30 and the transistors 35a and 35b are simultaneously turned on by the sampling pulse 44 applied to the input terminal 42, the buffer amplifier 3
The output of 0 flows from the transistors 38a and 38b to the transistors 35a and 35b, and this output current flows to the capacitor 4.
6, and the charging voltage of the capacitor 46 is updated in accordance with the sampling pulse 44.

The charging voltage of the capacitor 46 is taken out from the output terminal 48 as a sample and hold voltage.

In this case, as shown in (A) and (,B) in Figure 3,
The sample and hold voltage can be extracted with high precision and very little error.

In particular, as is clear from the circuit configuration of the example, a similar analog switch is connected in parallel to a conventional analog switch, and no special circuit is added, making it possible to use semiconductor integrated circuits at low cost. can be provided.

Although the embodiments have been described using signal switching and sample-hold circuits as examples, the analog switch circuit of the present invention can also be used for signal processing other than this type of circuit.

As described in detail, according to the present invention, the influence of voltage drop due to the conduction resistance of an analog switch can be suppressed to an extremely small level, and unlike the conventional method, the conduction resistance can be increased more than necessary in order to improve accuracy. It is possible to prevent cost amplifiers to keep them small.

[Brief explanation of the drawing]

Fig. 1 is a circuit diagram showing an embodiment of the analog switch circuit of this invention, Fig. 2 is a circuit diagram showing its equivalent circuit, and Fig. 3 is a circuit diagram showing an example of the analog switch circuit of this invention.
The figure is a circuit diagram showing a specific example of the configuration of the analog switch circuit of the present invention, Figure 4 is a circuit diagram showing an application example of the analog switch circuit of the present invention, and Figures 5 and 6 are conventional analog switch circuits. FIG. 7 is a circuit diagram showing an equivalent circuit of the circuit shown in FIG. 34a...first analog switch, 34b...second analog switch, 35a, 35b...transistor. Figure - Figure 2 (A) (B) Figure 3 (A) Figure 4 H 411''=L Figure 5 Figure 6 1-Go1

Claims (1)

[Claims] A second analog switch is connected in parallel through a resistor between the terminals of a first analog switch installed between the output side of the amplifier and the load, and a connection point between the second analog switch and the resistor is connected. An analog switch circuit that feeds back the output generated by the amplifier to the amplifier.