JPS61286946A - Microprocessor unit - Google Patents

Abstract

(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Application] The present invention relates to the field of address translation devices for memory management, particularly in microprocessor devices.

[Prior art]

There are many well-known mechanisms for memory management. In some devices, large addresses (virtual addresses) are translated into smaller physical addresses. In other devices, formal addresses are used to access large memory spaces, for example by using bank switching. The invention relates to the former category, where large virtual addresses can be used to access limited physical memory.

It is also known to provide various protection mechanisms in memory management devices. For example, a user may be prevented from writing an Operating 7 stem, or perhaps even reading an Operating 7 stem to an external port. As you will see later, the present invention allows data to
The protection mechanism is implemented as part of a broader control scheme that assigns attributes at two different levels.

The prior art that the inventors believe is closest to the present invention is disclosed in US Pat. No. 4,442,484. That U.S. patent covers commercially available microprocessors (
A memory management and protection mechanism is disclosed as embodied in Intel (286). The microprocessor includes a segmentation descriptor register containing segment pace addresses, limit information, and attributes (eg, protection bits). Both the segment description reserve and segment descriptor registers contain bits that define various control mechanisms such as priority level, type of protection, etc.

One problem with Intel 286 is that segment offsets are limited to 64 bytes. intel 28
6 requires contiguous locations in physical memory for segments, which is not always easy to maintain. As will be seen, one advantage of the apparatus of the present invention is that the segment offsets are of the same size as the physical address space. The apparatus of the present invention is also compatible with conventional segmentation mechanisms found in the Intel 286. The prior art device disclosed in said US patent and its commercial implementation (Intel 286 Microprocessor Tools)
) and the present invention, as well as other advantages of the present invention, are:
It will be clear from the explanation below.

[Summary of the invention]

This specification describes improvements to microprocessor devices including microprocessors and data memory. The microprocessor includes a segmentation mechanism or functionality for translating a virtual memory address into a second memory address (C) and for testing and controlling attributes of the data memory segment. The improvement of the present invention is as follows:
A page cache memory is included in the microprocessor for translating the tenth) field from a linear address for a ) state or a match (m t ch ) state. The data memory also stores page mapping data, in particular page directories and page tables. If no hit occurs in the page cache memory, the 10th field accesses the page directory and page table. The output from the page cache memory or page table provides the physical base address for the page in memory. Another field in the linear address gives the offset within the page.

Page mapping data in the page cache memory and data memory stores signals representing the seven tributes of data in a particular page. These attributes include read and write protection, indicate whether the page has been previously written, and other information. Importantly, page level protection provides a second level of control over data within a page that is separate and distinct from segment attributes.

〔Example〕

Hereinafter, the present invention will be described in detail with reference to the drawings.

A preferred embodiment of the microprocessor device of the present invention includes the microprocessor y1G (FIG. 1).

The microprocessor is fabricated on a single silicon substrate using complementary metal-oxide-semiconductor (0MO8) processing. Any of the many well known 0MO8 methods can be employed. The invention can also be implemented with other technologies such as beam channel, bipolar, SO8, etc.

Memory management mechanisms for certain conditions require accessing tables stored in main memory.

A random access memory (RAM) 13 is shown in FIG. 1, which serves as the main memory for the microprocessor device. RA with dynamic memory
A normal RAM such as M can be used.

As shown in FIG. 1, microprocessor 1° has a 32-bit physical address, and the microprocessor itself is a 32-bit microprocessor. Other components commonly used in microprocessors, such as drivers, mathematical processors, etc., are not shown in FIG.

Summary The memory management of the present invention uses segmentation and paging. A segment is defined by a set of segment descriptor tables that are distinct from the page costs used to describe page translations. The two mechanisms are completely different and independent. Using two types of mapping mechanisms, virtual addresses are translated into physical addresses in two stages. Segmentation techniques are used for stage 10) and paging techniques are used for the second translation stage. Paging technology may not be used to perform one-step translation using only segmentation technology. This one-step translation is compatible with Intel 286.

Segmentation (10th translation stage) translates the 48-bit virtual address into a 32-bit reduced (intermediate) address. A 48-bit virtual address consists of a 16-pit segment selector and a 32-bit offset within this segment.

A 16-bit segment selector is used to identify the segment and access entries from the segment descriptor fit. This segment descriptor entry includes the base address of the segment, the size (limit) of the segment, and the various triplets of the segment. This translation step adds the segment base to the 32 pint offset within the virtual address to obtain a 32-bit linear address. At the same time, the 32-bit offset in the virtual address is compared to the segment limit and the type of access is checked against the segment attributes. If the 32 pin offset is outside the segment limits, but the type of access is not allowed by the segment attributes, a fault is generated and the addressing process is aborted.

Paging (secondary translation) uses a two-level paging table to translate 32-pinto linear addresses to 32-pinto physical addresses in a process described below.

The two stages are completely independent. Korenyo 9 (big)
A segment can consist of any number of pages, or a page can consist of several (formal) segments.

A segment can start at any boundary, the segment can be any size, and
It is not limited to starting on a cuvage boundary or having a length that is an exact multiple of a page. This allows a segment to describe a separately protected area of memory starting at an arbitrary address, and can be made to any size.

Segmentation can be used to combine several smaller segments into one page, each with unique protection attributes and thickness formulas. In this case,
Segmentation provides a protection attribute, and pages provide a convenient way for physical memory to map groups of related units that must be protected separately.

For physical memory management, paging can be used to break down very large segments into smaller units. This allows a single identifier (segment, selector) and a single descriptor (segment descriptor) for separately protected units of memory, rather than requiring the use of a large number of page descriptors. Given. Within a segment, paging provides an additional level of manipulating that allows large segments to be mapped into separate pages that do not require contiguity in physical memory. In practice, paging allows manipulating large segments such that only a small number of pages reside in physical memory at a time, and the remainder of the segment is mapped to disk. Paging also supports the definition of substructure within a large segment, eg, supports writing protection to some pages of a large segment while leaving other pages writable.

Segmentation provides a very comprehensive model for operating on "natural" units used by a program, ie, arbitrarily sized portions of linearly addressable memory. Paging provides a very convenient way to manage physical memory, ie, seven stems of main storage and secondary storage. Combining these two methods in the present invention provides a very flexible and powerful protection model.

Overall Microprocessor Architecture In FIG. 1, the microprocessor includes a bus interface device 14. As shown in FIG. This bus interface device 14 has three
It includes a buffer to allow transmission of 2-bit address signals and to perform 32-pin transmission and reception of data. Inside the microprocessor, bus interface device 14 communicates via an internal bus 19.

Bus interface device 14 includes a briefetch device for fetching instructions from RAM 13 and a briefetch matrix that communicates with the instruction device of instruction decoder 16 . The matrixed instructions are processed in an execution unit (arithmetic logic unit) 18 that includes an 82 pinto register file. The execution unit 18 and decoder 16 communicate with an internal bus 19.

The present invention is structured around the address translation device 20. This translation device performs two functions: one related to segment descriptor registers and one related to page descriptor cache memory. Although most of the segment registers are conventionally known, they will be explained in detail with reference to FIG. The page cache memory and the interaction between the page table and page directory stored in the main storage device 13 and the page cache memory will be explained with reference to FIGS. 3 to 7. They form the basis of the invention.

Segmentation Mechanism The segmentation device shown in FIG. 1 receives a virtual address from execution device 1B and accesses the appropriate segmentation information. The register contains the segment base address. This segment base address is coupled to the page device via line 23 along with the offset from the virtual address.

FIG. 2 shows the access operations in main memory when the segment descriptor register is loaded with manipulating information for a new segment.

The segment field indexes the segment descriptor table in main memory 13. The contents of the garment include a base address and attributes related to the data within the segment. Base address and offset are comparator 2
It is compared with the segment limit at 7. The output of that comparator provides an error signal. Adder 26, which is part of the microprocessor, combines the base and offset to provide a "physical" address on line 31. That address can be used by the microprocessor as a physical address or used by a paging device. this is,
This is done to provide compatibility with many types of programs written for conventional microprocessors (Intel 286). In the case of Intel 286, the physical address space is 24 pintos.

Segment attributes, including details about the descriptors employed, such as the various priority levels, are described in US Pat. No. 4,442,484.

The break in FIG. 2 shows that segmentation mechanisms are known in the prior art! It is shown on the left side of 28.

The page field mapping block 30 including the page device of FIG. 1, and the interaction of the page field mapping with the page directory and page table stored in main memory are shown in FIGS. I'm clearly disappointed.

In the embodiment described here, the segmentation mechanism is a shadow register (5hadv register).
, but the segmentation mechanism can also be configured with cache memory, as is done with paging mechanisms.

Page Descriptor Cache Memory In FIG. 3, the page descriptor cache memory of page device 22 of FIG. 1 is shown within dashed line 22m. This cache memory consists of two arrays: content addressable memory (CAM) 34 and page data (BASE) 34;
A memory 35 is provided.

Both memories are made up of static memory cells.

The configuration of the memories 34 and 35 will be explained with reference to FIG. The specific circuitry used in CAM 34 and its unique masking features will be described with reference to FIGS. 7 and 8.

A line from the segment device 21 is coupled to a page device 22 whose address is shown in FIG. As shown in FIG. 3, this linear address comprises two fields: a page information field (20 bits) and a displacement field (12 bits). Also,
This is a 4-pin page attribute field configured by microcode. The 20 bit page information field is compared to the contents of CAM 34. Furthermore, 4
Two attribute focus (dirty)
J, 'valid J, l'-U/SJ and 'W/Rj) must also be munched to the attribute focus in the CAM before the hint occurs (as explained later, 'masking There is an exception to this when `` is used.) For hint conditions, memory 35 provides a 20-bit base word. The base word is combined into the linear address 012 focus displacement field as represented by adder 36 in FIG. The resulting physical address selects from the 4-byte page field in main memory 13.

A page address specification page directory 13m and a page table 13b for a no-hit state are stored in the main storage device 13 (see FIG. 4).

A base address for the page directory is provided by the microprocessor. The directory rebase is shown in FIG. 4 as page direct rebase 38.

The 10 bits of the page information field are used as an index (after being quadrupled) in the page directory, as shown by adder 40 in FIG. The page directory provides 32-bit words. 2 of this word
0 focus can be used as a base for page table −
It will be done. The other 10 focuses in the page information field are the 4th
It is also used as an index (after being quadrupled) in the page table, as shown by adder 41 in the figure. The pace chart also supports 32-bit language. The 20 bits of that word are the page pace of the physical address. This page base address is combined with a 12 bit displacement field in adder 42 to form a 32 bit physical address.

Five bits from the 12-bit field of the page directory and page table are used for the attributes, specifically "dirty", "accessed", "U/S", r_R/WJ and "present". These will be explained in detail later with reference to the fifth factor. The remaining bits in this field are unassigned.

Stored attributes from the page directory and page table are coupled to control logic 75 along with four bits of attribute information associated with the linear address. Parts of this logic circuit are shown in later figures. This will be explained with reference to those figures.

Page directory attributes Figure 5 shows page directory words, page index words,
The CAM word is shown again. The protection/control attributes assigned to the four bits of the page directory word are shown in brackets 43. The same four attributes with one additional attribute are used for the page lexicon and are shown in brackets 44. The four attributes used for the CAM word are shown in brackets 45.

Attributes are used for the following purposes:

1. “DIRTY J...This bit is
Indicates whether the page has received nine writes. When a page is written, its focus is changed.

This bit is used, for example, to inform the operating system that the entire page is not "clean." This focus is stored in the page table and CAM (not in the page directory). When a page is written, the processor sets its focus in the page table.

2) ACCESSED J - This bit is stored only in the page directory and page table (not CAM) and is used to indicate that a page has been accessed. When a page is accessed, its bits are changed in memory by the processor. Unlike the dirty bit, the bit indicates whether a page has been accessed for writing or reading.

3. rU/SJ...The state of this bit indicates whether the content of the page is accessible to the user and supervisors (binary "l") or accessible only to supervisors (binary "O"). ”).

4. l'-R/WJ . . . This write/read protection bit must be a binary "1" in order to be writable by a user-level program.

5. "Present (PRESKNT) J... This bit in the page table indicates whether the associated page resides in physical memory. This bit in the page directory indicates that the associated page world is in physical memory. Indicates whether it exists within.

6. [Parindo (VALID) J --- This focus, which is stored only in the CAM, is used to indicate whether the contents of Oy are valid. This bit is set to the 10th) state during initialization and then set to a valid Ω
Changed when the cause word is loaded.

Five bits from the page directory and page table are coupled to control logic 75 to provide the appropriate error signals within the microprocessor.

The user/supervisor (U/S) bits from the page directory and page table are ANDed as shown by gate 46 to provide the R/W bit stored in CAM 34 of FIG. . Similarly, read/write protection (R/W) from the page directory and page table
) bits are ANDed by gate 41 and C
Gives W/R focus stored in AM. Dirty bits from the page are stored in the CAM. These gates are part of the control logic circuit 75 shown in FIG.

Attributes stored in CAM are "automatic"
will be tested. The reason is that those attributes are treated as part of the address and matched to the 4 bits from the microcode. for example,
If the linear address indicates that a "user" write cycle is to occur within the page with R/W=0, an error condition will occur even if a valid page pace is stored in the CAM.

The AND operation of the U/S bits from the page directory and page table ensures that the "worst case" is stored in the cache memory. Similarly, the R/W AND operation provides the worst case to the cache memory.

Page Descriptor Cache Memory Configuration The CAM 34 is comprised of eight cents, each set containing four words, as shown in FIG. 21 bits (address 17, attribute 4) are used to find a match in this play.

Four comparator lines from the four words stored in each set are connected to the detector. For example, a comparator line for set 10) 4 words is connected to detector 53. Similarly, the comparator wires for 49 of each of sets 2-8 are connected to the detector. To determine which words in the set match the input to the CAM play (21 bits),
A detector examines the comparator wire. Each detector includes "hardwired" logic. The logic allows one of the detectors to be selected depending on the state of three bits from the 20-bit page information field coupled to the detector. (Note that the other 17 bins of this bitbage information field are coupled to the CAM array.) For purposes of illustration, assume that eight detectors are used in FIG. In the embodiment described herein, only one detector is used, and one detector is used for the three bits that select a set of four lines for coupling to the detector. The detector itself is shown in FIG.

The data storage portion of the cache memory is the play 35a~
It is organized into four plays shown as 35d.

The data words corresponding to each set of CAMs are distributed to 1
A word is stored in each of the four arrays. for example,
The data word (pace address) selected by the person with set 10) word 1 is in array 35a, and the data word (pace address) selected by the person with set 10) word 2 is in array 35b. etc. The three bits used to select the detector are also used to select the word within each play. therefore,
At the same time, a word is selected from each of the four plays.

The final selection of words from the array is done via a multiplexer. This multiplexer is controlled by four comparator lines in the detector.

When the cache memory is no longer accessed, a matching process, which is a relatively slow process, is initiated using 21 pins. The other three bits can immediately select a set of four lines, and a detector is made to detect the potential drop on the comparator lines.

(As explained later, all comparator (row) wires are pre-charged; selected (human) lines remain charged, while unselected lines are discharged.) At the same time, the selected (row) wires are discharged. Four words from the set are accessed in arrays 35a-35d. When a match occurs, the word in the set can be identified by the detector, and the information field is passed to multiplexer 5.
5 to enable data word selection. This configuration reduces cache memory access time.

Content Addressable Memory (CAM) The 21 bits associated with the CAM play are shown again in FIG. 17 of the 21 bits are coupled to complementary generator/override circuit 56, and 4 of the remaining bits are
The bits or attribute bits are coupled to VUDW logic 57. The three bits associated with detector selection described with reference to FIG. 6 are not shown in FIG.

Circuit 56 generates a true signal and a complement to the true signal for each address signal and couples the signals to parallel lines such as lines 59 and 60 in the CAM array. Similarly, VUDW logic circuit 57 generates a true signal and a complementary signal to the true signal for the attribute bit and couples those signals to the parallel lines in the υy play. Lines 59,60 are made in duplicate for each true focus line and each complementary focus line (ie, 21 pairs of bit and Z acupoint lines).

Each of the 32 rows in the CAM array has a pair of parallel row lines, such as line s 8.70. A normal static memory cell such as cell 67 is connected to each bit and each Z point line (column).
and associated with the line pair. In the embodiment described herein, the memory cell comprises a conventional seven lip-flop static memory cell using p-channel transistors.

Each row line pair (line 70) as data is written to the play.
One of the lines allows the memory cell to be coupled to the bit and the bit line. Otherwise, the contents of the memory cell are compared with the data on the column line and the result of the comparison is coupled to hint line 18.

The comparison is performed by a comparator associated with each cell. The comparator includes n-channel transistors 61 to
Consists of 64. Each transistor pair of the comparator, eg, transistors 61, 62, is coupled between one side of the memory cell and the focus line on the opposite side.

Assume that data is stored in memory cell 67 and the node of the cell closest to bit line 59 is at a high level. CA
When the contents of M are examined, first line 68 is precharged through transistor 69. The signal coupled to the CAM is then applied to the column line. First, line 59
Assume that is at a high level. Since line 60 is low, transistor 62 is not conductive. Since the side of the cell to which transistor 63 is connected is at a low level, transistor 63 does not become conductive.

In such conditions, line 6B is not discharged, indicating that a match has occurred in the cell. The hit line performs an AND operation of the comparisons that occur along the row.

If no match occurs, one or more comparators discharge the hit line.

During precharging, circuits 56 and 57 are override signals.
1 to bring all column lines (both bit and bit lines) low. This prevents the comparator from discharging the human line before the comparison begins.

Note that the comparator examines the "binary 1" condition and actually ignores the "binary O" condition.

That is, for example, when the gate of transistor 64 is high (line 59 is high), transistor 63
and 64 control the comparison. Similarly, when focus line 60 is high, transistors 61 and 62 control the comparison. This feature of the comparator allows cells to be ignored. Thus, if a word is coupled to the CAM, the bit can be masked from the matching process by bringing the bit and bit line low. This causes the contents of the cell to appear to match the states on the column lines. This feature is the VUDW logic circuit 5
Used by 7.

The microcode signal coupled to logic circuit 57 is
Bringing the bit and bit line for the selected focus of the attribute bit low as a function of the microcode focus. As a result, attributes associated with that focus are ignored. This operation is used, for example, to ignore the U/8 bit in supervisory mode.

That is, supervisory mode can access user data. Similarly, when reading or while running supervisor mode,
Read/write bits can be ignored.

Dirty bits can also be ignored when reading.

(This feature is not used for pared bits.

) When the attribute bits are stored in main memory, those attribute bits can be accessed and examined, and logic can be used to control the access operation based on the 1 state or O state of the U/S bit, for example. The circuit is used. However, separate logic is not used for cache memory. In fact, by bringing the focus and bit lines low, extra logic is provided by allowing matches (or preventing errors) even if the bit patterns of the attribute bits do not match.

As shown in FIG. 8, the detector from FIG.
It includes multiple NOR gates such as 1.82, 83.84. Three hint lines from the selected set of CAM lines are coupled to gate 81. Those lines are lines A and B
, C. Various combinations of those lines are connected to each other NOR gate. For example, NOR gate 84 receives hint lines, A, and B. The output terminal of each NOR gate is a NAND gate such as a NAND gate 86.
This is the input to the D gate. One hint line corresponds to each NA
It becomes one input of the ND gate. The hint line is NO
Not input to R gate (4 hint lines A, B, C
, D). That line is also the focus line from the cent entry to be selected. For example, gate 86 must select the cent associated with the hint line. For example, if NOR gate 810)
Tip #! D is coupled to NAND gate 86. Similarly, for NAND gate 90, hint line C is the input to gate 84 in addition to its output.

The enable read signal is also coupled to the NAND gate to prevent the output of this logic from being enabled for writing. NAND gate line 87
Outputs such as are used to control multiplexer 55 in FIG. In fact, the signal from the NAND gate on line 87 controls the multiplexer via the p-channel transistors. For illustrative purposes, an additional inverter 88 is shown to which an output line 89 is connected.

The advantage of this detector is that it allows the use of a precharge line for multiplexer 55. Alternatively, static equipment can be used, but this requires much more power. With the configuration shown in FIG. 8, the output from the inverter remains in the same state until the potential of one hit line drops. When a potential drop occurs, only one output line is reduced in potential to allow the multiplexer to select the correct word.

A unique address translation system has been described that uses two levels of cache memory for segmentation and paging. Independent data attribute control (eg, protection) is provided at each level.

[Brief explanation of the drawing]

Figure 1 is a block diagram showing the overall architecture of a microprocessor currently implementing the present invention, Figure 2 is a block diagram showing the segmentation mechanism implemented in the microprocessor of Figure 1, and Figure 3 is a page cache. Block diagram illustrating page field manipulating for hits or matches in memory, No. 4
Figure 3 is a block diagram illustrating page field mapping for no hints or no matches in the page cache memory of Figure 3, where page directories and page tables in main memory are used; Diagram used to show attributes stored in memory page directories and page worlds, Part 6
The figure is a block diagram showing the configuration of associative memory and data storage included in the page cache memory.
FIG. 7 is an electrical circuit diagram of a part of the associative memory shown in FIG.
FIG. 8 is an electrical circuit diagram of logic circuitry associated with the detector of FIG. 6. 13...Main storage device, 14...Bus interface device, 16...Decoder, 18...Execution device, 20...Address translation device, 21...Segment device , 22... page device, 27... comparator, 30... page field mapping block, 34... content addressable memory (CAM), 35
...Page data memory, 38..Page direct rebase, 53..Detector, 55..Multiplexer, 57..VUDW logic circuit, 67.
...Memory cell, 15...Control logic circuit. Patent Applicant Intel Corporation Agent
Masaki Yamakawa (ebi lambda 2 people) 4 chivalry 4

Claims (25)

[Claims] (1) A microprocessor device including a microprocessor and a data memory, the microprocessor having a segmentation mechanism for translating a virtual memory address to a second memory address and for controlling data based on attributes; a page cache memory integral with the microprocessor for receiving a first field of the second memory address and comparing it with its own contents to obtain a second field under certain conditions; a cache memory, the data memory including storage for page mapping data, and wherein the data memory includes storage for page mapping data;
fields of the page cache memory are coupled to the data memory to select a third field from the page data when the certain condition of the page cache memory is not met; one of which is combined with an offset field from the first address to obtain a physical address for the data memory, thereby improving the physical addressability of the data memory. A microprocessor device characterized by: (2) The microprocessor device according to claim 1, wherein the page cache memory and the storage for the page data include information on attributes of memory pages. . (3) The microprocessor device according to claim 2, wherein the storage for the page mapping data includes at least one page directory and at least one page table. Microprocessor device. (4) The microprocessor device according to claim 3, wherein each of the page directories and each of the page tables stores the attributes for the memory pages. (5) The microprocessor device according to claim 4, wherein at least some of the attributes stored in the page directory and the page table are logically combined to A microprocessor device characterized by being stored in a cache memory. (6) A microprocessor device according to claim 5, wherein the microprocessor provides a page directory rebase for the page directory. 7. The microprocessor device of claim 6, wherein the first portion of the first field provides an index to the page directory to a location within the page directory. microprocessor device. (8) The microprocessor device of claim 7, wherein the location in the page directory stores a page table base, and a second
3. A microprocessor device according to claim 1, wherein said section provides an index to said page table to a page table location within said data memory. 9. The microprocessor device of claim 8, wherein the location in the page table provides a base for a page in the data memory. (10) The microprocessor sensor device according to claim 2, wherein the page cache memory includes a content addressable memory (CAM) and a page base memory, and the output of the CAM is a page for the data memory. A microprocessor device characterized in that a base is selected from the page base memory. (11) A microprocessor device according to claim 10, wherein the content addressable memory stores attributes of data memory pages. (12) A microprocessor sensor device according to claim 11, wherein the associative memory includes means for selectively masking at least one of the attributes during the comparison. Characteristic microprocessor device. (13) a microprocessor including a microprocessor having a segmentation mechanism for translating a virtual memory address to a second memory address and for testing attributes of a data memory segment; and a data memory coupled to the microprocessor. The microprocessor includes a page cache memory integral with the microprocessor, the page cache memory including a first address of the second memory address.
and compares it with its own content to obtain a second field under certain conditions, the data memory includes storage for page mapping data, and the second memory includes storage for page mapping data; said first address
fields are coupled to the data memory to select a third field from the page data when the certain condition of the page cache memory is not met; , with an offset field from the first address to obtain a physical address for the data, thereby improving the physical addressability of the data memory. A microprocessor sensor device characterized by improved memory management. (14) The device according to claim 13,
The segmentation mechanism comprises a segment descriptor register integral to the microprocessor for providing a segment base, and the data memory includes a segment descriptor table accessed by the segment field of the first address. Microprocessor device. (15) The device according to claim 14,
A microprocessor device, wherein the page cache memory and the storage for page data include information about attributes of memory pages. (16) The device according to claim 15,
A microprocessor device, wherein the storage for the page mapping data comprises a page directory and a page table. (17) The device according to claim 16,
A microprocessor device, wherein each of the page directories and the page table stores the attributes for the memory pages. (18) The device according to claim 17,
A microprocessor device, wherein at least some of the attributes stored in the page directory and the page table are logically combined and stored in the page cache memory. (19) An address translation device formed as part of a microprocessor to operate with a data memory, comprising a segment descriptor register receiving a virtual address and providing a segment base, and a page cache memory, the microprocessor comprising: providing an address for a data memory to enable addressing of a segment descriptor table within the data memory, the segment descriptor table providing the segment base address; and providing a second memory address; The microprocessor takes the second base address and a portion of the virtual address, and the page cache memory receives the first field of the second memory address and compares it with its own contents. and providing a second field under a certain second condition; when the second condition is not met, the microprocessor provides the first field to a page data table in the data memory; for operating with a data memory, characterized in that the second field provides a page base to the data memory, thereby improving the physical addressability of the data memory. an address translation device formed as part of a microprocessor. (20) The device according to claim 19,
The apparatus of claim 1, wherein the segment descriptor register stores segment data attributes and the page cache memory stores page data. (21) a plurality of buffers receiving first signals and providing the first signals and a second signal that is the complement of the first signals; and a plurality of generally parallel wire pairs; each of the wire pairs is coupled to receive one of the first and second signals, and the wire pairs are coupled between each wire pair and arranged in a row generally perpendicular to the wire pair. a plurality of row comparator lines each associated with said respective row of cells; and a plurality of row comparator lines each associated with said respective row of cells; a plurality of comparators coupled between each memory cell and its respective line pair and the comparator line; loading means for loading data from the line pair into the cell; and, wherein the comparator is disabled when both of the respective line pairs of the comparator are held in some binary state, thereby disabling the certain binary signal from at least some of the buffers. A content addressable memory device characterized in that a state is applied to the first signal and the second signal, and a selected one of the cells can be ignored for the comparison. (22) The device according to claim 21,
The apparatus characterized in that the row comparator wire is a precharged wire. (23) The device according to claim 22,
a storage memory, the storage memory comprising a plurality of parts, characterized in that data is accessed simultaneously in all said parts, and an output from one of said parts is selected through said row line. Device. (24) The device according to claim 23,
Apparatus comprising detectors coupled to a predetermined number of said row wires, said detectors detecting which of said predetermined number of wires remains charged. (25) The device according to claim 24,
Apparatus, characterized in that the selection of the output from one of the parts is performed by the detector.