JPS61285523A - Clock switching circuit - Google Patents

Abstract

PURPOSE:To reduce the generation of glitch by selecting a designated clock in response to the control signal which designates one of plural clocks and the feedback output clock. CONSTITUTION:If the clock delivered presently as an output clock phiOUT is equal to the 1st clock phi1, the control signal (l) is changed to a low level from a high level to switch the 2nd control signal. Thus the 2nd flip-flop FF2 is reset by the change of the signal (l) and synchronously with the fall of the clock phi1. Then the 3rd flip-flop FF3 becomes enable and is set synchronously with the next fall of the 2nd clock phi2. The clock phiOUT is toothless in a switching mode owing to a series of said actions and changed into the clock phi2. Thus no glitch is produced.

Description

[Detailed Description of the Invention] [Technical Field] The present invention relates to a floppy disk, a hard disk, etc., in which a plurality of clocks, such as a write (WRITE) system clock and a read (READ) system clock, have mutually different phases and frequencies. The present invention relates to a clock switching circuit that selects and outputs one clock from the plurality of clocks in the system.

[Prior art]

Conventionally, in the simplest circuit configuration of this type of clock switching circuit, as shown in FIG.
An AND gate that performs a logical AND operation between the control signal and the control signal, and the inverted signal of the control signal that is inverted by the inverter and the clock φ
2, and an OR gate that performs a logical OR operation on the outputs of both AND gates.
Both clogs φ1. Normally, φ2 is selected and switched by a control signal statement to become the output clock φout. However, as can be seen from the timing chart shown in FIG.
Sometimes, glitches like the one shown in this figure will occur. The occurrence of this glitch is originally due to the previous clock φ1. This is because the phases of φ2 are not the same, and this glitch caused by the phase shift often causes malfunctions in peripheral circuits.

〔the purpose〕

An object of the present invention is to eliminate the above-mentioned drawbacks and to provide a clock switching circuit that prevents glitches from occurring when selecting one clock from a plurality of n clocks using n+1 flip-flops. .

In order to achieve this object, the present invention provides a plurality of n clocks φ1 to φ having different frequencies and phases.

One clock φx (X-1
~n), which selectively outputs a clock φx, includes a flip-flop that enables only the output that corresponds to the level change of the control signal among the n outputs in response to the input of the clock φx that is currently being selectively output, and this flip-flop. The present invention is characterized in that glitches can be prevented by outputting n flip-flops according to the output of the flip-flop.

Another aspect of the present invention is that the present invention is provided with an AND-OR gate that individually performs an AND operation on the outputs of the n flip-flops and clocks φ1 to φn and outputs one clock φx specified by a control signal. It is characterized by

〔Example〕

The present invention will be described in detail below with reference to one drawing.

FIG. 3 shows an example of the circuit configuration of the present invention, and FIG. 4 is a timing chart thereof. That is, FIG. 3 is the simplest configuration example of the present invention when one clock is selected from two types of clocks, where the sentences are control signals for switching, and φl, φ2°φout are the signals shown in FIG. 1. With a signal similar to φ1
．． φ2 is a clock with different frequency and phase, φo
ut is the selected output clock. Also, FFI~
FF3 is an FK flip-flop, and Gl is an and-or gate.

A control signal is input to the J input of the first J- flip-flop FFI, and an inverted signal obtained by inverting the control signal by an inverter is input to that input, and its Op (clock)
A feedback clock φout, which will be described later, is input to the input, and its R
An initial reset signal is input to the input. second J
The Q output of the flip-flop FFI is input to the J input and R input of the flip-flop FF2 to the first J-, and the first clock φ1 is input to the Cp large input of the FF2. Also, J of flip-flop FF3 is connected to the third J-.
A flip-flop F is connected to the first J- input and the R input.
The possible output of FI is input, and the Cp large input of FF3 is the second
The clock φ2 is input.

Furthermore, the first clock φ1 and the Q output of the flip-flop FF2 are input to the second J- to one of the 17th AND gates constituting the AND/OR game) Gl, and the second The Q output of the flip-flop FF3 is input to the clock φ2 and the third J-, and the output φout of the OR gate to which the outputs of the first and second AND gates are input is simultaneously outputted to the outside as described above. , the Cp large input of flip-flop FF2 is fed back to the second J-.

In the above configuration, if the clock that has been output as the output clock φout is the first clock φ1 as shown in FIG. 4, in order to switch to the second clock φ2, the control signal must be In order to select clock φ2 of 2, high level (HIG) I) to low level (LO
Changes to W). This change causes the first clock φ!
In synchronization with the falling edge of FF2, the second flip-flop FF2
is reset and the third flip-flop FF3 is enabled (ENABLE). The third flip-flop FF3 is set in synchronization with the next falling edge of the second clock φ2. Through this series of operations, the output clock φout changes from clock φ1 to φ2 as shown in FIG.
At the time of switching, the waveform becomes the state waveform, and the second clock t
i) Since the transition is made to 2, the glitch as shown in FIG. 2 does not occur.

Furthermore, when switching from the second clock φ2 to the first clock φ, the operation is similar, and the output clock φout changes from the clock φ2 to φ as shown in FIG.

When switching, the tooth extraction becomes a state waveform, and the glitch as shown in Fig. 2 does not occur.In other words, when the clock φout that has been selected and output is the second clock φ2, the control signal is low. When changing from a level to a high level,
The third flip-flop FF3 is reset in synchronization with the rise of the second clock φ2, and the second flip-flop FF2 is enabled. The second flip-flop FF2 is set in synchronization with the next fall of the first clock φi. Through this series of operations, the output clock φ
As shown in FIG. 4, out has the waveform of the tooth extraction state when the clock φ1→φ2 is switched.

FIG. 5 shows a configuration example of the present invention in a case where n claw sources are to be selected, and FIG. 6 is a timing chart thereof. Here, φ1 to φn are a plurality of n clocks with different frequencies and phases, φout is a selected clock output, FFI to FFn are n flip-flops, G1 is an AND-OR gate, and FFn+1 is a It is a flip-flop with an input and an output.

In addition, -1 to ln are the above-mentioned flip-flops FFn
+1 n outputs. 1fxin are n control inputs of flip-flop FFn+1, and n clocks φ! It is an encoded signal that instructs which clock to select among ~φn, and always selects one of i2(
iml~n) is “1” and all other signals are “1”.
0”, the output 1-1 of the flip-flop FFn÷1
-1-2 are individually input to the J input and R input of the corresponding flip-flops FFI to FFn. Further, the clocks φ1 to φn are individually inputted to the corresponding AND gates in the AND gate group of the AND gates of the corresponding FFI-FFn cp large input and AND/OR game) G1. The Q output of each flip-flop FFI to FFn is individually input to one input terminal of the corresponding AND gate, and the AND operation result with the corresponding clock φi to φn is passed through Gl and externally as the output clock φout. is output to. At the same time, this output clock φout is fed back and inverted via an inverter, and this inverted signal is input to Cp of the flip-flop FFn◆1.

In the above configuration, now the output clock φout is Φo
The control signal i1~in is set to 12m1 so that the second clock φ2 is selected when the clock signal ut is output as φ1.
．． Assuming that the change is from il to inmb (other than i2), the falling i? of the first clock φ1 as shown in FIG.
1-2g+1.1-1m0. l −3w 1−nm0
Then, the second flip-flop FF2 is enabled, and the flip-flops FFI and FF3 to FFn are all reset.

Next, in synchronization with the fall of the second clock φ2, the second
The flip-flop FF2 is set, and the second clock φ2 is selectively output from the next output of the second clock φ2 as the output clock φout.

In other words, when switching from φ1 to φ2, the output clock φout becomes the waveform of the tooth extraction state, and the second clock φout becomes the waveform of the tooth extraction state.
2, the glitch as shown in FIG. 2 does not occur. Furthermore, when switching from clock φ2 to φn, the operation is similar to that described above, and the waveform of output clock φout becomes a toothless state.

In this way, when selecting one clock from among n clocks with different frequencies and phases, this selection is performed using n J- flip-flops, one n-input EFI output flip-flop, and one This can be realized using the AND-OR gate, and the occurrence of glitches can be easily avoided.

〔effect〕

As explained above, according to the present invention, a group of flip-flops and an AND-OR gate are used to respond to a control signal specifying one clock among a plurality of n clocks and a feedback output clock φn. Since the specified clock is selectively outputted using the clock, it is possible to provide a clock switching circuit that can perform claw 2 switching without generating glitches.

[Brief explanation of drawings]

FIG. 1 is a circuit diagram showing the configuration of a conventional circuit, FIG. 2 is a timing chart showing its operation, and FIG. 3 is a circuit diagram showing an example of the configuration of the circuit of the present invention. FIG. 4 is a timing chart showing an example of its operation, and FIG. 5 is a circuit diagram showing another example of the configuration of the circuit of the present invention. FIG. 6 is a timing chart showing an example of the operation. FFI, FFn+1...Flip-flop, FF2~
FFn--flip-flop, G--and-or gate, look, look-1, 1-2 to l-n...control signal. φ1. φ2 to φn...Clock, φout...Output clock. $-e, ~ 5 9゜Figure 5

Claims (1)

[Claims] A plurality of n clocks φ_1~ with different frequencies and phases
One clock φ_x specified by the control signal from φ_n
In a clock switching circuit that selectively outputs (x=1 to n), only the output that corresponds to the level change of the control signal is enabled among the n outputs according to the input of the clock φ_x that is being selectively output. A clock switching circuit characterized in that glitches are prevented by a flip-flop and the outputs of n additional flip-flops according to the output of the flip-flop.