JPS61255441A - Information processer - Google Patents

Abstract

PURPOSE:To discover the erroneous data by storing the data following the request and the output of the parity converting circuit to a data buffer and checking the parity from the data read from the data buffer and the output of the parity converting circuit. CONSTITUTION:Usually, at the time of operation, for data 14 from a demander data processing device 1, a part is inverted or the data are written in a data buffer 5 as they are, by the first data converting circuit 4 according to the indication of the first register 3, and the first register 3 is up dated by the first control circuit 2 after prescribed times of a request 11 are received. Next, data 16 are read from a data buffer 5, and the second register 7 is up dated by the second control circuit 6 after prescribed times of a request receiving signal 22 from a request receiving circuit 23 are received. For data 16 read from a data buffer 5, in accordance with the indication of the second register 7 corresponding to the register 3, a part is inverted or the data are sent to a data checking circuit 9 by the second data converting circuit 8 as they are, and the error is detected.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to failure detection in a data processing device, and particularly to a method for detecting errors in the order of data accompanying multiple requests.

[Conventional technology]

Conventionally, in this type of information processing apparatus, regarding data processing between each apparatus, a data buffer that stores data from a requesting data processing apparatus, a first counter that provides a write address of the data buffer, and the data buffer A second counter provides a read address of .

[Problem that the invention seeks to solve]

The data accompanying the request from the requesting data processing device is written into the data buffer (-) according to the write address given by the first counter, and then the first counter is updated. Data is read from the data buffer according to the read address given by the counter, and the second counter is updated.

For example, suppose that the first counter fails and the write address becomes fixedly 0.

Data accompanying subsequent requests from the requesting data processing device will be written to the same address (address 0). Then, the data subsequently read from the data buffer by the read address given by the second counter will no longer match the data accompanying the request from the requesting data processing device. When such a failure occurs, the conventional failure detection method of performing a parity check on data with a parity bit added cannot detect the failure, resulting in garbled data and failure of the information processing device. This had the disadvantage of reducing reliability.

[Purpose of the invention]

An object of the present invention is to invert and write part or all of the data using a data conversion circuit according to the number of requests when writing data associated with a request to a data buffer, and when reading data according to the number of requests accepted by the data conversion circuit. The above drawback can be solved by inverting part or all of the data to determine whether the read data corresponds to the request to be processed, and data garbled data can be detected. west,
An object of the present invention is to provide an information processing device with improved reliability.

[Means for solving problems]

As shown in FIG. 1, the information processing device of the present invention includes a request source data processing device 1 and a request signal 11 from the request source data processing device 1.
a data buffer 5 that stores data 14 associated with the conversion after being converted by a first data conversion circuit 4; and a first register that stores first identification information 12 in response to a request signal 11 from the requesting data processing device 1. 5, a first control circuit 2 that updates the first register 3 in response to a request signal 11 from the requesting data processing device 1; and a first control circuit 2 that updates the first register 3 according to an instruction from the first register 3;
a first data conversion circuit 4 that inverts part or all of the write data 14 for the request signal 11;
a second register 7 that stores second identification information 17 in response to a request acceptance signal 22 from a request acceptance circuit 23; and a data buffer 5 at the time of request acceptance.
A part or all of the data 16 read from the second
A second data conversion circuit 8 that inverts the data according to the instruction of the register 7, a $2 control circuit 6 that updates the second register 7 in response to the request acceptance signal 22, and the second data conversion circuit 8. Inverted data 19
The data check circuit 9 includes a data check circuit 9 that checks the validity of the data, and an error detection circuit 10 that sends out an error report signal 21 when the data check circuit 9 detects an abnormality.

[For production]

- data conversion circuit 4 inverts a portion of the data and writes it as is into data buffer 5, and first register 3 is updated by first control circuit 2 after receiving request 11 a predetermined number of times. Then, data 16 is read out from data buffer 5.

The second register 7 is updated by the second control circuit 6 after receiving the request acceptance signal 22 from the request acceptance circuit 26 a predetermined number of times. The data 16 read from the data buffer 5 is transferred to the instruction 1 of the second register 7 corresponding to the first register 3; therefore, a part of the data 16 is inverted by the second data conversion circuit 8, or it is directly sent to the data check circuit 9. It is checked for errors, and if there is an error, an error is reported by the error detection circuit 10.

Here, the instructions on whether to invert a part of the data of the first Yuta 3) 1 the second, , > Yuta 7 will always match as long as the royal palace is operating with respect to the same request data. ing.

However, for example, when a failure occurs, the read address when reading data buffer 5 becomes fixed.

Even though the data associated with the real request was written partially inverted, a case may occur where data that is not partially inverted due to a failure is read, resulting in a parity error and the failure being detected.

〔Example〕

Hereinafter, one embodiment of the present invention will be described in detail with reference to the drawings.

FIG. 2 is a circuit diagram showing the configuration of an embodiment of the present invention.

In FIG. 2, there are two information processing apparatuses according to the present invention.

Request 1 from the requesting data processing device (not shown)
01 and associated data 108! a first counter 202 that is updated by the output 102 of the register 201; a first parity conversion circuit 204 that inverts the parity bit output 110 of the register 203 by the output 103 of the first counter 202; The output 102 of the register 201 is set as a write enable, the output 104 of the first counter 202 is set as a write address, and the output 109 of the register 203 and the output 11 of the parity conversion circuit 204 are set as a write enable.
1, a second counter 206 that is updated by the request source data number 107, and the parity bit output 113 read from the data buffer 205 is inverted by the output 106 of the second counter 206. and a parity check circuit 208 that performs a parity check using the output 112 of the data buffer 205 and the output 114 from the second parity conversion circuit 207.

Here, the first counter 202 is a 5-pit counter, and its MOB is a control signal 103 for determining whether or not to invert the parity bit output 110 to the first parity conversion circuit 204, and the remaining lower 4 bits are for the data buffer. 2
This is an address signal 104 indicating a write address of 05.

Similarly, the second counter 206 is also a 5-pit counter, and its MSB is a control signal 1 to the second parity conversion circuit 207 to determine whether or not to invert the parity pit output 116.
'06, and the remaining lower 4 bits are data buffer 2.
This is an address signal 105 indicating a read address of 05. The first counter 202 is connected to the first control circuit 2 in FIG.
The second counter 206 has the functions of both the second control circuit 6 and the second register 7 in FIG.

Parity check circuit 208 has the functions of both data check circuit 9 and error detection circuit 10 in FIG. Further, the request reception circuit 209 has a function of monitoring whether reception is possible due to busy status.

During normal operation, the first counter 202 outputs the data 109 accompanying the request 101 from the requesting data processing device and the output 111 of the parity conversion circuit 204 to the data buffer 202.
5 is simultaneously updated by +1, and the lower 4 bits excluding the MSB indicate the write address of data associated with the next request. When the request acceptance circuit 209 accepts the request 102, the data 112 and the parity bit output 113 are read out from the second filter 205, and the second counter 206 receives the request acceptance signal 107.
1m, it is updated by +1 and indicates the primary read address.

The parity corresponding to the data 112 read from the data buffer 205 is the output 114 of the second parity conversion circuit 207, and normally does not cause a parity error.

However, due to some kind of failure 9, for example, the first counter 202
If the data buffer 205 malfunctions and updates are no longer performed, the write address to the data buffer 205 is fixed to, for example, address 0, and data associated with subsequent requests will always be written to the same address (address 0) 1:. In this embodiment, the output 111 of the first parity conversion circuit 204 written to the data buffer 205 is
Since the output 103 (MSB) of 02 does not change, it continues to be converted to even parity or odd parity.

However, the second counter 206 is updated by the request acceptance signal 107, and the parity bit output 113 read from the data buffer 205 is updated by the second counter 206 whose input is the output 106 (MSB) of the second counter 206. Since the signal is inverted or output as is by the parity conversion circuit 207, a parity error occurs. This is detected by the parity check circuit 208 and an error report signal 115 is sent to report the failure.

〔Effect of the invention〕

As explained above, the present invention can store data associated with a request and the output of a parity conversion circuit in a data buffer, and perform a parity check on the data from the data read from the data buffer and the output of the parity conversion circuit. With this configuration, it is possible to discover failures that cause data corruption that could not be discovered conventionally.

Remaining days below

[Brief explanation of drawings]

FIG. 1 is a block diagram showing the configuration of the present invention, and FIG. 2 is a circuit diagram showing the configuration of one embodiment of the present invention. DESCRIPTION OF SYMBOLS 1... Request source data processing device, 2... First control circuit, 3... First register, 4... First data conversion circuit, 5... Data buffer, 6... - Second control circuit, 7... Second register, 8... Second data conversion circuit, 9... Data check circuit, 10... Error detection circuit, 11... Request signal, 12...
Control signal, 16...Control signal, 14...Data signal, 15...Data signal, 16...-Data signal. 17... Control signal, 18... Control signal, 19...
Data signal, 20... Control signal, 21... Error report communication counter, 203... Data register, 204...
XOR times m (exclusive OR circuit), 205...data buffer, 206...second counter, 2o7...
XOR circuit (exclusive OR circuit), 208... Parity check circuit, 209... Request reception circuit, 1
01...Request signal, 102...Control signal, 1
03...Control signal. 104... Write address signal, 105... Read address signal, 106... Control signal, 107... Request acceptance signal, 108... Data signal, 109...
...Data signal, 110...Parity bit signal, 1
11... Parity bit signal, 112... Data signal, 115... Parity bit signal, 114... Parity bit signal. 115...Error report signal.

Claims (1)

[Claims] 1. In an information processing device that includes multiple data processing devices, regarding data transfer between each device, a data buffer that stores data from the requesting data processing device and an instruction as to whether or not to invert part of the written data are provided. first to give
a first control circuit for inverting the first register in response to a request from the requesting data processing device; and a first control circuit for inverting a part of the data written to the data buffer by the first register a first data conversion circuit that inverts a portion of the data written to the data buffer when instructed; a second register that provides an instruction as to whether or not a portion of the data read from the data buffer is to be inverted; , when the second control circuit inverts the second register in response to a request acceptance signal for the request and the second register instructs to invert a part of the data read from the data buffer; a second data conversion circuit that inverts a portion of the data read from the data buffer; a data check circuit that detects whether there is an error in the data output from the second data conversion circuit; and the data check circuit. and an error detection circuit that sends out an error report signal when an error is detected in the data output from the second data conversion circuit.