JPS6122651A - Manufacture of semiconductor device - Google Patents
Manufacture of semiconductor deviceInfo
- Publication number
- JPS6122651A JPS6122651A JP59135444A JP13544484A JPS6122651A JP S6122651 A JPS6122651 A JP S6122651A JP 59135444 A JP59135444 A JP 59135444A JP 13544484 A JP13544484 A JP 13544484A JP S6122651 A JPS6122651 A JP S6122651A
- Authority
- JP
- Japan
- Prior art keywords
- layer
- wiring
- silicon
- opening
- tungsten
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 14
- 238000004519 manufacturing process Methods 0.000 title claims description 5
- 239000000758 substrate Substances 0.000 claims abstract description 11
- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical compound [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 claims abstract description 7
- 229910052721 tungsten Inorganic materials 0.000 claims abstract description 7
- 239000010937 tungsten Substances 0.000 claims abstract description 7
- 229910052710 silicon Inorganic materials 0.000 claims description 14
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims description 12
- 239000010703 silicon Substances 0.000 claims description 12
- 150000003377 silicon compounds Chemical class 0.000 claims description 10
- 238000000151 deposition Methods 0.000 claims description 6
- 239000010410 layer Substances 0.000 abstract description 84
- 239000011229 interlayer Substances 0.000 abstract description 7
- 238000000034 method Methods 0.000 abstract description 7
- 150000001875 compounds Chemical class 0.000 abstract description 4
- 239000011248 coating agent Substances 0.000 abstract description 2
- 238000000576 coating method Methods 0.000 abstract description 2
- 238000004544 sputter deposition Methods 0.000 abstract description 2
- WQJQOUPTWCFRMM-UHFFFAOYSA-N tungsten disilicide Chemical compound [Si]#[W]#[Si] WQJQOUPTWCFRMM-UHFFFAOYSA-N 0.000 abstract description 2
- 229910021342 tungsten silicide Inorganic materials 0.000 abstract description 2
- 238000005229 chemical vapour deposition Methods 0.000 abstract 1
- 230000002542 deteriorative effect Effects 0.000 abstract 1
- 239000007789 gas Substances 0.000 description 4
- 239000005360 phosphosilicate glass Substances 0.000 description 4
- 238000006243 chemical reaction Methods 0.000 description 3
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 3
- XKRFYHLGVUSROY-UHFFFAOYSA-N Argon Chemical compound [Ar] XKRFYHLGVUSROY-UHFFFAOYSA-N 0.000 description 2
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 2
- PNEYBMLMFCGWSK-UHFFFAOYSA-N aluminium oxide Inorganic materials [O-2].[O-2].[O-2].[Al+3].[Al+3] PNEYBMLMFCGWSK-UHFFFAOYSA-N 0.000 description 2
- 239000003085 diluting agent Substances 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 238000005530 etching Methods 0.000 description 2
- QKCGXXHCELUCKW-UHFFFAOYSA-N n-[4-[4-(dinaphthalen-2-ylamino)phenyl]phenyl]-n-naphthalen-2-ylnaphthalen-2-amine Chemical compound C1=CC=CC2=CC(N(C=3C=CC(=CC=3)C=3C=CC(=CC=3)N(C=3C=C4C=CC=CC4=CC=3)C=3C=C4C=CC=CC4=CC=3)C3=CC4=CC=CC=C4C=C3)=CC=C21 QKCGXXHCELUCKW-UHFFFAOYSA-N 0.000 description 2
- 239000002356 single layer Substances 0.000 description 2
- TXEYQDLBPFQVAA-UHFFFAOYSA-N tetrafluoromethane Chemical compound FC(F)(F)F TXEYQDLBPFQVAA-UHFFFAOYSA-N 0.000 description 2
- NXHILIPIEUBEPD-UHFFFAOYSA-H tungsten hexafluoride Chemical compound F[W](F)(F)(F)(F)F NXHILIPIEUBEPD-UHFFFAOYSA-H 0.000 description 2
- QYKABQMBXCBINA-UHFFFAOYSA-N 4-(oxan-2-yloxy)benzaldehyde Chemical compound C1=CC(C=O)=CC=C1OC1OCCCC1 QYKABQMBXCBINA-UHFFFAOYSA-N 0.000 description 1
- IJGRMHOSHXDMSA-UHFFFAOYSA-N Atomic nitrogen Chemical compound N#N IJGRMHOSHXDMSA-UHFFFAOYSA-N 0.000 description 1
- 229910008814 WSi2 Inorganic materials 0.000 description 1
- 229910052782 aluminium Inorganic materials 0.000 description 1
- 229910052786 argon Inorganic materials 0.000 description 1
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 description 1
- YXTPWUNVHCYOSP-UHFFFAOYSA-N bis($l^{2}-silanylidene)molybdenum Chemical compound [Si]=[Mo]=[Si] YXTPWUNVHCYOSP-UHFFFAOYSA-N 0.000 description 1
- 230000008021 deposition Effects 0.000 description 1
- 238000001312 dry etching Methods 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 239000003292 glue Substances 0.000 description 1
- 239000001307 helium Substances 0.000 description 1
- 229910052734 helium Inorganic materials 0.000 description 1
- SWQJXJOGLNCZEY-UHFFFAOYSA-N helium atom Chemical compound [He] SWQJXJOGLNCZEY-UHFFFAOYSA-N 0.000 description 1
- 230000010354 integration Effects 0.000 description 1
- 238000004518 low pressure chemical vapour deposition Methods 0.000 description 1
- 239000000203 mixture Substances 0.000 description 1
- 229910021344 molybdenum silicide Inorganic materials 0.000 description 1
- 239000001301 oxygen Substances 0.000 description 1
- 229910052760 oxygen Inorganic materials 0.000 description 1
- 238000005268 plasma chemical vapour deposition Methods 0.000 description 1
- 238000001020 plasma etching Methods 0.000 description 1
- 238000000927 vapour-phase epitaxy Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/76877—Filling of holes, grooves or trenches, e.g. vias, with conductive material
- H01L21/76879—Filling of holes, grooves or trenches, e.g. vias, with conductive material by selective deposition of conductive material in the vias, e.g. selective C.V.D. on semiconductor material, plating
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/76877—Filling of holes, grooves or trenches, e.g. vias, with conductive material
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/76886—Modifying permanently or temporarily the pattern or the conductivity of conductive members, e.g. formation of alloys, reduction of contact resistances
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
- H01L29/45—Ohmic electrodes
- H01L29/456—Ohmic electrodes on silicon
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Manufacturing & Machinery (AREA)
- Ceramic Engineering (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
Abstract
Description
【発明の詳細な説明】
〔産業上の利用分野〕
本発明は半導体装置の製造方法に係り、多層配線の層間
接続方法に関する。DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a method for manufacturing a semiconductor device, and more particularly to a method for connecting layers of multilayer wiring.
半導体装置の高集積化、高密度化に伴い多層配線構造が
用いられるようになり、この場合層間接続は層間絶縁層
にコンタクト孔を開けて上下の配線層を接続することに
より行っている。With the increasing integration and density of semiconductor devices, multilayer wiring structures have come into use, and in this case, interlayer connections are made by forming contact holes in interlayer insulating layers to connect upper and lower wiring layers.
また半導体装置を構成する素子は微細化され、コンタク
トホールの形状は開口幅に比し深さが大きくなり、配線
層被着に際し段差被覆が悪くなり半導体装置の信頼性を
著しく阻害する。Furthermore, as elements constituting semiconductor devices become smaller, the depth of contact holes becomes larger than the width of the opening, and step coverage becomes poor when wiring layers are deposited, which significantly impairs the reliability of semiconductor devices.
従って上下の配線層の接続を完全に行って、しかも基板
表面を平坦化する方法が種々試みられている。Therefore, various methods have been attempted to completely connect the upper and lower wiring layers and to flatten the substrate surface.
第２図は従来例により、第１の配線層上の絶縁層に開口
されたコンタクトホールに第２の配線層を被着した状態
を示す断面図である。FIG. 2 is a sectional view showing a state in which a second wiring layer is applied to a contact hole opened in an insulating layer on a first wiring layer according to a conventional example.
第２図（ａ）において、１は半導体基板で珪素基板を用
い、基板上に被着された絶縁層を介して第１の配線層２
としてアルミニウム（Ａ１）を被着し、さらにその上に
絶縁層３として燐珪酸ガラス（ＰＳＧ）を厚さ約１μｍ
成長し、ここに開口されたコンタクト孔を覆って、第２
の配線層４として八１を被着した状態を示す。In FIG. 2(a), 1 is a semiconductor substrate using a silicon substrate, and a first wiring layer 2 is connected through an insulating layer deposited on the substrate.
Aluminum (A1) is deposited on top of this as an insulating layer 3, and phosphosilicate glass (PSG) is deposited to a thickness of approximately 1 μm as an insulating layer 3.
A second layer grows and covers the contact hole opened here.
81 is shown as the wiring layer 4 of FIG.
第２図ｆｂｌにおいて、第２の配線層４の被着時に、段
差部に掻く僅かの庇カ月詩的にでも生ずると、庇は第２
の配線層４の被着の進行に従って大きく成長して、段差
部に深い亀裂を生ずるようになる。In FIG. 2 fbl, when the second wiring layer 4 is deposited, if even a slight eave is scratched on the stepped portion, the eaves will be removed from the second wiring layer 4.
As the deposition of the wiring layer 4 progresses, it grows to a large extent, causing deep cracks at the stepped portions.
これを防止するため絶縁層３をメルトフローして開口部
の肩をなだらかにしているが、開口幅が小さくなった場
合は段差被覆が悪くなり、信頼性を劣化させる。In order to prevent this, the insulating layer 3 is melt-flowed to make the shoulder of the opening smooth, but if the width of the opening becomes small, the step coverage becomes poor and the reliability deteriorates.
第３図は他の従来例による層間接続の状態を示す断面図
である。FIG. 3 is a sectional view showing the state of interlayer connections according to another conventional example.
図において、第１の配線層２の上に被着した絶縁層３の
開口部の底に、モリブデン・シリサイド（ＭｏＳ ｉ２
）層５を被着し、この上にタングステン（讐）を選択成
長させてコンタクト孔を埋める。この場合にの選択成長
は成長速度が遅く、約１μｍの孔を埋めることば極めて
賄しい。In the figure, molybdenum silicide (MoS i2
) layer 5 is deposited on which tungsten is selectively grown to fill the contact hole. In this case, selective growth has a slow growth rate, and it is extremely convenient to fill holes of about 1 μm.
〔発明が解決しようとする問題点〕
半導体装置の微細化に伴い、第１の配線層上に被着され
た眉間絶縁層に形成されたコンタクト孔の形状が深さに
比し開口幅が小さくなると、第２の配、線層被着に際し
段差被覆が悪くなり半導体装置の信頼性を著しく阻害す
る。[Problems to be Solved by the Invention] With the miniaturization of semiconductor devices, the shape of the contact hole formed in the glabella insulating layer deposited on the first wiring layer has an opening width smaller than the depth. In this case, the step coverage becomes poor when the second interconnection layer is deposited, which significantly impairs the reliability of the semiconductor device.
そのため前記コンタクト孔を低抵抗層で埋め込む方法が
試みられているが、生産工程に適用して効果的な方法が
なかった。For this reason, attempts have been made to fill the contact hole with a low resistance layer, but there has been no effective method that can be applied to the production process.
上記問題点の解決は、基板上に被着された第１の配線層
上に絶縁層を被着し、該絶縁層に開口部を設けて該第１
の配線層を表出する工程と、該開口部を覆って珪素層も
しくは珪素化合物層を被着する工程と、該珪素層もしく
は珪素化合物層の開口部内の部分を残して該絶縁層上の
部分を除去する工程と、該開口部内に残った該珪素層も
しくは珪素化合物層をタングステン層に変換し、該タン
グステン層を覆って第２の配線層を被着する工程を有す
る本発明による半導体装置の製造方法により達成される
。The above problem can be solved by depositing an insulating layer on the first wiring layer deposited on the substrate, and providing an opening in the insulating layer.
a step of exposing the wiring layer, a step of depositing a silicon layer or a silicon compound layer covering the opening, and a step of exposing a portion of the silicon layer or silicon compound layer on the insulating layer, leaving a portion inside the opening. and converting the silicon layer or silicon compound layer remaining in the opening into a tungsten layer, and depositing a second wiring layer covering the tungsten layer. This is achieved by a manufacturing method.
本発明によれば、層間絶縁層のコンタクト孔内にＣＶＤ
やスパッタ等を用いて極めて容易に珪素（Ｓｉ）やＳｉ
化合物を埋め込むことができ、埋め込み後−に変換して
低抵抗化することにより、接触抵抗を増大させることな
く、段着被覆を改良して信頼性を向上することができる
。According to the present invention, CVD is formed in the contact hole of the interlayer insulating layer.
Silicon (Si) and Si
By embedding a compound and converting it into a low resistance after embedding, it is possible to improve the stepped coating and improve the reliability without increasing the contact resistance.
Ｗの変換は六弗化タングステン（ＷＦＪ を用いて、つ
ぎの化学反応によって行う。The conversion of W is carried out by the following chemical reaction using tungsten hexafluoride (WFJ).
Ｗｈ＋５ｉ−４１Ｎ−５ｉＦ４
〔実施例〕
第１図は本発明による層間接続の状態を工程順に示す断
面図である。Wh+5i-41N-5iF4 [Example] FIG. 1 is a sectional view showing the state of interlayer connection according to the present invention in the order of steps.
第１図（ａｌにおいて、１は半導体基板で珪素基板を用
い、基板上に被着された絶縁層を介して第１の配線層２
として厚さ約１μｍのＡＩを被着し、さらにその上に気
相成長（ＣＶ Ｄ）法を用いて絶縁層３としてＰＳＧを
厚さ約１μｍ成長する。In FIG. 1 (al), 1 is a semiconductor substrate, and a silicon substrate is used, and a first wiring layer 2 is connected via an insulating layer deposited on the substrate.
As an insulating layer 3, AI is deposited to a thickness of about 1 μm, and then PSG is grown to a thickness of about 1 μm as an insulating layer 3 using a vapor phase epitaxy (CVD) method.
つぎに通常のりソゲラフイエ程を用いてバクーニングし
て、ドライエツチングによりコンタクト孔を形成する。Next, a contact hole is formed by dry etching and vacuuming using a normal glue sockeye process.
第１図（ｂｌにおいて、コンタクトをとるために前もっ
て三弗化窒素（ＮＦ２）のプラズマエツチングにより第
１の配線層２の表面のアルミナ栃除去した後、珪素層も
しくは珪素化合物層７として、−コンタクト孔を覆って
基板表面が平坦になるように、四水素化珪素（Ｓ ｉ
Ｈ４）のプラズマＣＶＤにより多結晶珪素層を成長する
。In FIG. 1 (bl), in order to make a contact, the alumina on the surface of the first wiring layer 2 is removed by nitrogen trifluoride (NF2) plasma etching in advance, and then a silicon layer or a silicon compound layer 7 is formed as a -contact. Silicon tetrahydride (S i
A polycrystalline silicon layer is grown by plasma CVD (H4).
（スパッタにより多結晶珪素層を成長する場合も、前も
ってスバ、ツタエツチングを行って第１の配線層２の表
面のアルミナを除去する。）成長条件は周波数１３．５
６Ｍ）ｌｚのＲＦ電力を３０會加え、Ｉ Ｔｏｒｒに排
気して５ｉｔ（ｎを１０ｃｃ／ｍｉｎ流して、１００〜
２００℃で約１μｍ成長する。(Even when growing a polycrystalline silicon layer by sputtering, alumina on the surface of the first wiring layer 2 is removed by performing sputter and vine etching in advance.) The growth conditions are a frequency of 13.5
Apply RF power of 6M)lz for 30 hours, exhaust to I Torr, and flow 5it(n at 10cc/min, 100~
It grows to about 1 μm at 200°C.
この工程は多結晶珪素層の代わりに、珪素化合物として
タングステン・シリサイド（ＷＳｉ２）層を成長しても
よい。In this step, a tungsten silicide (WSi2) layer may be grown as a silicon compound instead of the polycrystalline silicon layer.
この成長は減圧ＣＶＤにより、ＱＪＴｏｒｒに排気して
ＷＦ６ とＳ ｉ Ｈｇをに６０に混合したガスを用い
て、３００〜３５０℃で行う。This growth is performed by low pressure CVD at 300 to 350° C. using a gas in which WF6 and Si Hg are mixed at 60% by evacuation to QJTorr.
第１図（Ｃ）において、珪素層もしくは珪素化合物層７
の開口部内の部分を残して、絶縁層３上の部分を除去す
る。In FIG. 1(C), a silicon layer or a silicon compound layer 7
The portion on the insulating layer 3 is removed, leaving the portion inside the opening.
この除去は周波数１３．５６ＭＨｚのＲＦ電力を２００
會加え、０．３Ｔｏｒｒに排気して四弗化炭素（ＣＦ４
）と酸素（０□）を１０：１に混合したガスを用いてプ
ラズマ・エツチングすることにより行う。This removal reduces the RF power at a frequency of 13.56 MHz by 200 MHz.
Add carbon tetrafluoride (CF4) and exhaust to 0.3 Torr.
) and oxygen (0□) at a ratio of 10:1.
この場合Ｓｉまたは−ＳｉｘとＰＳＧとのエツチングの
選択比は十分とることができるが、ＰＳＧ３と珪素層も
しくは珪素化合物Ｎ７の間にレジストを介在させてリフ
トオフにより、ＰＳＧａ上の珪素層もしくは珪素化合物
層７を容易に除去することもできる。In this case, it is possible to obtain a sufficient etching selectivity between Si or -Six and PSG. 7 can also be easily removed.
第１図（ｄ＋において、開口部に残った珪素層もしくは
珪素化合物層７を一層８に変換する。In FIG. 1 (d+), the silicon layer or silicon compound layer 7 remaining in the opening is converted into a single layer 8.
この変換は０．２Ｔｏｒｒに排気して、ＷＦｂと希釈ガ
スとして窒素（Ｎ２）を１＝８０に混合したガスを用い
て行う。This conversion is performed by evacuation to 0.2 Torr and using a gas mixture of WFb and nitrogen (N2) as a diluent gas at a ratio of 1=80.
希釈ガスとしてＮ２の他にヘリウム（ｌｉｅ）、アルゴ
ン（＾ｒ）等を用いてもよい。In addition to N2, helium (lie), argon (^r), or the like may be used as the diluent gas.
つぎに変換された一層８を覆って第２の配線層４として
厚さ約１μｍのＡＩを被着する。Next, AI having a thickness of about 1 μm is deposited as a second wiring layer 4 covering the converted layer 8.
以上詳細に説明したように本発明によれば、半導体装置
の微細化に伴い、第１の配線層上に被着された層間絶縁
層に形成されたコンタクト孔の形状が深さに比し開口幅
が小さくなっても、インタフｉ・孔内に低抵抗のＷを埋
め込−むことにより、配線抵抗を増大することなく、か
つ第２の配線層被着に際しての段差被覆が良く半導体装
置の信頼性を向」二することができる。As explained in detail above, according to the present invention, as semiconductor devices become smaller, the shape of the contact hole formed in the interlayer insulating layer deposited on the first wiring layer becomes smaller than the depth. Even if the width becomes smaller, by embedding low-resistance W in the interface i/hole, the wiring resistance will not increase and the step coverage when depositing the second wiring layer will be good, making it possible to improve the performance of the semiconductor device. Reliability can be improved.
第１図Ｃａ＋乃至（ｄ＋は本発明による眉間接続の状態
を工程順に示す断面図、
第２図［ａ）、 ［ｂｌは従来例により、第１の配線層
上の絶縁層に開口されたコンタクトホールに第２の配線
層を被着した状態を示す断面図、
第３図は他の従来例による眉間接続の状態を示す断面図
である。
図において、
１は半導体基板、 ２は第１の配線層、３は配線
層、 ４は第２の配線層、５はＭｏ５ｉ２層
、 ６は一層、７はＳｉまたはＳｉ誓２層、
８は一層を示す。 −Fig. 1 Ca+ to (d+ are cross-sectional views showing the state of the glabella connection according to the present invention in the order of steps; Fig. 2 [a) and [bl are contacts opened in the insulating layer on the first wiring layer according to the conventional example. FIG. 3 is a cross-sectional view showing a state in which the second wiring layer is applied to the hole, and FIG. 3 is a cross-sectional view showing a state of glabella connection according to another conventional example. In the figure, 1 is a semiconductor substrate, 2 is a first wiring layer, 3 is a wiring layer, 4 is a second wiring layer, 5 is a Mo5i layer, 6 is a single layer, 7 is a Si or Si layer,
8 indicates one layer. −
Claims (1)
該絶縁層に開口部を設けて該第１の配線層を表出する工
程と、該開口部を覆って珪素層もしくは珪素化合物層を
被着する工程と、該珪素層もしくは珪素化合物層の開口
部内の部分を残して該絶縁層上の部分を除去する工程と
、該開口部内に残った該珪素層もしくは珪素化合物層を
タングステン層に変換し、該タングステン層を覆って第
２の配線層を被着する工程を有することを特徴とする半
導体装置の製造方法。depositing an insulating layer on the first wiring layer deposited on the substrate;
a step of providing an opening in the insulating layer to expose the first wiring layer; a step of covering the opening with a silicon layer or a silicon compound layer; and an opening in the silicon layer or silicon compound layer. a step of removing a portion on the insulating layer while leaving a portion inside the opening, converting the silicon layer or silicon compound layer remaining in the opening into a tungsten layer, and forming a second wiring layer covering the tungsten layer; 1. A method of manufacturing a semiconductor device, comprising a step of adhering.
Priority Applications (5)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP59135444A JPS6122651A (en) | 1984-06-29 | 1984-06-29 | Manufacture of semiconductor device |
| DE8585303878T DE3580192D1 (en) | 1984-06-02 | 1985-05-31 | METHOD FOR PRODUCING A CONTACT FOR A SEMICONDUCTOR ARRANGEMENT. |
| EP85303878A EP0164976B1 (en) | 1984-06-02 | 1985-05-31 | Method of producing a contact for a semiconductor device |
| KR1019850003833A KR900008387B1 (en) | 1984-06-02 | 1985-06-01 | Method of producing a contact for a semiconductor device |
| US07/166,832 US4906593A (en) | 1984-06-02 | 1988-03-04 | Method of producing a contact plug |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP59135444A JPS6122651A (en) | 1984-06-29 | 1984-06-29 | Manufacture of semiconductor device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS6122651A true JPS6122651A (en) | 1986-01-31 |
| JPH0260058B2 JPH0260058B2 (en) | 1990-12-14 |
Family
ID=15151860
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP59135444A Granted JPS6122651A (en) | 1984-06-02 | 1984-06-29 | Manufacture of semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS6122651A (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| EP0328970A2 (en) * | 1988-02-18 | 1989-08-23 | International Business Machines Corporation | Method of depositing tungsten on silicon in a non-self-limiting CVD process and semi-conductor device manufactured thereby |
| JPH04152631A (en) * | 1990-10-17 | 1992-05-26 | Mitsubishi Electric Corp | Semiconductor device |
-
1984
- 1984-06-29 JP JP59135444A patent/JPS6122651A/en active Granted
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| EP0328970A2 (en) * | 1988-02-18 | 1989-08-23 | International Business Machines Corporation | Method of depositing tungsten on silicon in a non-self-limiting CVD process and semi-conductor device manufactured thereby |
| JPH04152631A (en) * | 1990-10-17 | 1992-05-26 | Mitsubishi Electric Corp | Semiconductor device |
Also Published As
| Publication number | Publication date |
|---|---|
| JPH0260058B2 (en) | 1990-12-14 |
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