JPS61153895A - Semiconductor memory device - Google Patents

Abstract

PURPOSE:To change over and use the same device to a low power consumption type or high speed type in accordance with the purpose by changing over and setting a control signal with a row address buffer and a column address buffer. CONSTITUTION:When an electric power source is turned on, a change-over signal VD is inputted from an external circuit to a selecting circuit 16, and by the output, a row address buffer 14 and a column address buffer 15 execute the usual action with a constant level signal. Next, for initialization when the level of the signal VD is changed to a higher level, a chip enable signal CE' is outputted through the selecting circuit 16 and supplied to the buffers 14 and 15. Consequently, in accordance with the signal VD, changing-over and setting can be executed concerning whether a memory array 11 is controlled by the signal CE' or the array is always controlled by a constant signal.

Description

[Detailed Description of the Invention] [Technical Field of the Invention] This invention relates to semiconductor memory IT, and in particular,
Regarding static RAM.

[Technical background of the invention and its problems]

As is well known, there are two types of static RAM: the 0MO8 type using CMOS and the NMO8 type using NMO8.

The 0MO8 type has a low power consumption RAM with battery backup that controls the input stage consisting of a row address buffer and a column address buffer using the chip select signal n, and a high-speed RAM that controls the input stage.
It is classified as These address access times (access time after address signal is input) TACC
The relationship between and chip select access time (access time after the chip enable signal is supplied) 'l'co is 'l'Acc≦TCO for the former and 'l'Acc≦TCO for the latter.

'rice > TCO. Furthermore, NMO8m is also classified into two types: RAM that has a low power consumption standby state and RAM that does not have such a state. The relationship between these access times is 'i'Acc≦I'c for the former.

The latter 'i'Acc)'pc.

It is.

As described above, conventional static RAMs are divided into low power consumption types and high speed types, which has the disadvantage that the optimum one must be selected depending on the application.

[Purpose of the invention]

This invention was made based on the above circumstances, and its purpose is to provide an extremely advantageous semiconductor device that allows the same device to be used by switching to a low power consumption type or a high speed type depending on the purpose. It aims to provide a storage device.

[Summary of the invention]

According to the present invention, for example, it is possible to switch and set the row address buffer and column address buffer to be controlled by a chip enable signal or constantly controlled by a constant signal using a signal supplied from the outside.

[Embodiments of the invention]

Hereinafter, one embodiment of the present invention will be described with reference to the drawings.

In FIG. 1, a memory array 11 includes a row address decoder 12. A column address decoder 13 is connected to S, and these row address decoders 12 and column address decoders 13 hold the input row address signal and column address signal, respectively, and also hold the input address signal 2 and the inverted address signal. A row address buffer 14 and a column address buffer 15 that output address signals are connected.

Further, the row address decoder 122 and the column address decoder 13 each receive a chip enable signal "σ".
The operation is controlled by 1.

On the other hand, the selection circuit 16 is, for example, a NAND circuit 1F.

18, a flip-flop circuit 19.2, an inverter circuit 20, and an AND circuit 21. It is composed of a resistor 22. That is, the voltage #VDD is supplied to one terminal (reset input terminal) of the NAND circuit 18 via the resistor 22,
A switching signal VD is supplied to one input end (set input end) of the NAND circuit 11 from an external circuit (not shown) via an inverter circuit 20. Further, the output signal of the NAND circuit 17 is supplied together with the chip enable signal CE to the input terminal of an AND circuit 21, and the output signal of this AND circuit 21 is supplied to the row address buffer 14. The data is supplied to the column address buffer 15.

The operation in the above configuration will be explained in detail. FIG. 2 shows an example of the switching signal vn, and shows the sequence from power-on. When the power is turned on, the external circuit outputs v? A switching signal VD of level t is output. This signal is supplied to the NAND circuit 11 via the inverter circuit 20, but one output level of the inverter circuit 20 is not low enough to invert the output signal of the AND circuit 17. When the power is turned on, the power supply VDD is supplied to the input terminal of the NAND circuit 18, so
The output level of this NAND circuit 18 is set to high level, and the output signal of the NAND circuit 17 to which this signal is supplied is set to low level. Therefore, the input conditions of the AND circuit 21 are not satisfied, and the row address buffer 1
4. The column address buffer 1.5 is normally operated by a constant level signal.

Further, after the time T has elapsed, when the switching signal VD from the external circuit is changed from VTE1 to a higher level VTE2 to perform initialization, the NAND circuit 17 changes the output of the inverter circuit 20. The output signal is inverted to high level by the signal. Therefore, the input conditions of the AND circuit 21 are satisfied, and the operations of the row address buffer y14s and the column address buffer 15 are controlled according to the chip enable signal n supplied via the AND circuit 21.

According to the above embodiment, the row address buffer 14 and the column address buffer I5 are connected to the chip enable signal "σ1" according to the switching signal VD supplied to the selection circuit 16.
It is possible to switch between two modes: control with a fixed signal or constant control with a constant signal.

Therefore, one semiconductor memory device can be used by switching to a low power consumption type or a high speed type.

Similarly, in the above-mentioned embodiment, the selection circuit 16 is composed of a flip-flop circuit 192, a NAND circuit 2°1, etc., but the present invention is not limited to this.

Further, although the switching signal VD is generated by an external circuit, the present invention is not limited to this, and the switching signal VD may be provided within the same chip.

It goes without saying that various other modifications can be made without departing from the gist of the invention.

〔Effect of the invention〕

As detailed above, according to the present invention, the same device can be switched to a low power consumption type or a high speed type depending on the purpose.
It is possible to provide a very advantageous semiconductor memory device that can be used in the summer.

[Brief explanation of the drawing]

The drawings show an embodiment of a semiconductor memory device according to the present invention, and FIG. 1 is a circuit configuration diagram, and FIG. 2 is a waveform diagram shown for explaining the operation. 11...Memory array, 12...Row address decoder, 13...Column address buffer, 14...
Row address buffer, 15... Column address buffer, 16... Selection circuit, Deto... Chip enable signal, VD... Switching signal.

Claims (1)

[Claims] A memory array, a row address decoder and a column address decoder connected to this memory array, a row address buffer and a column address buffer connected to these row address decoders and column address decoders, respectively, and a chip enable signal according to a switching signal. Alternatively, a semiconductor memory device comprising a selection circuit that selectively supplies an operation signal of a constant level to a row address buffer and a column address buffer.