JPS61153374U - - Google Patents
Info
- Publication number
- JPS61153374U JPS61153374U JP1985036431U JP3643185U JPS61153374U JP S61153374 U JPS61153374 U JP S61153374U JP 1985036431 U JP1985036431 U JP 1985036431U JP 3643185 U JP3643185 U JP 3643185U JP S61153374 U JPS61153374 U JP S61153374U
- Authority
- JP
- Japan
- Prior art keywords
- flip
- mounting
- chip semiconductor
- electrode
- substrate
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 claims description 7
- 239000000758 substrate Substances 0.000 claims description 7
- 239000004020 conductor Substances 0.000 claims description 2
- 229910000679 solder Inorganic materials 0.000 claims description 2
- 239000000463 material Substances 0.000 claims 3
- 239000000919 ceramic Substances 0.000 claims 1
- 239000011347 resin Substances 0.000 claims 1
- 229920005989 resin Polymers 0.000 claims 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
Landscapes
- Electric Connection Of Electric Components To Printed Circuits (AREA)
- Wire Bonding (AREA)
Description
第２図は従来の混成集積回路装置を示す要部断
面図、第１図はこの考案の一実施例を示す混成集
積回路装置の要部断面図である。
図中、１は絶縁基板、２はフリツプチツプ半導
体、３はフリツプチツプの突起電極、４は取付け
用電極、５は接続用導体パターン、６ははんだで
ある。なお各図中同一符号は同一又は相当部分を
示す。
FIG. 2 is a sectional view of a main part of a conventional hybrid integrated circuit device, and FIG. 1 is a sectional view of a main part of a hybrid integrated circuit device showing an embodiment of this invention. In the figure, 1 is an insulating substrate, 2 is a flip chip semiconductor, 3 is a protruding electrode of the flip chip, 4 is an attachment electrode, 5 is a connecting conductor pattern, and 6 is solder. Note that the same reference numerals in each figure indicate the same or equivalent parts.
Claims (1)
板を用い、その絶縁基板上に、一側面に突起電極
を有するフリツプチツプ半導体を搭載した混成集
積回路装置において、前記フリツプチツプ半導体
に接続する導体パターン及びこのフリツプチツプ
半導体の突起電極の取付け部分に開孔箇所を有す
る孔設基材と、この孔設基材と同一面積で、且つ
前記フリツプチツプ半導体の取付け用電極及びこ
の電極につながる導体パターンを有する基材とを
積層して前記絶縁基板を形成するとともに、この
基板上にフリツプチツプ半導体を取付け、かつ、
この半導体の突起電極部分と前記取付け用電極間
をはんだを用いて接続して形成させたことを特徴
とする混成集積回路装置。 In a hybrid integrated circuit device using an insulating substrate such as a ceramic substrate or a resin laminated substrate, and mounting a flip-chip semiconductor having a protruding electrode on one side on the insulating substrate, a conductor pattern connected to the flip-chip semiconductor and the flip-chip semiconductor are provided. A perforated base material having an opening at the mounting portion of the protruding electrode, and a base material having the same area as the perforated base material and having a conductive pattern connected to the flip-chip semiconductor mounting electrode and this electrode. forming the insulating substrate, mounting a flip-chip semiconductor on the substrate, and
A hybrid integrated circuit device characterized in that the protruding electrode portion of the semiconductor and the mounting electrode are connected using solder.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1985036431U JPS61153374U (en) | 1985-03-14 | 1985-03-14 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1985036431U JPS61153374U (en) | 1985-03-14 | 1985-03-14 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS61153374U true JPS61153374U (en) | 1986-09-22 |
Family
ID=30541603
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP1985036431U Pending JPS61153374U (en) | 1985-03-14 | 1985-03-14 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS61153374U (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH0272642A (en) * | 1988-09-07 | 1990-03-12 | Nec Corp | Structure and method for connecting substrates |
-
1985
- 1985-03-14 JP JP1985036431U patent/JPS61153374U/ja active Pending
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH0272642A (en) * | 1988-09-07 | 1990-03-12 | Nec Corp | Structure and method for connecting substrates |