JPS61136244A - Wiring process of semiconductor device - Google Patents

Abstract

PURPOSE:To perform the lack-filling process of a via hole and flattening process of layer simultaneously by a method wherein, in order to form the second and after second wiring layers, the layer is firstly formed into the half of specified thickness and then only the wiring material at the upper part of interlayer film step difference is removed by etching process to deposit the wiring material repeatedly. CONSTITUTION:An interlayer film 11 is provided on the first wiring pattern 10. A via hole 12 is opened in the interlayer film 11 to form the second wiring layer 13 with around half of the final thickness required for wiring pattern by evaporation, sputtering etc. coating the surface with resist 14 for flattening process. After removing the resist 14 down to a dotted line (a) by dryetching process utilizing a plasma asher, RIE equipment etc., only the wiring material at the upper part of interlayer film step difference is removed by dry or wet etching process to remove any residual resist by plasma ashing process etc. Finally wiring material 15 may be deposited secondly for specified patterning 15' by photoetching process.

Description

[Detailed description of the invention] 11th page J construction! The present invention relates to a multilayer wiring method for semiconductor devices, and more particularly to a multilayer wiring technology for semiconductor devices that can simultaneously solve the problem of filling via holes or contact holes and unevenness due to their presence.

In recent years, the design and manufacturing technology for semiconductor devices such as IC5LSI has made remarkable progress, with the trend towards miniaturization and higher integration of elements being particularly noticeable. By the way, in order to increase the degree of integration of semiconductor devices, it is necessary to reduce the dimensions of the elements, but as this progresses, the wiring patterns for connecting these elements on the chip become more complex, and the wiring patterns cover the entire surface of the chip. Since a large portion of the space will be occupied,
This greatly limits high-density packaging. On the other hand, although the above problem can be solved to some extent by reducing the width of the wiring pattern, there is a limit to the reduction of the width of the pattern when considering the characteristics required of the wiring pattern such as current capacity and resistance of the wiring.

Under these circumstances, multilayer wiring technology has attracted attention and is widely used as an extremely effective technology for solving the above-mentioned wiring problems associated with the increase in R1 density of semiconductor devices.

This multilayer wiring technology multilayers the wiring of semiconductor devices such as ICs, provides a large degree of freedom in coupling between each element arranged on a chip, etc., and is extremely important in forming high-density devices. It is a technology that already has three AI layers (
For example, high-density logic LSIs (gate arrays, etc.) containing two A1 layers, polysilicon gates with A1 layers multiplexed into two or three layers, etc.) have been realized and put into practical use. has been done.

The advantage of this multilayer wiring technology is that it allows various elements to be laid out without having to create space for wiring on the chip, which not only improves the degree of integration and density, but also reduces the size of the chip. It is also possible to Furthermore, the degree of freedom in wiring increases, making it easier to design turns, and providing more leeway in setting the electrical characteristics of the wiring.

However, even with this multilayer interconnection technology, the process is complicated and the surface has large irregularities, so a new denomination failure mode that is not directly related to the semiconductor physical properties occurs, which is a problem that needs to be improved. ing. Among these failure modes, the most serious is, for example, the occurrence of wiring opens or shorts on the surface, and the multilayer wiring process consists of multiple thin film deposition processes.
Inconsistency in stepper noise in contact holes or via holes for making contact between the substrate and the first wiring layer, or between the first wiring layer and the second wiring layer, is a cause of failure modes.

Therefore, in semiconductor devices having a multilayer wiring structure, flattening the interlayer insulating film is necessary to prevent failure modes caused by the multilayer wiring and to obtain semiconductor devices with high reliability and high yield. is important. If this flattening is insufficient, there is a very high possibility that the above-mentioned wiring will break at the stepped portion, and even if it is not broken, there is a very high possibility that it will melt due to current concentration during subsequent use. big. For example, especially in areas where there are contact holes, via holes, etc. as described above, there is a high risk that the wiring will break due to steep steps.

Currently, various methods are used to planarize the interlayer insulating film, such as (i) etch-back method, (ii) lift-off method, (iii) silica film coating method (polyimide coating method), and (iv) bias sputtering method. Although this method is being studied, there are large variations in the process, which is the main cause of lowering the manufacturing yield of devices such as LSIs.

The various problems in multilayer wiring technology mentioned above are explained in attached 2nd page.
This will be described in more detail with reference to the diagram. First, a substrate (for example, S
i) A field oxide film (SiO2) 2 is formed on the substrate 1, and then a contact hole 3 is formed by etching (see FIG. 2(a)). Next, a first wiring layer 4 (for example, A1) is formed and etched into a predetermined wiring pattern (see FIG. 2 (5)), and then a phosphor glass (PSG) layer is formed.
An interlayer insulating film 5 is formed, and via holes 6 are similarly provided (see FIG. 2(C)). Next, a second A1 wiring layer 7 is formed and similarly etched into a predetermined wiring pattern (see Figure 2G)), and a second insulating layer 8 is provided to complete the wiring pattern (see Figure 2G). (e)〉.

In the completed multilayer wiring diagram shown in FIG. 2(e), the field oxide film 2, interlayer insulating film 5, etc. generally require a thickness of about 1 μm considering dielectric strength voltage and wiring capacitance.
Since the contact hole 3 and via hole 6 are provided in these films, the step difference due to this is also about 1 μm.

As a result, a disconnection A in the contact hole portion, a disconnection B in the via hole portion, and a disconnection C due to insufficient planarization of the interlayer film 5 are formed.

Problems to be Solved by the Invention Thus, planarization of interlayer insulating films and step coverage of stepped portions such as contact hole vias and holes are as follows:
In manufacturing a semiconductor device having a multilayer wiring structure, this is an important step in order to eliminate failure modes based on the formation of multilayer wiring.

Nevertheless, each of the above-mentioned methods proposed in the past has its own drawbacks, and no method has been established to fundamentally solve the above two problems. For example, in the etch-back method, it is necessary to set special conditions so that two layers with different properties, a resist film and an insulating film (for example, PSG), can be etched at the same etching speed. Setting conditions is extremely difficult. In addition, even in the lift-off method, a gap is formed between the glabella film and the AI wiring layer, and this gap remains as a groove even after the formation of the second interlayer film, making it difficult to ensure sufficient flattening. .

Therefore, it is necessary to develop a method for forming multilayer wiring that does not exhibit the various drawbacks of the conventional methods described above, eliminates the failure mode of semiconductor devices based on the shortcomings of the multilayer wiring technology itself, and can greatly improve manufacturing yield. It was desperately needed. It is also an object of the present invention to develop a method for forming such a wiring structure.

Means for Solving the Problems The inventors of the present invention have conducted various studies to solve the above-mentioned problems in multilayer wiring technology, particularly the problems of step coverage and flattening of interlayer films, etc. As a result, the present inventors have found that During formation, the layer is first formed to a thickness of about half of the predetermined thickness, only the wiring material layer above the glabellar membrane step is removed by etching, and the wiring material is deposited again.
It has been found that filling of via holes and contact holes and planarization of layers can be achieved at the same time. The present invention was completed based on such new findings.

That is, in the semiconductor device wiring method of the present invention, the steps of forming a first wiring pattern, forming an interlayer film and via holes or contact holes, and then forming a second wiring pattern are repeated to form a semiconductor device. A method for forming a multilayer wiring technology, in which when forming a wiring pattern for the second layer and subsequent layers, a wiring material is first deposited to a thickness equivalent to about half of a predetermined thickness of the wiring pattern, and then a resist is deposited. Apply the material so that the upper surface is flat, remove the resist by dry etching up to the upper surface of the wiring material on the step part of the interlayer film, remove only the wiring material on the step part of the interlayer film by etching, and remove the resist. The method is further characterized in that a wiring material is deposited to a predetermined thickness and then etched into a predetermined pattern.

The interlayer film material that can be advantageously used in the method for forming multilayer wiring of a semiconductor device according to the present invention is 5102.5r3N...PG.
It can be appropriately selected from various known materials such as S, resins such as polyimide, and Al2O*, depending on the base material, wiring material, etc. Methods for forming this interlayer film include sputtering method (SiO□, S+3N-, etc.), chemical vapor deposition method (
CVD method: S10□, PSG, etc.), coating method (Si30.
, polyimide, etc.), anodic oxidation method (A1203), and various other methods can be used.

In addition, the main material for the metal film for multilayer wiring is AI.
Mo, W, TiPt, or their alloys are used in other special device structures and packaging formats (e.g. beam lead, flip chip format).

Pd5Pt, Au, etc. can also be used. Formation of this metal film can also be carried out by sputtering, vacuum evaporation, CVD, physical vapor deposition (PVD), and other evaporation methods, which are appropriately selected and used depending on the type of material.

In the method of the present invention, photoetching is used to form contact holes and via holes and to form predetermined patterns of wiring material. Various known materials can be used as the resist at this time, including polycinnamic acid resins such as TPR, O3 manufactured by Tokyo Ohka Co., Ltd.
R series, KPR series manufactured by Kodak, etc.; combination of cis-isoprene and allyldiazide crosslinking agent, such as Tokyo Ohkabu OMR, NMR series, KM manufactured by Kodak
ER series, etc.: Ester of novolabuku type phenolic resin and 0-quinone azide, such as 5hipley's A
Examples include photoresists such as Z series and Tokyo Ohkasha's 0FPR series. When selecting this resist, it is necessary to take into consideration the later etching/etching operation of the metal film.
? , 78, A 21350 J.

By using OMR83 or the like, dry etching (reactive gas plasma etching) can be particularly advantageously applied to the removal of metal films.

Of course, it is also possible to use other electron beam resists such as polymethyl methacrylate and epoxidized polybutadiene.

Formation of this resist film can be carried out by a series of operations consisting of cleaning, coating, and prebeta, and removal of this resist film is performed by chemical reaction between atomic oxygen generated in 02 plasma and polymer resin. It is advantageous to use a plasma ashing method or a reactive ion etching method (RIE method), which utilizes the effect of reducing the molecular weight, decomposing the low-molecular resin into CO2 and H2O through oxidation, and vaporizing the resin. In addition, when using a parallel plate electrode type plasma etching device to remove the next metal film, the resist is also removed using the same device, so that the resist removal and the metal pattern removal can be performed continuously. is possible.

To remove the metal film, in addition to general wet etching using an etching solution mainly composed of phosphoric acid, nitric acid, acetic acid, etc., sputter etching, ion beam etching, etc. can be used, and plasma etching equipment can also be used. Of course, it is also possible to use so-called reactive ion etching, which is carried out at a reaction gas pressure of about 10-3 to 10'-' Torr.

In this method, when the metal film material is A1, the reactive gas is cc+4+ (0□, C1□, C2H,)
, B[:I3 + (02), CC+□F2, etc. are used, A1 is removed as volatile AlCl3, and
For WSPt, Ti, etc., CF is used and removed as volatile products MoFs, WFs, ptFa, TiF, etc., and for T1, Cr, CCIs is
CI2 is used for Cr5Au, etc., and C2 is used for Au.
C12F, will be used and removed as a volatile halide as well.

At this stage, the resist remaining on the wiring pattern is removed by the aforementioned plasma ashing, general wet etching, or a suitable organic solvent.

After removing the resist in this way, wiring material is deposited again to a thickness necessary to ensure a predetermined thickness of the wiring pattern, and a predetermined wiring pattern is similarly formed by photoetching.

To explain the method of the present invention in more detail with reference to the attached FIG. 1, first, as shown in FIG. 1(a), a substrate (for example, S1
A field oxide film etc. is formed on the chip (chip), a contact hole is formed in this (not shown for simplicity), a first wiring pattern 10 is formed, and a glabellar film 11 is formed on it.
(for example, PSG). In the operations up to this point, in order to form a flat first wiring pattern, a contact ball is formed on the field oxide film, etc., a wiring material layer is formed, a resist is applied thereon, and the resist is Remove up to the surface of the wiring material layer by plasma ashing or the like, leaving only the resist in the contact hole portion, and then remove the wiring material layer by etching,
The resist in the hole portion is removed, a wiring material is formed again by vapor deposition, etc., and the first wiring pattern is formed by photo-etching, so that the surface of the first wiring pattern is The flattening problem can be solved.

Next, as shown in FIG. 1, etc., via holes 12 are formed in the interlayer film 11 by photoetching, and a second wiring layer is deposited on top of the via hole 12 by vapor deposition, sputtering, etc. to form the final wiring pattern required. Approximately half the thickness (approximately 0.5 to 0.
7 μm) (see FIG. 1(C)). Next, as shown in FIG. 1(d), a resist 14 (or polyimide, etc.) is applied onto the wiring material layer 13 so that the upper surface thereof is flat. At this time, in order to apply the resist layer 14 etc. so that the upper surface is flat, it is advantageous to take measures such as increasing the film thickness or decreasing the viscosity of the resist solution to increase fluidity. . Furthermore, the resist layer thus formed flat is dried using a plasma asher-1RrE device or the like up to the dotted line a in FIG. 1(d).
After removal by etching (see Figure 1(e)), only the wiring material above the interlayer film step is removed by wet etching or dry etching (see Figure 1(f)), and then the remaining resist, polyimide, etc. Remove with organic solvent, plasma ashing, etc. (see Figure 1 (mother))
. Finally, as shown in Figure 1 (color), a second wiring material 15 is deposited, a predetermined pattern (15") is formed by photo-etching, and a multi-layer layer as shown in Figure 1 (color) is formed. Complete the wiring structure.

In the above explanation, a multilayer wiring structure including two layers of wiring patterns has been described, but by repeating the operations shown in FIG. It is possible.

In semiconductor devices such as semiconductor devices, the number of via holes existing in the interlayer film is enormous, and all of them are electrically conductive and have sufficiently low contact resistance. must be maintained. In such a case,
When wiring is performed using a conventionally known method such as the lift-off method, there is a high incidence of wire breakage in vias and hole contact holes in the wiring pattern, or in areas where flattening is insufficient, and fusing due to current concentration during use. Therefore, devices with a large number of holes, such as LSIs, are expected to have a high incidence of failure modes due to wiring, resulting in a significant decrease in reliability and manufacturing yield. .

However, by forming a multilayer wiring structure according to the method of the present invention, that is, by forming the wiring patterns from the second layer onward according to the steps described above,
It becomes possible to provide a semiconductor device with an almost completely satisfactory multilayer wiring structure.

According to the method of the present invention, by depositing and forming the wiring material twice, vias are first formed by the first vapor deposition and subsequent etching operations (FIGS. 1C to 1E).
It is possible to fill holes or contact holes, and by depositing the wiring material in the first and second times, it is possible to form a wiring material layer with good step coverage in the step portion. Therefore, disconnections in via holes, contact holes, interlayer film steps, etc., and melting during use do not occur.

In the method of the present invention, after the interlayer film shown in FIG. 1(a) is formed, the surface of the glabellar film is flattened by applying a method such as etch-back. Even if there are variations in the thickness, the stepped portions can be deposited with good step coverage, so by using the method in combination with the planarization according to the present invention, an even better multilayer wiring structure can be obtained.

Thus, the method of the present invention is extremely effective not only for LSIs with a significantly large number of holes as exemplified in the above explanation, but also for various semiconductor devices in general, when performing multilayer wiring in order to achieve miniaturization and high integration. It is expected that this method will suppress failure modes caused by multilayer wiring in these various semiconductor devices and bring about a significant improvement in manufacturing yield.

Further, since it can be carried out using only conventionally known techniques and by combining them, it can be said that the method of the present invention has high applicability.

Example Using a Si chip as the substrate, 5in2 as the interlayer film, AI as the wiring material, and AZ 1350 J as the resist material, the wiring material was changed according to each process as shown in Figure 1. A multilayer wiring including two layers, that is, the A1 layer, was formed. When forming the second A1 layer, the thickness of the first and second evaporated films was 0.5 μm, and the resist layer was etched using a plasma asher using 02 plasma. This was carried out using a reactive ion etching apparatus using CC1 as a reactive gas. Note that the thickness of each layer was approximately 1 μm.

In this way, the Si chip having multilayer wiring manufactured according to the method of the present invention has sufficient step coverage and flattening of interlayer films, etc., so that holes are completely filled, excellent flatness is achieved, and there is no disconnection or long wires. It was confirmed that there were almost no failure modes such as melting after operation for a long time, and that the product had a long service life and the manufacturing yield was greatly improved.

Effects of the Invention As explained in detail above, according to the multilayer wiring technology for semiconductor devices of the present invention, contact Even if there are hornopevia holes, the coverage of the stepped portions caused by these is extremely good, and therefore various defects caused by insufficient filling of the holes,
Furthermore, it is possible to almost or completely eliminate failure modes caused by multilayer wiring, such as defects caused by insufficient planarization of each layer.

Therefore, a semiconductor device having multi-station wiring obtained by the method of the present invention has extremely high reliability, excellent long life, and extremely high manufacturing yield.

Furthermore, the method of the present invention can be implemented using only conventionally well-known techniques and does not require the use of any new techniques, so it has extremely wide applicability.

[Brief explanation of drawings]

FIGS. 1(a) to (i) are schematic diagrams for explaining each step in the method of the present invention, and FIG. 2 is a diagram for explaining the conventional method for forming multilayer wiring and the drawbacks seen therein. FIG. 1 is a schematic diagram similar to FIG. (Main reference numbers) 1... Substrate, 2... Field oxide film, 3... Contact hole, 4.10... First wiring layer, 5.11... Interlayer insulating film, 6. 12... To via horn 7... Second wiring layer, 8... Second insulating layer, ■3... Second wiring layer (approximately +A thickness), 14... Resist, 15...・Second wiring layer (approximately A thickness), Patent applicant Sumitomo Electric Industries Co., Ltd. Representative Patent attorney Masahiko Arai 10...M1 wiring shoulder 11...Interlayer film 12...Here complete ( (1) (h) J 10°

Claims (1)

[Claims] (1) The process of forming a first wiring pattern, then forming an interlayer film, forming via holes or contact holes therein, and then forming a second wiring pattern is repeated to form a semiconductor device. In the method of forming a multilayer wiring structure, the step of forming the wiring pattern after the second layer forms a wiring material layer with a thickness corresponding to about 1/2 of the predetermined thickness of the wiring pattern, and then the upper surface is Apply a resist material so that it is flat, remove the resist by dry etching up to the upper surface of the wiring material on the step part of the interlayer film, remove only the wiring material on the step part of the interlayer film by etching, and remove the resist. The method for forming a multilayer wiring for a semiconductor device as described above, comprising the steps of forming the wiring material layer again to have a thickness of a predetermined wiring pattern and etching it into a predetermined pattern.