JPS61105660A - Interruption control method - Google Patents

Abstract

PURPOSE:To realize the high speed interruption control capable of reducing the volume of hardware or software, by concentrating the plural interruption addresses by interruption level and providing interruption control circuit corresponding to each level. CONSTITUTION:A CPU 6 executes an interruption routine when it identifies an address vector, during which time a factor flag of interruption address ''0'' is identified by the CPU. At this time, an address ''0'' processing termination signal 701 and READ signal 109 of factor reset timing are turned to logical 1, and as the output of AND circuit 701 is turned to logical 1, and resets the flip-flop of 106 which has been making the prohibitive condition of AND circuit 705 which issues a request to an interruption factor selection circuit 2, even if a factor flag of interruption address ''0'' may occur. When the flip-flop 106 is reset, the interruption to the factor flag of interruption address ''0'' can be again accepted by the factor identification circuit 1. Thus, by limiting the interruption control circuit to onle one for an interruption level, the interruption factor is selected among plural addresses having interruption factors. In such a way, the volume of hardware or software is reduced and the circuit is simplified and its speed will be increased.

Description

[Detailed Description of the Invention] [Industrial Application Field] The present invention relates to a computer system consisting of a processor, a storage device, or an input/output device connected to a common bus, in which an interrupt is sent to the processor from a control unit included in the input/output device, etc. The present invention relates to an interrupt control method C for exchanging information between an input/output device and a processor, and particularly relates to an interrupt control method that is performed by concentrating on different interrupt routines (addresses) at the same level.

Normally, in a computer system, the processor connects the display device and disk device via a common bus.

It is necessary to exchange information with a magnetic tape device, printer device, or panel switch. in this case.

The desire to minimize the amount of time that the processor spends processing input/output (Cl10) devices and storage devices causes the processor to continue executing the main program, stopping the main program only when requested by the I10 device. An interrupt control method of servicing Ilo is generally employed. In this method, when a device requesting a service asynchronously sends an interrupt request signal to the processor, the processor finishes the instruction being executed, allows the interrupt, returns the interrupt permission signal to the device, and then sends the main memory to the requesting device. Execution is transferred to an interrupt routine within the device, and upon completion, the instruction sequence of the main program is returned to the interrupted location. Using this method increases the overall system throughput and allows the processor to handle a variety of tasks.

However, this interrupt control method requires the addition of interrupt control hardware between the processor and the input/output device, which means that control jumps after the input/output device issues an interrupt to the processor. This is because it is necessary to supply information for specifying the destination, and it is also necessary to determine priorities for various interrupts. This addresses issues such as what to do if you want to assign a higher priority to a particular device, or what to do if you want to disable a particular interrupt while the processor allows other interrupts. In order to improve the flexibility of the system, the amount of hardware increases. What is most desirable is to realize interrupt control with a high degree of flexibility and throughput using a minimum amount of hardware.

[Conventional technology]

Conventionally, there is an interrupt controller as a control circuit that executes this type of interrupt control. As shown in FIG. 3, when one or more of the interrupt requests (for example, IRo-IRv) corresponding to the 9 interrupt levels becomes logic 1, this interrupt controller checks the priority of the request and outputs the interrupt request signal INT.
Make it logical 1. Then, when the signal is transmitted to the processor connected to the common bus via the control bus and an interrupt is generated, when two interrupts are accepted, an interrupt enable signal INTA is returned as a logic 0 from the processor.

In other words, the processor accepts the interrupt request.

Informs the interrupt controller that it is ready to process the interrupt. Upon receiving this permission signal, the interrupt controller gives the start address on the main memory of the interrupt routine corresponding to the data bus, that is, the 9th interrupt vector address, to the processor via the data bus, and the processor executes that interrupt routine. . Therefore, the input (I Ro = I R?) of the interrupt controller that executes such control exists corresponding to each interrupt level, that is, each interrupt routine having a different priority. In other words, the inputs of one interrupt controller each have a dedicated interrupt vector address with a different priority in the main memory. The input terminal of this interrupt controller is an input/output device control device (IOP) that controls the input/output operations of each input/output device.
etc., and receives interrupt requests from each 1-OP.

Since such conventional interrupt controllers receive interrupt request signals for different interrupt levels with different priorities, the interrupt routines are different even for the same level. That is, when the interrupt addresses are different, it is necessary to prioritize each address and input it to the interrupt controller even if they are at the same level. Therefore, even if the interrupt level as a system is the same, if the 9 interrupt addresses are different, the addresses are controlled as different levels, and when there are a large number of different interrupt addresses, a large number of levels are controlled. It is the same thing as there is. Therefore, if a 78-level structure is to be realized using an 8-level interrupt controller, three layers of 8-level interrupt controllers will be used as shown in FIG.

(A total of 9 controllers are cascade-connected by connecting CASBUS, resulting in 64 levels in the second layer, but the interrupt request signal INT of the controller is connected to the lowest level I/R62 and lR63.) Therefore, the second layer has 62 levels and the third layer has 16 levels.Therefore, the total is 78 levels.In such a case,
A direct vector jump is performed only in the second layer which directly receives the interrupt enable signal INTA, and software is required for the vector jump requested in the third layer.

[Problem that the invention seeks to solve]

Therefore, in such conventional interrupt control.

Interrupt control hardware or software is required for each separate interrupt level, which not only makes the design extremely troublesome, but also requires cascading of priorities among all levels after multiple interrupt request signals are output. Since the highest interrupt is determined by checking, there is a drawback that the interrupt time to the CPU becomes slow. Therefore, even if the interrupt level of the system is the same but the interrupt routine, that is, the interrupt address is different, there is a drawback that it is not possible to control the interrupt to be executed at the same level, that is, with the same probability, for the address.

The present invention classifies and collects the addresses that cause two interrupts according to the interrupt level on the system, and executes interrupt control using a priority determination method only between levels, and gives priority to interrupt control between interrupt addresses within the same interrupt level. It is an object of the present invention to provide a high-speed interrupt control method that can reduce the amount of hardware or software by providing an interrupt control circuit on a selective or non-prioritized basis.

[Means for solving problems]

The present invention reduces the number of interrupt control circuits by concentrating interrupt factors in a plurality of interrupt addresses for each interrupt level and providing an interrupt control circuit corresponding to each level. Individual interrupt factor flags are provided for the aggregated interrupt addresses, and priorities are assigned between the flags. When interrupt control is possible, interrupt processing is performed in the order of priority.

〔Example〕

Next, the present invention will be explained with reference to the drawings.

FIG. 1 is a block diagram of an interrupt control section according to the interrupt control method of the present invention. The interrupt control unit of the present invention is a device for each of the same level of interrupt levels divided into a plurality of levels, and a plurality of interrupt addresses having the same level, (a logical For example, as shown in Figure 1.

There are three interrupt addresses: interrupt address 01, interrupt address 12, and interrupt address 2, and interrupt factor flags 70, 71, and 72 corresponding to each address are input. That is, even if each interrupt factor has the same interrupt level from the perspective of the entire system, the contents of the interrupt routine are different, so different types of interrupt request flags 70, 71, . They are input as j2 from the I10 device or the like to the to and 11.12 of the 9 interrupt factor recognition circuit 1, respectively. Generally, a common bus 5 includes a plurality of central processing units (CPUs), a plurality of input/output I10 devices,
Alternatively, in a system where storage devices are commonly connected, when an I10 device interrupts a certain CPU 6, this is called an external interrupt.

Even if the external interrupts from the I10 devices have the same interrupt level, the interrupt routine executed by the CPU often differs depending on the I10 device. For example, three I10 devices with the same interrupt level or three
Since the interrupt factors from two panel switches etc. are different, these are collected and input to this control unit.For example, 70.71
．． 72 request flags are input to 10, 11, and 12 of the interrupt factor recognition circuit 1, respectively. Each circuit 10, 11.12 of the three interrupt factor recognition circuits 10, 11, 12 corresponds to each input interrupt factor flag 70, 71, 72 and interrupt address 0.1.2, that is, the flag corresponds to which address. It is a circuit that recognizes whether the
All have the same structure. For example, 2 interrupt factor recognition circuit 1
0 is when the input interrupt factor flag 70 is activated to logic 1 and requests the CPU 6 to execute the routine at interrupt address 0. 2 Interrupt address O Processing end signal 2 Interrupt address l Processing end signal 9 Interrupt address 2 Interrupt address 0 processing end signal 701 among processing end signals
is being entered. Since the CPU 6 has not yet processed the interrupt, it is at logic O, so the logic 1 of the interrupt factor flag 70 is sent to the internal flip-flop and output to the output line 100. If two or more of the factor flags 70, 71, and 72 of the interrupt address become logic 1 at the same time, the internal flip-flops will also be set to logic 1 at the same time. 10.11.1 of interrupt factor recognition circuit l
All of the outputs 100, 110° and 120 of 2 are input to the interrupt factor selection circuit 2. When there are two or more interrupt address factors at the same time, that is, when two or more of the outputs 100, 110° and 120 of the interrupt factor recognition circuit 1 are logic 1, the interrupt factor selection circuit 2 selects one of them. This is a circuit that selects

This control circuit inputs the interrupt cause flag corresponding to each address and selects the requested address flag when the interrupt level as a system is the same but the interrupt address, that is, the interrupt routine is different. The selection circuit 2 does not necessarily need to use a priority circuit to select the three output flags of the recognition circuit 1 that are input.1 The selection means can be set in various ways. One possible method is to select a request. However, in order to reduce the amount of hardware, if the output of the recognition circuit 10, which is a priority circuit based on the daisy-change method, is logic 1 and there is an interrupt request at address 0, this logic 1 can be used to The simplest method is to forcibly set the logic of the outputs of recognition circuits 11 and 12 to 0. If there is an interrupt request for any address among addresses 0, 1.2 in the interrupt factor selection circuit 2, the output 20 will be set to logic O as negative logic.
The 0 interrupt control circuit is activated and given to the interrupt control circuit 3, and when there is an interrupt request, the output 20 becomes logic 0.
When the interrupt request signal (RQI) is given to the CPU 6 via the priority circuit between levels by the interrupt controller, the CPU finishes a certain process and is ready to issue an interrupt to either address 0.1 or 2 of this level. If execution is permitted, an interrupt permission signal (INTA signal) is returned from the CPU 6 and given to the interrupt control circuit 3. Communication of handshake signals during this time is performed via the communication line 30. The interrupt control circuit 3 is given an interrupt request for either address 0, 1.2 via the interrupt cause recognition circuit 1, and is sent to signal lines 100, 110, . Alternatively, even if at least one of the lines 120 becomes logic 1, if any interrupt routine at this address 0.1.2 is currently being executed, that is.

Before that, an interrupt request signal (RQI) was sent to the CPU from the interrupt control circuit, and the interrupt was accepted, a permission signal INTA was returned, and the R-RQI signal 31 was fed back to the interrupt factor selection circuit 2. While , new interrupts are controlled to be in the waiting state.

The interrupt address generation circuit 4 has an internal address of 0°1.2.
It has an address vector for giving the start address of each of the interrupt routines on the main memory to be executed by the CPU 6 in response to the three interrupt factors of the same level, and any of the addresses 0.1.2 When the interrupt request flag is selected by the selection circuit 2 and set in three internal flip-flops, the output of each flip-flop is given to the interrupt address generation circuit via the signal line 40.

Then, at the time when the permission signal INTA is returned from the CPU 6, the IAWoP signal 41 is given from the interrupt control circuit 3.
Control is performed so that any of the requested address vectors is provided to the data bus of the common bus via the signal line 42 by triggering on the signal line 42.

In this manner, in this control device, when the cause of interrupt address 7 occurs, the corresponding bit of the corresponding address is turned on in the interrupt cause recognition circuit 1.

The fact that an interrupt factor has occurred is sent to the second interrupt factor selection circuit. The interrupt factor selection circuit accepts this interrupt if it is not currently under interrupt control. However, if there is a request from another interrupt factor recognition surface at the same time, the factor will be selected according to the selection means such as priorities set individually in each register, and if interrupt control is currently in progress, the control will end. This selection will be made later. When a factor is selected, the FF corresponding to the address belonging to the selected factor is turned on in the first interrupt factor selection circuit, and an interrupt start signal is sent to the third interrupt control circuit. The interrupt control circuit 3 is.

It is connected to 6 CPUs via 5 common buses. The interrupt control circuit 3 issues an interrupt request to the CPU.

Next, each internal circuit of the interrupt control circuit of the present invention shown in FIG. 1 will be described in detail using FIG.

The cause flag 70 of the interrupt address O becomes logic 1 in the interrupt cause recognition circuit 10, and the D type flip-flop 1 is output.
When set to 02, during that clock period the contents of the flip-flop 103 cascaded to it are still a logic 0 and the FaLse output 104 is a logic 1;
If the FaLse output 107 of flip-flop 106 is also logic 1, the output of AND circuit 108 will be logic 1 during that clock cycle. This interrupt factor recognition circuit 10
Haha, since this circuit recognizes that the cause flag 70 of the interrupt address 0 is address O, the interrupt address 0 processing end signal 701 and the READ signal 109, which is the interrupt cause reset timing, are input to the AND circuit 702.
If one of the inputs is logic O, the OR circuit 70
If the other input 101 of 3 is a logic O, the JK flip-flops 704 and 106 will be in the set state because J-1,=0. Therefore, when the next clock is inputted to the two JK flip-flops 704 and 106, the output becomes logic 1, and the output of the AND circuit 705 becomes logic 1. However, when this clock is input to the D type flip-flop 103, the PaLse output becomes logic 0.
Therefore, the request flag at the J terminal input of the JK flip-flop 7'' 704 becomes a logic 1 pulse for one cycle, and therefore the output signal of the AND circuit is also required, and even if it becomes logic 1, the logic 1 level is maintained. It becomes a pulse instead of a pulse.

As is clear, this pulse is output because the cause flag 70 corresponds to address 0, so this circuit is a circuit that recognizes the interrupt cause. Interrupt factor recognition circuit 10.11゜12 outputs 100, 110
．． 120 are both input to the interrupt factor selection circuit 2. The interrupt factor selection circuit 2 includes three JK flip-flops 21, 22, and 23, and each JK flip-flop 21, 22, and 23 has one interrupt address. 0,
Flag 100 when each of the factors in 1.2 is accepted.
, 110, and 120 cents, respectively.
There are various conditions for them to be sent as cents. For example, even if the output 100 of the recognition circuit 10 becomes logic 1 and there is a request for 1 interrupt address and O, in order to be set in the JK flip-flop, the True output A must be 0 and the FaLse output must be 1. . That is,
Under the condition that there is currently no request for address O, the output of the AND circuit 24 becomes logic 1 for the first time, and logic 1 is sent to the JK frimb flop at the next clock. That is, in the interrupt factor selection circuit 2.

The same goes for 0 interrupt address 1 or 2, which will accept this interrupt if it is not currently under interrupt control, but the AND circuit 26 corresponding to the AND circuit 24 for address 0 is The PaLse output ☆A is connected in a daisy-chain manner, and the above address O is connected to the AND circuit on the 2nd day.
FaLse output of JK flip-flop 21 in ☆
Not only A, but also the PaLse output ☆B of the JK flip-flop 22 at address 1 are connected in a daisy-chain manner. Therefore, the flag set to the JK flip-flop 22 at address 1 is set to the JK flip-flop 22 at address 0.
It can be set when the flag of the K flip-flop 21 is not set, and the flag can be set to the JK flip-flop 23 at address 2 when both the JK flip-flop 21 at address 0 and the JK flip-flop 22 at address 1 are not set. This means that it can be set to . Therefore, this interrupt factor selection circuit 2 uses the daisy chain method to prioritize the addresses 0, .
Interrupt requests are also executed with priority given in the order of 1.2. However, address 0.1.2 has the same interrupt level as the system, so it is not necessarily 3.
It is not necessary that the two flags be selected by a priority circuit, but may be selected according to the requested order. No good circuit 210
is true of three flip-flops 21.22.23
Output A.

Since B and C are input, the output signal 20 will be activated to logic 0 when any one of addresses 0.1.2 requests an interrupt, and the output signal 20 will become an internal interrupt request signal. It is given to the interrupt control circuit 3 as RQIN7. When the internal interrupt request signal RQrN7 becomes logic 0, this interrupt control circuit waits until this request is accepted according to the priority order among other levels, and after the internal interrupt request signal RQrN7 is accepted, it outputs the control bus of the common bus 5 as a side interrupt request signal Y. An interrupt is applied to the CPU connected to the common bus via the common bus.

When an interrupt is accepted by the CPU 6, the interrupt permission signal "ma 7" is returned from the CPU 6 to the interrupt control circuit 3 as a logic 0. Iru Shinsaki 31
is activated to logic 1 after a certain delay when this INTA becomes logic O, and one of the JK flip-flops
This is a signal that controls the one that is set to be reset after a while after MA1 becomes logic 0.In other words, this signal is used when the interrupt sequence for either address 0 or 1.2 ends. Therefore, when this signal line is O.

For example, since the output of the AND circuit 25 is a logic 0, the terminal of the JK flip-flop 21 is set to a logic 0 so that it can be set when J=1. Furthermore, when the output of the AND circuit 25 is logic O, at least one of the interrupt address O processing end signal 701 and the interrupt factor reset timing READ signal 109 is also logic through the signal line 101 to the JK flip-flop 704 between the t recognition circuits. If it is O, the output of the AND circuit 702 becomes logic 0, and the output of the OR circuit 703 becomes O, so that when the JK flip-flop 704 is J-1, it can be sent.

Of course, after the INTA signal becomes logic 0, the signal line 31
When becomes logic 1, Tr of JK flip-flop 21
When the ue output is 1, the output of AND circuit 25 is logic 1
Therefore, the JK flip-flop 21 is reset, but at the same time, the JK flip-flop 704 is also reset to the OR circuit 703.
will be reset by a logic 1 on the output of .

In this way, the 9 interrupt factor selection circuit 2 selects a request among addresses 0.1.2 according to the selection means such as the priority order if the interrupt is not currently under control, and if the interrupt is currently under control, the request is selected after the control ends. A selection is made.

The lJ address generation circuit 4 internally stores addresses 0°1.
2, the CPU 6
Interrupt address O setting value circuit 439, interrupt address 1 setting value circuit 44. and an interrupt address 2 set value circuit 45, and when the interrupt request flag at address 0 or 1.2 is set in any of the JK flip-flops 21, 22, or 23, the set value corresponds to that flag. AND circuits 46, 47, 48 and N.

It is applied to the CPU 6 as an interrupt vector to the data bus after the common bus through a selection circuit composed of an R circuit 49 and the like. At this time, the timing for giving one interrupt vector to the data bus is the IAWO given from the interrupt control circuit 3 at the time when the interrupt enable signal INTA is returned from the CPU 6.
This is the point in time when the P signal 41 commonly inputs logic 1 to the AND circuits 46, 47, 48, etc. In this embodiment, the address vector is 16 bits from ☆D800 to ☆DB15.

When the CPU 6 recognizes the address vector by the interrupt sequence, the CPU executes the interrupt routine. In this routine, the cause flag at interrupt address 0 is recognized by the CPU. When this is recognized, the 9-interrupt address 0 processing end signal 701 and the READ signal 109 at the interrupt factor reset timing become logic 1, and the output of the AND circuit 701 becomes logic 1, and after the 1-interrupt sequence ends, the interrupt address 0 factor is returned to logic 1. AND sends a request to the 2-interrupt factor selection circuit 2 even if a flag occurs
Reset the flip-flop 106 of the circuit 705 that created the prohibition condition. When the flip-flop 106 is reset, the cause flag at the interrupt address O allows the cause recognition circuit 1 to accept the interrupt again.

When an interrupt factor occurs in this control unit, an interrupt control sequence is performed by turning on the corresponding bit of the corresponding address, and by notifying the CPU of the interrupt address, the CPU can select the address where the interrupt factor is held. A method of recognition is being taken.

〔Effect of the invention〕

According to the present invention, there is only one interrupt control circuit for each interrupt level, and by selecting an interrupt factor among addresses that have multiple interrupt factors belonging to that interrupt level, it is possible to reduce the amount of hardware or The amount of software is reduced.

This has the effect of making the circuit faster and simpler.

[Brief explanation of drawings]

FIG. 1 is a block diagram of one embodiment of the present invention, and FIG. 2 is a more detailed block diagram of one embodiment of the present invention. FIGS. 3 and 4 are block diagrams for explaining a conventional interrupt control method. l...Interrupt factor recognition circuit, 2...Interrupt factor selection circuit, 3...Interrupt control circuit,
4...Interrupt address creation circuit. 6...Central processing unit. Figure 3 Figure 4

Claims (1)

[Claims] In a computer system in which the central processing unit, storage device, input/output control device, etc. are all connected by a common bus, different interrupt routines within the same interrupt level are grouped together corresponding to logical addresses, and An interrupt control method characterized in that the interrupt selection of the address is performed prior to the selection based on the priority order between levels.