JPS6070742A - Master slice type semiconductor device - Google Patents
Master slice type semiconductor deviceInfo
- Publication number
- JPS6070742A JPS6070742A JP17859183A JP17859183A JPS6070742A JP S6070742 A JPS6070742 A JP S6070742A JP 17859183 A JP17859183 A JP 17859183A JP 17859183 A JP17859183 A JP 17859183A JP S6070742 A JPS6070742 A JP S6070742A
- Authority
- JP
- Japan
- Prior art keywords
- input
- output circuit
- circuit area
- output
- bonding pads
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 24
- 239000000758 substrate Substances 0.000 claims description 5
- 238000000034 method Methods 0.000 abstract description 8
- 238000006073 displacement reaction Methods 0.000 abstract description 5
- 239000004020 conductor Substances 0.000 abstract 2
- 230000001681 protective effect Effects 0.000 abstract 1
- 238000003491 array Methods 0.000 description 3
- 238000004519 manufacturing process Methods 0.000 description 2
- 239000003795 chemical substances by application Substances 0.000 description 1
- 238000007796 conventional method Methods 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 239000002184 metal Substances 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
- H01L27/10—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a repetitive configuration
- H01L27/118—Masterslice integrated circuits
- H01L27/11898—Input and output buffer/driver structures
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
- H01L2224/0554—External layer
- H01L2224/0555—Shape
- H01L2224/05552—Shape in top view
- H01L2224/05554—Shape in top view being square
Landscapes
- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Design And Manufacture Of Integrated Circuits (AREA)
- Semiconductor Integrated Circuits (AREA)
Abstract
Description
【発明の詳細な説明】
〔発明の技術分野〕
本発明は、マスク・スライス型半導体装置に係わり、特
に入出力回路領域の改良をはかったマスク・スライス型
半導体装置に関する。DETAILED DESCRIPTION OF THE INVENTION [Technical Field of the Invention] The present invention relates to a mask-sliced semiconductor device, and more particularly to a mask-sliced semiconductor device with improved input/output circuit area.
マスク・スライス型半導体装置は、予め複数の素子から
なる基本セルを半導体基板上に多数作り込んでおき配線
層並びに接続孔を変更することにより所望の回路動作を
得ようとするもので、新たな機能の回路の要望に対して
比較的簡単に対処できる特徴を有している。即ち、金属
配線を形成する以前の工程により作成される半導体チッ
プは全ての椴能回路に共通であるＩ〔め、上記方式を採
用すると、開発期間の短縮及び製造コストの低減がはか
れ、多品種少量生産が可能となる。A mask-sliced semiconductor device is a device in which a large number of basic cells consisting of multiple elements are fabricated in advance on a semiconductor substrate, and the desired circuit operation is obtained by changing the wiring layers and connection holes. It has the feature that it can relatively easily meet the demands of functional circuits. In other words, since the semiconductor chip created by the process before forming metal wiring is common to all circuits, adopting the above method shortens the development period, reduces manufacturing costs, and reduces the cost of manufacturing. It becomes possible to produce a variety of products in small quantities.
マスク・スライス型半導体装置の一つとして、ゲート・
アレイの例を第１図に示す。この半導体装置は半導体チ
ップ１上が基本素子領域２とその周辺の入出力回路領域
３とに分けられている。入出力回路領域中３には、複数
の入出力端子（ボンディング・パッド）４が設置される
。As one of the mask slice type semiconductor devices, gate and
An example of an array is shown in FIG. In this semiconductor device, a semiconductor chip 1 is divided into a basic element area 2 and an input/output circuit area 3 surrounding it. A plurality of input/output terminals (bonding pads) 4 are installed in the middle input/output circuit area 3.
しかしながら、このような方式にあっては次のような問
題があった。即ち、入出力端子のピッチは、外囲器（パ
ッケージ）とのボンディングの際の制約や入出力回路を
構成する際の制約によりそれ程小さくすることができな
い。このため、特に大規模なゲート・アレイにｄ′３い
ては、内部の基本セルの数に比較して入出力端子数が不
足するような欠点があった。また、入出力回路の数が多
くなると、多数の出力回路がＯＮすることにより発生す
る電源の揺ぎや変位電流により、誤った読込みやラッチ
アップの虞れが問題となる。However, such a method has the following problems. That is, the pitch of the input/output terminals cannot be made so small due to restrictions in bonding with the envelope (package) and restrictions in configuring the input/output circuit. For this reason, especially in a large-scale gate array d'3, there is a drawback that the number of input/output terminals is insufficient compared to the number of internal basic cells. Furthermore, as the number of input/output circuits increases, there is a risk of erroneous reading and latch-up due to fluctuations in the power supply and displacement currents generated when a large number of output circuits are turned on.
（発明の目的）
本発明の目的は、内部の基本セルの数に比較して入出力
端子の数を十分多くすることができ、かつ電源の揺ぎや
変位電流の低減をはかり得、多数の入出力回路を有する
ゲート・アレイ等に適したマスク・スライス型半導体装
置を提供することにある。(Objective of the Invention) An object of the present invention is to be able to sufficiently increase the number of input/output terminals compared to the number of internal basic cells, reduce fluctuations in power supply and displacement current, and provide a large number of input/output terminals. An object of the present invention is to provide a mask slice type semiconductor device suitable for a gate array or the like having an output circuit.
本発明の母子は、半導体チップの周囲に配置される入出
力回路領域の面積増大をはかると共に、ボンディングの
妨げとならないよう入出力端子の配置位置を定めたこと
にある。The key points of the present invention are to increase the area of the input/output circuit area disposed around the semiconductor chip and to determine the positions of the input/output terminals so as not to interfere with bonding.
即ち本発明は、半導体基板に複数個の能ｖＪ素子からな
る基本セルを複数個配列した基本素子領域と、その周囲
に入出力領域が形成されてなるチップに必要に応じた配
線パターンを施しで所望の回路動作を実現するマスク・
スライス型半導体装置において、上記入出力領域を上記
基板の最外周に形成された第１の入出力回路領域と、そ
の内側に形成された第２の入出力回路領域とから構成し
、かつ第２の入出力回路領域のボンディング・パッドを
第１の入出力回路領域の隣り合う２つのボンディング・
パッド間に形成するようにしたものである。That is, the present invention provides a chip having a basic element area in which a plurality of basic cells each consisting of a plurality of functional VJ elements are arranged on a semiconductor substrate, and an input/output area formed around the basic element area, and a wiring pattern as required. Masks and masks that achieve the desired circuit operation
In the slice type semiconductor device, the input/output region is composed of a first input/output circuit region formed on the outermost periphery of the substrate, and a second input/output circuit region formed inside the first input/output circuit region, and Connect the bonding pads in the input/output circuit area to two adjacent bonding pads in the first input/output circuit area.
It is formed between pads.
本発明によれば、入出力回路をチップの最外周だけでな
くその内側にも形成しているので、従来と同ピツチであ
っても入出力端子の個数を十分多くすることができる。According to the present invention, since the input/output circuit is formed not only on the outermost periphery of the chip but also on the inside thereof, the number of input/output terminals can be sufficiently increased even if the pitch is the same as that of the conventional chip.
即ち、多ビン化が可能となる。また、外側と内側との入
出力回路に供給する電源線或いば接地線を分離すること
により多数の出力回路を外側と内側に分配することがで
き、出力回路が同時にＯＮする際の電源線の揺ぎや変位
電流を低減することが可能となる。このため、特に大規
模なグー１〜・アレイ等において極めて有効である。That is, it becomes possible to create multiple bins. In addition, by separating the power line or ground line that supplies the input/output circuits on the outside and inside, it is possible to distribute a large number of output circuits between the outside and inside, and when the output circuits are turned on simultaneously, the power line This makes it possible to reduce fluctuations and displacement currents. Therefore, it is extremely effective, especially in large-scale arrays.
第２図は本発明の一実施例に係わるグー１〜・アレイの
概略構成を示す平面模式図である。図中１０は半導体チ
ップであり、このチップ１０上の中央部には基本素子領
域２０が形成されている。基本素子領域２０の外側には
入出力回路領域（第２の入出力回路類１ｆｔ）３０が形
成され、その外側には入出力回路領域く第１の入出力回
路領域）４０が形成されている。これらの入出力回路領
域３０゜４０には、マスター工程においてｌ・ランジス
タの他に抵抗等の保護回路が形成される。なお、第２図
は配線工程を施した後の図であり、そのうち特に本発明
に関する配線だけを示している。FIG. 2 is a schematic plan view showing a schematic configuration of a goo array according to an embodiment of the present invention. In the figure, 10 is a semiconductor chip, and a basic element region 20 is formed in the center of this chip 10. An input/output circuit area (second input/output circuits 1 ft) 30 is formed outside the basic element area 20, and an input/output circuit area (first input/output circuit area) 40 is formed outside of the basic element area 20. . In these input/output circuit areas 30 and 40, protection circuits such as resistors are formed in addition to L transistors in the master process. It should be noted that FIG. 2 is a diagram after the wiring process has been performed, and shows only the wiring particularly related to the present invention.
最外周の第１の入出力回路領域４０にはトランジスタや
保護回路等を配線接続して入力回路及び出力回路等が形
成される。さらに、この入出力回路領域４０にはボンデ
ィング・パラ１へ（入出力端子）４１．電源線（Ｖｄｄ
線）４２及び接地線（ＶＳＳ線）４３が形成される。電
源線４２及び接地線４３に電位を供給するのは入出力回
路領域４０のうちの１つ或いは複数の入出力回路である
。In the first input/output circuit area 40 on the outermost periphery, input circuits, output circuits, etc. are formed by connecting transistors, protection circuits, etc. with wiring. Further, this input/output circuit area 40 has bonding terminals 41 to 1 (input/output terminals). Power line (Vdd
A ground line (VSS line) 42 and a ground line (VSS line) 43 are formed. One or more input/output circuits in the input/output circuit area 40 supply potential to the power supply line 42 and the ground line 43.
一方、内側の第２の入出力回路領域３０にもボンディン
グ・パッド３１．電源線３２及び接地線３３が形成され
る。ここで、ボンディング・パッド３１は最外周の隣り
合う２つのボンディング・パッド４１間に形成される。On the other hand, bonding pads 31 . A power line 32 and a ground line 33 are formed. Here, the bonding pad 31 is formed between two adjacent bonding pads 41 on the outermost periphery.
また、電源５１３２及び接地線３３のうちの少なくとも
一方は最外周の電源線４２若しくは接地線４３と接続さ
れず、入出力回路領域３０の１つ或いは複数個の入力回
路から電位を供給される。さらに、基本素子領域２０へ
の電位の供給は入出力回路領域３０の電源線３２及び接
地線３３よりなされる。Furthermore, at least one of the power source 5132 and the ground line 33 is not connected to the outermost power line 42 or the ground line 43, and is supplied with a potential from one or more input circuits in the input/output circuit area 30. Furthermore, potential is supplied to the basic element region 20 through a power supply line 32 and a ground line 33 of the input/output circuit region 30.
このような構成であれば、入出力回路領域を最外周のみ
に形成したものに比して入出力端子の数を大幅に増加さ
せることができる。このため、多数の入出力端子を持つ
ゲート・アレイにも十分対処することができる。また、
内側の入出力回路領域３０を入力回路だけに用いると、
電源線３２及び接地線３３の少なくとも一方が最外周の
電源線４２若しくは接地線４３と接続されていないため
、最外周の多数の出力回路が同時にＯＮする場合にも、
従来と比較して電源線３２及び接地線３３の揺ぎや変位
電流等を低減することができる。With such a configuration, the number of input/output terminals can be significantly increased compared to a configuration in which the input/output circuit area is formed only on the outermost periphery. Therefore, it can adequately handle gate arrays having a large number of input/output terminals. Also,
If the inner input/output circuit area 30 is used only for the input circuit,
Since at least one of the power line 32 and the ground line 33 is not connected to the outermost power line 42 or the ground line 43, even when a large number of outermost output circuits are turned on simultaneously,
Compared to the conventional method, fluctuations in the power supply line 32 and the grounding line 33, displacement current, etc. can be reduced.
なお、本発明は上述した実施例に限定されるものではな
い。例えば、前記各入出力回路領域のボンディング・パ
ッドの数及びピッチ等は仕様に応じて適宜窓めればよい
。さらに、グー１〜・アレイに限らず各種のマスク・ス
ライス型半導体装置に適用できるのは勿論のことである
。また、入出力回路領域は２つに限定されるものではな
く、それ以上形成することも可能である。さらに、複数
の入出力回路領域がマスター工程により入力回路専用領
域及び出力回路専用領域等に形成されている場合にも適
用可能である。その他、本発明の要旨を逸脱しない範囲
で、種々変形して実施することができる。Note that the present invention is not limited to the embodiments described above. For example, the number and pitch of bonding pads in each input/output circuit region may be adjusted as appropriate depending on specifications. Furthermore, it goes without saying that the present invention can be applied not only to arrays but also to various mask/slice type semiconductor devices. Furthermore, the number of input/output circuit areas is not limited to two, and more than two areas can be formed. Furthermore, it is also applicable to a case where a plurality of input/output circuit areas are formed as an input circuit dedicated area, an output circuit dedicated area, etc. by a master process. In addition, various modifications can be made without departing from the gist of the present invention.
第１図は従来のゲート・アレイ構造を示づ゛平面模式図
、第２図は本発明の一実施例に係わるグーｊ〜・アレイ
の概略構成を示す平面図である。
１０・・・半導体チップ、２０・・・基本素子領域、３
０・・・第２の入圧ツク回路領域、４０・・・第１の入
出力回路領域、３１．４１・・・ボンディング・パッド
（入出力端子）、３２．４２・・・電源線、３３゜４３
・・・接地線。
出願人代理人 弁理士 鈴江武彦FIG. 1 is a schematic plan view showing a conventional gate array structure, and FIG. 2 is a plan view showing a schematic configuration of a gate array according to an embodiment of the present invention. 10... Semiconductor chip, 20... Basic element area, 3
0... Second input pressure circuit area, 40... First input/output circuit area, 31.41... Bonding pad (input/output terminal), 32.42... Power line, 33゜43
...Grounding wire. Applicant's agent Patent attorney Takehiko Suzue
Claims (4)
を複数個配列した基本素子領域と、その周囲に入出力領
域が形成されてなるチップに必要に応じた配線パターン
を施して所望の回路動作を実現するマスク・スライス型
半導体装置において、前記入出力領域は前記基板の最外
周に形成された第１の入出力回路領域と、その内側に形
成された第２の入出力回路領域とからなるもので、かつ
第２の入出力回路領域のボンディング・パットは第１の
入出力回路領域の隣り合う２つのボンディング・パッド
間に形成されたものであることを特徴とするマスク・ス
ライス型半導体装置。(1) A desired circuit is created by applying wiring patterns as necessary to a chip consisting of a basic element area in which a plurality of basic cells each consisting of a plurality of active elements are arranged on a semiconductor substrate, and an input/output area formed around it. In a mask-sliced semiconductor device for realizing operation, the input/output area includes a first input/output circuit area formed on the outermost periphery of the substrate and a second input/output circuit area formed inside the first input/output circuit area. A mask-sliced semiconductor, characterized in that the bonding pad in the second input/output circuit area is formed between two adjacent bonding pads in the first input/output circuit area. Device.
構成されていることを特徴とする特許請求の範囲第１項
記載のマスク・スライス型半導体装置。(2) The mask-slice type semiconductor device according to claim 1, wherein the second input/output circuit area is composed of only input circuits.
１の入出力回路領域と第２の入出力回路領域とで接続さ
れていないことを特徴とする特許請求の範囲第１項記載
のマスク・スライス型半導体装置。(3) The mask according to claim 1, wherein at least one of the power supply line and the ground line is not connected between the first input/output circuit area and the second input/output circuit area.・Slice type semiconductor device.
１の入出力回路領域と第２の入出力回路領域とで接続さ
れておらず、かつ第２の入出力回路領域から基本素子領
域へ電位を供給することを特徴とする特許請求の範囲第
１項記載のマスク・スライス型半導体装置。(4) At least one of the power supply line or the ground line is not connected between the first input/output circuit area and the second input/output circuit area, and the second input/output circuit area is connected to the basic element area. 2. The mask slice type semiconductor device according to claim 1, wherein a potential is supplied.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP17859183A JPS6070742A (en) | 1983-09-27 | 1983-09-27 | Master slice type semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP17859183A JPS6070742A (en) | 1983-09-27 | 1983-09-27 | Master slice type semiconductor device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS6070742A true JPS6070742A (en) | 1985-04-22 |
| JPH0542823B2 JPH0542823B2 (en) | 1993-06-29 |
Family
ID=16051136
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP17859183A Granted JPS6070742A (en) | 1983-09-27 | 1983-09-27 | Master slice type semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS6070742A (en) |
Cited By (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH02180049A (en) * | 1989-01-04 | 1990-07-12 | Nec Corp | Semiconductor device |
| JPH0327529A (en) * | 1990-02-23 | 1991-02-05 | Seiko Epson Corp | Semiconductor integrated circuit device |
| US5216280A (en) * | 1989-12-02 | 1993-06-01 | Kabushiki Kaisha Toshiba | Semiconductor integrated circuit device having pads at periphery of semiconductor chip |
| EP0826243A2 (en) * | 1995-05-12 | 1998-03-04 | David Sarnoff Research Center, Inc. | Electrostatic discharge protection for an array of macro cells |
| WO2006035787A1 (en) * | 2004-09-28 | 2006-04-06 | Kabushiki Kaisha Toshiba | Semiconductor device |
| JP2021534592A (en) * | 2018-08-21 | 2021-12-09 | テキサス インスツルメンツ インコーポレイテッド | Pad-restricted configurable logical device |
-
1983
- 1983-09-27 JP JP17859183A patent/JPS6070742A/en active Granted
Cited By (9)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH02180049A (en) * | 1989-01-04 | 1990-07-12 | Nec Corp | Semiconductor device |
| US5216280A (en) * | 1989-12-02 | 1993-06-01 | Kabushiki Kaisha Toshiba | Semiconductor integrated circuit device having pads at periphery of semiconductor chip |
| JPH0327529A (en) * | 1990-02-23 | 1991-02-05 | Seiko Epson Corp | Semiconductor integrated circuit device |
| EP0826243A2 (en) * | 1995-05-12 | 1998-03-04 | David Sarnoff Research Center, Inc. | Electrostatic discharge protection for an array of macro cells |
| EP0826243A4 (en) * | 1995-05-12 | 2000-07-19 | Sarnoff Corp | Electrostatic discharge protection for an array of macro cells |
| WO2006035787A1 (en) * | 2004-09-28 | 2006-04-06 | Kabushiki Kaisha Toshiba | Semiconductor device |
| JP2006100436A (en) * | 2004-09-28 | 2006-04-13 | Toshiba Corp | Semiconductor device |
| US7550838B2 (en) | 2004-09-28 | 2009-06-23 | Kabushiki Kaisha Toshiba | Semiconductor device |
| JP2021534592A (en) * | 2018-08-21 | 2021-12-09 | テキサス インスツルメンツ インコーポレイテッド | Pad-restricted configurable logical device |
Also Published As
| Publication number | Publication date |
|---|---|
| JPH0542823B2 (en) | 1993-06-29 |
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