JPS6057225B2 - Testing method for semiconductor devices - Google Patents
Testing method for semiconductor devicesInfo
- Publication number
- JPS6057225B2 JPS6057225B2 JP5606480A JP5606480A JPS6057225B2 JP S6057225 B2 JPS6057225 B2 JP S6057225B2 JP 5606480 A JP5606480 A JP 5606480A JP 5606480 A JP5606480 A JP 5606480A JP S6057225 B2 JPS6057225 B2 JP S6057225B2
- Authority
- JP
- Japan
- Prior art keywords
- insulating film
- semiconductor device
- semiconductor
- film
- etching
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L22/00—Testing or measuring during manufacture or treatment; Reliability measurements, i.e. testing of parts without further processing to modify the parts as such; Structural arrangements therefor
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/0001—Technical content checked by a classifier
- H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
Landscapes
- Engineering & Computer Science (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Local Oxidation Of Silicon (AREA)
- Testing Or Measuring Of Semiconductors Or The Like (AREA)
Description
【発明の詳細な説明】 本発明は、半導体装置の試験方法に関するものてある。[Detailed description of the invention] The present invention relates to a method for testing a semiconductor device.
半導体基板上に絶縁被膜を形成する場合、製造欠陥とし
て絶縁被膜にピンホール、クラック等を生じ易い。例え
ば、周知のプレーナ技術によつて作られた二層配線構造
を有する半導体装置の一断面を示すと第１図のようにな
る。When an insulating film is formed on a semiconductor substrate, manufacturing defects such as pinholes and cracks are likely to occur in the insulating film. For example, FIG. 1 shows a cross section of a semiconductor device having a two-layer wiring structure manufactured using the well-known planar technology.
図において、１はトランジスタ等が形成されたシリコン
半導体基板、２ａは拡散層安定絶縁被膜、３ａは第１金
属配線層、２ｂは層間絶縁被膜、３ｂは第２金属配線層
、２ｃは表面保護絶縁被膜である。上記の構造の半導体
装置において、表面保護被膜２ｃにピンホール、クラッ
ク４ａを生じた場合、水の浸入により第２金属配線層３
ｂの腐食断線または電気的特性劣化を引き起こす原因と
なる。In the figure, 1 is a silicon semiconductor substrate on which transistors etc. are formed, 2a is a diffusion layer stable insulation coating, 3a is a first metal wiring layer, 2b is an interlayer insulation coating, 3b is a second metal wiring layer, and 2c is a surface protection insulation coating. It is a film. In the semiconductor device having the above structure, if pinholes or cracks 4a occur in the surface protection film 2c, water may infiltrate into the second metal wiring layer 3.
This may cause corrosion of wires or deterioration of electrical characteristics.
また、層間絶縁被膜２ｂにピンホール、クラック４ｂを
生じた場合、第１金属配線層３ａと第１金属配線の間で
層間短絡または不純物イオンによる電気的特性の劣化を
引き起こす原因となる。このように半導体絶縁被膜のピ
ンホール、クラックは、信頼性低下の原因となり大きな
問題となつている。従来、半導体絶縁被膜のピンホール
、クラックを検出する場合、特にピンホールは数μ以下
と極めて小さな穴であるため、通常の光学顕微鏡（分解
能１μ程度）による拡大観察では、このようなピンホー
ルを検出することは困難であつた。Further, if pinholes or cracks 4b occur in the interlayer insulating film 2b, this may cause an interlayer short circuit between the first metal wiring layer 3a and the first metal wiring or deterioration of electrical characteristics due to impurity ions. As described above, pinholes and cracks in the semiconductor insulating film cause a decrease in reliability and have become a major problem. Conventionally, when detecting pinholes and cracks in semiconductor insulating films, pinholes are extremely small holes of a few microns or less, so magnified observation using a normal optical microscope (resolution of about 1 micron) cannot detect such pinholes. It was difficult to detect.
このため高分解能を持つた走査電子顕微鏡（以下ＳＥＭ
と称す）等による極めて高倍率ての拡大観察による検出
により試験方法が行われていた。しかしながら、ＳＥＭ
等による極めて高倍率での拡大観察であるため、あらか
じめ予測出来る箇所への検出は比較的容易であるが、半
導体ウェハ上に形成した半導体絶縁被膜のあらかじめ予
測出ノ来ない箇所のピンホール、クラックを検出して試
験方法する場合は、多大な時間を要すること。並びにＳ
ＥＭ等の極めて高倍率の装置は、非常に高価である欠点
があつた。また、上記ＳＥＭを必要としない従来方法と
し夕て、特開昭５０−１０９６７８号公報に記載されて
いるように、絶縁被膜をマスクとしてエッチング尤、こ
のエッチングによる窪を願微鏡で観察するようにした方
法があつた。For this reason, a scanning electron microscope (hereinafter referred to as SEM) has a high resolution.
The test method used was detection by magnified observation at extremely high magnification. However, the SEM
It is relatively easy to detect pinholes and cracks in locations that cannot be predicted in advance in the semiconductor insulating film formed on the semiconductor wafer because the observation is performed under extremely high magnification using Detecting and testing methods require a large amount of time. and S
Extremely high magnification devices such as EM have the drawback of being very expensive. In addition, as a conventional method that does not require the above-mentioned SEM, as described in Japanese Patent Laid-Open No. 50-109678, etching is performed using an insulating film as a mask, and the depressions caused by this etching are observed using a microscope. I found a way to do it.
しかしこの従来方法では、上記窪の周縁がなだらかにな
るため、該窪を発見するのは困難てあり、結局この従来
方法ては、絶縁被膜のピンホール等の検出は困難であつ
た。本発明は以上の点に鑑み、このような欠点を除去す
べくなされたもので、金属膜上に半導体絶縁被膜を形成
した構成となる半導体装置または半導体ウェハにおいて
、半導体絶縁被膜をマスクとして所定量エッチングする
ことにより、半導体絶縁被膜の欠陥（ピンホール、クラ
ック等）の有無を金属膜の電気的特性の変化により間接
的に検出できる。半導体絶縁被膜の試験方法を提供する
ことを目的とする。以下、この発明の一実施例を第２図
の半導体装置の断面図により説明する。図において、１
はトランジスタ等が形成されたシリコン基板、２ａはシ
リコン基板上に拡散層安定化絶縁被膜として形成したシ
リコン酸化膜（ＳｉＯ２膜）、３ｂは金属膜として形成
したアルミニウム配線層、２ｃは表面保護絶縁被膜とし
て形成したリンガラス膜（以下ＰＳＧ膜と称する。）、
４はＰＳＧ膜２ｃに製造欠陥として発生したピンホール
、５はアルミニウム配線層３ｂにエッチングにより形成
された断線部てある。本実施例方法では、上記ピンホー
ル４を有する半導体装置を、周知のエッチング技術によ
リアル；ミニウムエツチング液に浸漬する。However, in this conventional method, the periphery of the depression becomes gentle, making it difficult to detect the depression.In the end, with this conventional method, it is difficult to detect pinholes in the insulating coating. In view of the above points, the present invention has been made to eliminate such drawbacks.In a semiconductor device or a semiconductor wafer having a structure in which a semiconductor insulating film is formed on a metal film, a predetermined amount of the semiconductor insulating film is used as a mask. By etching, the presence or absence of defects (pinholes, cracks, etc.) in the semiconductor insulating film can be indirectly detected based on changes in the electrical characteristics of the metal film. The purpose is to provide a test method for semiconductor insulation coatings. An embodiment of the present invention will be described below with reference to a sectional view of a semiconductor device shown in FIG. In the figure, 1
2a is a silicon oxide film (SiO2 film) formed as a diffusion layer stabilizing insulating film on the silicon substrate, 3b is an aluminum wiring layer formed as a metal film, and 2c is a surface protection insulating film. A phosphorus glass film (hereinafter referred to as PSG film) formed as
Reference numeral 4 indicates a pinhole generated as a manufacturing defect in the PSG film 2c, and reference numeral 5 indicates a disconnection portion formed by etching in the aluminum wiring layer 3b. In the method of this embodiment, the semiconductor device having the pinhole 4 is immersed in a real-minimum etching solution using a well-known etching technique.
するとＰＳＧ膜２ｃはエッチングマスクとして働き、ピ
ンホール部４のみエッチング液が侵入し、所定時間が経
過すると、ＰＳＧ膜２ｃのピンホール４の周囲のみのア
ルミニウム配線がサイドエッチングされ、アルｊミニウ
ム配線上にピンホール４による断線部５が形成され、こ
のエッチングされた半導体装置のアルミニウム配線の電
気抵抗はエッチング前と比べて大きくなつている。この
ように本実施例方法では、半導体絶縁被膜３の欠陥（ピ
ンホール、クラック等）の有無を、電気的特性の変化に
より検出でき、半導体絶縁被膜の欠陥を極めて簡単に除
去することが出来る。Then, the PSG film 2c acts as an etching mask, and the etching solution enters only the pinhole portion 4. After a predetermined period of time, the aluminum wiring only around the pinhole 4 in the PSG film 2c is side-etched, and the aluminum wiring is etched on the aluminum wiring. A disconnection portion 5 is formed due to the pinhole 4, and the electrical resistance of the aluminum wiring of the etched semiconductor device is larger than that before etching. As described above, in the method of this embodiment, the presence or absence of defects (pinholes, cracks, etc.) in the semiconductor insulating film 3 can be detected based on changes in electrical characteristics, and defects in the semiconductor insulating film can be removed very easily.
なお、上記実施例においては、アルミニウム配線上に形
成した表面保護絶縁被膜の欠陥を検出し４て試験する場
合について説明したが、第１図に示すような多層配線構
造を有する半導体装置の層間絶縁被膜２ｂの欠陥を検出
して試験する場合についても全く変わらない。また、半
導体絶縁被膜としてＰＳＧ膜に限ることはなく、例えば
、酸化シリコン膜、窒化シリコン膜、ポリミド樹脂膜等
の絶縁膜でもよい。また金属膜は、アルミニウムに限る
ことはなく、例えば、チタン、モリブデン、金、銀、銅
、クロム、白金などでもよく、また、エッチング方法と
しては、ケミカルエッチング方法に限ることはなく、プ
ラズマ等のエッチング技術を用いてもよい。In the above embodiment, a case was described in which defects in a surface protective insulating film formed on an aluminum wiring were detected and tested. The same applies to the case of detecting and testing defects in the coating 2b. Further, the semiconductor insulating film is not limited to the PSG film, and may be, for example, an insulating film such as a silicon oxide film, a silicon nitride film, or a polyimide resin film. Furthermore, the metal film is not limited to aluminum, and may be made of titanium, molybdenum, gold, silver, copper, chromium, platinum, etc., and the etching method is not limited to chemical etching, but may include plasma, etc. Etching techniques may also be used.
第３図は横軸に故障時間Ｈをとり、縦軸に残存故障率（
％）をとつて表した、樹脂封止形半導体装置の耐湿性試
験における耐久性比較を示す説明図で、実線ａはこの発
明の一実施例を表面保護絶縁被膜に適用した半導体装置
の特性を示したもので・あり、点線ｂは適用しない半導
体装置の特性を示したものである。In Figure 3, the horizontal axis shows the failure time H, and the vertical axis shows the remaining failure rate (
%) is an explanatory diagram showing a comparison of durability in a moisture resistance test of resin-sealed semiconductor devices, in which the solid line a represents the characteristics of a semiconductor device in which an embodiment of the present invention is applied to a surface protective insulating film. The dotted line b indicates the characteristics of the semiconductor device to which this is not applied.
第４図は横軸に半導体装置の破壊電圧をとり、縦軸は累
積故障率（％）をとつて表したコンデンサチャージ法に
よつてコンデンサチャージ電圧を半導体装置のある特定
端子に印加した破壊試験における破壊強度比較を示す説
明図で、実線ａは本発明の一実施例を多層配線構造を有
する半導体装置の層間絶縁膜に適用した半導体装置の特
性を示したものであり、点線ｂは適用しない半導体装置
の特性を示したものである。Figure 4 shows a breakdown test in which a capacitor charge voltage is applied to a specific terminal of a semiconductor device using the capacitor charging method, with the horizontal axis representing the breakdown voltage of the semiconductor device and the vertical axis representing the cumulative failure rate (%). In this explanatory diagram showing a comparison of breakdown strength in , solid line a shows the characteristics of a semiconductor device in which an embodiment of the present invention is applied to an interlayer insulating film of a semiconductor device having a multilayer wiring structure, and dotted line b does not apply. This shows the characteristics of a semiconductor device.
第５図は横軸に故障時間Ｈをとり、縦軸に残存故障率（
％）をとつて表した、半導体装置の連続動作試験におけ
る耐久性比較を示す説明図で、実線ａは本発明の一実施
例を多層配線構造を有する半導体装置の層間絶縁膜に適
用した半導体装置の特性を示したものであり、点線は適
用しない半導体装置の特性を示したものである。In Figure 5, the horizontal axis shows the failure time H, and the vertical axis shows the remaining failure rate (
%) is an explanatory diagram showing a comparison of durability in continuous operation tests of semiconductor devices, in which the solid line a indicates a semiconductor device in which an embodiment of the present invention is applied to an interlayer insulating film of a semiconductor device having a multilayer wiring structure. The dotted line shows the characteristics of a semiconductor device to which this is not applied.
この第３図、第４図、第５図から明らかなように、本発
明一実施例による試験方法を適用した半導体装置が、試
験方法を適用しない半導体装置に比して非常にすぐれて
いることがわかる。As is clear from FIGS. 3, 4, and 5, the semiconductor device to which the test method according to the embodiment of the present invention is applied is extremely superior to the semiconductor device to which the test method is not applied. I understand.
すなわち、第３図に示す如く、表面保護絶縁被膜の欠陥
と密接な関係のある耐湿性の向上が図られ、また、第４
図、および第５図に示す如く、層間絶縁被膜の欠陥に密
接な関係のある破壊耐量の向上、並びに製品の耐久性の
向上が計られ、高品質の製品を提供することができるの
で、実用上の効果は極めて大である。このように、本発
明によれば、絶縁被膜をマスクとして所定量エッチング
し、金属膜の電気的特性の変化てもつて絶縁被膜の欠陥
の有無を検出するようにしたので、従来のこの種の方法
に比して極めて簡単かつ確実に半導体絶縁被膜の欠陥を
発見できる効果がある。That is, as shown in FIG. 3, the moisture resistance, which is closely related to defects in the surface protection insulating film, has been improved, and
As shown in Figures 1 and 5, the breakdown resistance, which is closely related to defects in the interlayer insulation coating, has been improved, and the durability of the product has been improved, making it possible to provide high-quality products. The above effect is extremely large. As described above, according to the present invention, the insulating film is etched by a predetermined amount using a mask, and the presence or absence of defects in the insulating film is detected based on changes in the electrical characteristics of the metal film. This method has the advantage of being able to discover defects in semiconductor insulating coatings much more easily and reliably than other methods.
第１図は半導体装置において用いられる半導体絶縁被膜
の構造を説明するための断面図、第２図は本発明の一実
施例を説明するための半導体装置の断面図、第３図は本
発明の一実施例を表面保護絶縁被膜に適用した半導体装
置と適用しない半導体装置の耐湿性試験における耐久性
比較を示す説明図、第４図は本発明の一実施例を多層配
線構造の層間絶縁被膜に適用した半導体装置と適用しな
い半導体装置の破壊耐量比較を示す説明図、第５図は本
発明の一実施例を多層配線構造の層間絶縁被膜に適用し
た半導体装置と適用しない半導体装置の連続動作試験に
おける耐久性比較を示す説明図てある。
１はトランジスタ等を形成したシリコン基板、２ａはＳ
ｌＯ。FIG. 1 is a cross-sectional view for explaining the structure of a semiconductor insulating film used in a semiconductor device, FIG. 2 is a cross-sectional view of a semiconductor device for explaining an embodiment of the present invention, and FIG. An explanatory diagram showing a comparison of durability in a moisture resistance test of a semiconductor device in which an embodiment of the present invention is applied to a surface protection insulating film and a semiconductor device in which it is not applied. An explanatory diagram showing a comparison of breakdown strength between a semiconductor device to which an embodiment of the present invention is applied and a semiconductor device to which it is not applied, and Fig. 5 is a continuous operation test of a semiconductor device to which an embodiment of the present invention is applied to an interlayer insulating film of a multilayer wiring structure and a semiconductor device to which it is not applied. This is an explanatory diagram showing a comparison of durability. 1 is a silicon substrate on which transistors etc. are formed, 2a is S
lO.
Claims (1)
縁被膜を有する半導体装置の試験方法に於て、上記半導
体絶縁被膜をエッチングマスクとして、半導体絶縁被膜
直下の金属電極または金属配線を所定量エッチングした
後、上記金属電極または金属配線の電気的特性を測定し
、この電気的特性の変化から上記半導体絶縁被膜の欠陥
の有無を判定することを特徴とする半導体装置の試験方
法。1. In a test method for a semiconductor device having a semiconductor insulating film on at least a metal electrode or metal wiring, after etching a predetermined amount of the metal electrode or metal wiring directly under the semiconductor insulating film using the semiconductor insulating film as an etching mask, the above-mentioned 1. A method for testing a semiconductor device, comprising measuring the electrical characteristics of a metal electrode or metal wiring, and determining the presence or absence of a defect in the semiconductor insulating film based on a change in the electrical characteristics.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP5606480A JPS6057225B2 (en) | 1980-04-26 | 1980-04-26 | Testing method for semiconductor devices |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP5606480A JPS6057225B2 (en) | 1980-04-26 | 1980-04-26 | Testing method for semiconductor devices |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS56152247A JPS56152247A (en) | 1981-11-25 |
| JPS6057225B2 true JPS6057225B2 (en) | 1985-12-13 |
Family
ID=13016645
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP5606480A Expired - Lifetime JPS6057225B2 (en) | 1980-04-26 | 1980-04-26 | Testing method for semiconductor devices |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS6057225B2 (en) |
Families Citing this family (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR100607408B1 (en) | 2004-07-21 | 2006-08-02 | 삼성전자주식회사 | Method of appraising of confidence a semiconductor wafer |
| JP5157654B2 (en) * | 2008-06-04 | 2013-03-06 | 富士電機株式会社 | Manufacturing method of semiconductor device |
| JP4792103B2 (en) | 2009-12-25 | 2011-10-12 | 株式会社東芝 | Centrifugal fans and electronics |
| US9245809B2 (en) * | 2013-03-12 | 2016-01-26 | Applied Materials, Inc. | Pin hole evaluation method of dielectric films for metal oxide semiconductor TFT |
-
1980
- 1980-04-26 JP JP5606480A patent/JPS6057225B2/en not_active Expired - Lifetime
Also Published As
| Publication number | Publication date |
|---|---|
| JPS56152247A (en) | 1981-11-25 |
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