JPS6056294B2 - semiconductor equipment - Google Patents
semiconductor equipmentInfo
- Publication number
- JPS6056294B2 JPS6056294B2 JP2893878A JP2893878A JPS6056294B2 JP S6056294 B2 JPS6056294 B2 JP S6056294B2 JP 2893878 A JP2893878 A JP 2893878A JP 2893878 A JP2893878 A JP 2893878A JP S6056294 B2 JPS6056294 B2 JP S6056294B2
- Authority
- JP
- Japan
- Prior art keywords
- film
- semiconductor device
- wiring layer
- gold
- wiring
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired
Links
Landscapes
- Local Oxidation Of Silicon (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
Description
【発明の詳細な説明】
本発明は半導体装置、特に金配線面に表面保護膜を有す
る構造の半導体装置に関するものてある。DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a semiconductor device, and particularly to a semiconductor device having a structure in which a surface protective film is provided on a gold wiring surface.
従来、ビームリード型半導体装置の金属膜配線構造は、
例えばＴｉ−Ｐｔ−Ａｕのように表面がＡｕ膜で成る積
層構造であつた。Conventionally, the metal film wiring structure of beam lead type semiconductor devices is
For example, it had a laminated structure such as Ti--Pt--Au, in which the surface was made of an Au film.
通常、Ａｕ膜は柔らかい性質のものであるため、配線部
に傷が入り易く、該種半導体装置の動作不良を生じさせ
る原因になつていた。上記改善策として、表面保護膜を
被覆することが試みられている。この被覆材とし−て一
般的にＳｊ０２膜やＳｉ３Ｎ４膜あるいはポリイミド膜
等が用いられる。一方、Ａｕ膜配線を施したこのような
半導体装置は、動作特性の安定性からみて印加される熱
サイクル条件が約３００℃に限定されるため、それ以下
の温度条件て該表面保護膜を；被覆処理しなければなら
ない。前述したＳｉ３Ｎ４膜はポリイミド膜に比らべて
電気絶縁性が優れているため、半導体装置特性の信頼度
が良い。しカルながらＡｕ膜が活性材料でないためＳｉ
３Ｎ４膜はＡｕ膜面との接着性が悪く、該界面から剥離
され易く、表面保護の役目を充分に果しきれなかつた。
本発明の目的は上記の欠点を除去し、Ａｕ膜を有する半
導体装置主面にＳ１。Ｎ。膜て成る表面保護膜を接着性
良く施設ならしめる構造の半導体装置を提供することに
ある。本発明の特徴は、半導体基板の不純物領域にアル
ミニウム（Ａｌ）のみからなる第１の配線層が設けられ
、該第１の配線層の一部の所定領域にチＩタニウムー白
金−金（Ｔｉ−Ｐｔ−Ａｕ）からなるビームリード型の
第２の配線層が接続され、この第２の配線層の最上膜て
ある金膜（Ａｕ）に銅膜（Ｃｕ）が被着され、該銅膜（
Ｃｕ）上をシリコン窒化膜（Ｓ１。Normally, since the Au film is soft, the wiring portion is easily damaged, causing malfunction of the semiconductor device. As a measure to improve the above, attempts have been made to cover the surface with a protective film. As this covering material, a Sj02 film, a Si3N4 film, a polyimide film, or the like is generally used. On the other hand, in such a semiconductor device with Au film interconnection, the thermal cycle conditions applied are limited to about 300° C. from the viewpoint of stability of operating characteristics, so the surface protective film can be removed under temperature conditions below that; Must be coated. The aforementioned Si3N4 film has superior electrical insulation properties compared to polyimide films, and therefore has good reliability in semiconductor device characteristics. However, since the Au film is not an active material, Si
The 3N4 film had poor adhesion to the Au film surface, was easily peeled off from the interface, and could not fully fulfill its role of surface protection.
An object of the present invention is to eliminate the above-mentioned drawbacks, and to form an S1 film on the main surface of a semiconductor device having an Au film. N. An object of the present invention is to provide a semiconductor device having a structure in which a surface protective film consisting of a film can be used as a facility with good adhesion. The present invention is characterized in that a first wiring layer made only of aluminum (Al) is provided in an impurity region of a semiconductor substrate, and a predetermined region of a part of the first wiring layer is provided with titanium-platinum-gold (Ti- A beam-lead type second wiring layer made of (Pt-Au) is connected, and a copper film (Cu) is deposited on the topmost gold film (Au) of this second wiring layer.
Cu) is covered with a silicon nitride film (S1).
Ｎ０）が表面保護膜として被覆している半導体装置てあ
る。本発明によると、前述した従来技術の欠点が除去て
き、即ち、絶縁性と界面接着性の表面保護膜特性の良い
半導体装置となり、信頼度特性も向上する。There is a semiconductor device whose surface is coated with N0) as a surface protective film. According to the present invention, the drawbacks of the prior art described above are eliminated, and a semiconductor device with good surface protection film characteristics such as insulation and interfacial adhesion is obtained, and its reliability characteristics are also improved.
次に本発明について図面を参照して説明する。Next, the present invention will be explained with reference to the drawings.
尚、説明の都合上、Ａｌ−（Ｔｉ−Ｐｔ−Ａｕ）の２層
配線構造で示し、外部端子領域及び不純物拡散素子領域
の導電型については省略した。第１は本発明の一実施例
の表面保護膜を有する半導体装置の断面図であり、シリ
コン基板１とＳｉＯ。For convenience of explanation, a two-layer wiring structure of Al-(Ti-Pt-Au) is shown, and the conductivity types of the external terminal region and the impurity diffusion element region are omitted. The first is a cross-sectional view of a semiconductor device having a surface protection film according to an embodiment of the present invention, showing a silicon substrate 1 and SiO.
膜２（又はＳｉ、Ｎｏ膜又はそれらを組合せた膜）の半
導体基板に拡散素子領域３とオーミック接触層４を有し
、Ａｌ膜５を配線して、且つ配線間をＡ１。０３膜６で
分離して第１層目配線を形成させ、ＳｌＯ２膜７を中間
絶縁層とし、所定領域を開孔してＴｉ−Ｐｔ−Ａｕ膜８
を施設し、更にＣ暎９を該Ａｕ膜面に載せ、主面全体に
Ｓｉ３Ｎ４膜１０を被覆して表面保護膜とした半導体装
置である。A diffusion element region 3 and an ohmic contact layer 4 are provided on the semiconductor substrate of the film 2 (or a Si, No film, or a combination thereof), an Al film 5 is wired, and an A1.03 film 6 is formed between the wires. The first layer wiring is formed by separating, using the SlO2 film 7 as an intermediate insulating layer, and forming holes in a predetermined area to form a Ti-Pt-Au film 8.
This is a semiconductor device in which a C layer 9 is placed on the Au film surface, and the entire main surface is covered with a Si3N4 film 10 to serve as a surface protection film.
本実施例の構造を得る方法としては、例えば、Ｔｉ−Ｐ
ｔ膜上にＡｕ膜を２〜３μｍ電気メッキで施設して上記
構成を形成する。この状態で、低温スパッタ法（低温条
件は約２００′Ｃ位）を行い、Ｓｉ３Ｎ４膜を該主面積
全体に１〜３μｍの厚さで付着させる。Ｓｉ３Ｎ４膜は
Ｃｕ膜と接着性が良く、又、表面保護膜としての電気絶
縁性及び機械的接着性に優れた半導体装置になり得る。As a method for obtaining the structure of this example, for example, Ti-P
The above structure is formed by electroplating an Au film of 2 to 3 μm on the T film. In this state, a low-temperature sputtering method (low-temperature condition is approximately 200'C) is performed to deposit a Si3N4 film to a thickness of 1 to 3 .mu.m over the entire main area. The Si3N4 film has good adhesion to the Cu film, and can be used as a surface protective film to provide a semiconductor device with excellent electrical insulation and mechanical adhesion.
第１図は本発明の一実施例の表面保護膜を有する半導体
装置の断面図てある。
尚、図において、１・・・・・シリコン基板、２・・・
・ＳｉＯ２、３・・・・・・不純物拡散領域、４・・・
・・・オーミックコンタクト層、５・・・・・・Ｎ層、
６・・・・・・Ａｌ２Ｏ３、７・・・ＳｉＯ２膜、８・
・・・・・Ｔｉ−Ｐｔ−Ａｕ膜、９・・・・・・ＣＵ膜
、１０・・・・・・Ｓｉ３＼膜である。FIG. 1 is a sectional view of a semiconductor device having a surface protective film according to an embodiment of the present invention. In addition, in the figure, 1... silicon substrate, 2...
・SiO2, 3... Impurity diffusion region, 4...
...Ohmic contact layer, 5...N layer,
6... Al2O3, 7... SiO2 film, 8...
...Ti-Pt-Au film, 9...CU film, 10...Si3\ film.
Claims (1)
る第１の配線層が設けられ、該第１の配線層の一部の所
定領域にチタニウム−白金−金からなるビームリード型
の第２の配線層が接続され、この第２の配線層の最上膜
である金膜に銅膜が被着され、該銅膜上をシリコン窒化
膜が表面保護膜として被覆していることを特徴とする半
導体装置。1 A first wiring layer made only of aluminum is provided in an impurity region of a semiconductor substrate, and a beam lead type second wiring layer made of titanium-platinum-gold is provided in a predetermined region of a part of the first wiring layer. A semiconductor device characterized in that a copper film is deposited on a gold film which is the uppermost film of the second wiring layer, and a silicon nitride film covers the copper film as a surface protection film.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2893878A JPS6056294B2 (en) | 1978-03-13 | 1978-03-13 | semiconductor equipment |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2893878A JPS6056294B2 (en) | 1978-03-13 | 1978-03-13 | semiconductor equipment |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS54121057A JPS54121057A (en) | 1979-09-19 |
| JPS6056294B2 true JPS6056294B2 (en) | 1985-12-09 |
Family
ID=12262337
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP2893878A Expired JPS6056294B2 (en) | 1978-03-13 | 1978-03-13 | semiconductor equipment |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS6056294B2 (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US11024510B2 (en) | 2019-09-20 | 2021-06-01 | Kioxia Corporation | Pattern forming method and method of manufacturing semiconductor device |
-
1978
- 1978-03-13 JP JP2893878A patent/JPS6056294B2/en not_active Expired
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US11024510B2 (en) | 2019-09-20 | 2021-06-01 | Kioxia Corporation | Pattern forming method and method of manufacturing semiconductor device |
Also Published As
| Publication number | Publication date |
|---|---|
| JPS54121057A (en) | 1979-09-19 |
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