JPS6051309A - Gain control circuit - Google Patents

Abstract

PURPOSE:To extent the gain variable range of a circuit and to make a low-voltage operation possible by constituting the circuit so that the amplitude variation of an input signal is held within a range of the PN junction forward voltage of an active element constituting a constant current source. CONSTITUTION:Ratios of currents flowed between collectors and emitters of transistors TRs Q11 and Q14 and those of TRs Q12 and Q13 are varied in accordance with a control current IC. When these ratios are denoted as (k) (0<=k<= 1) and a ratio of emitter areas of TRs Q17 and Q18 is denoted as alpha:1, 1/alpha of the current of the sum of individual currents flowed to emitter and collector paths of TRs Q12 and Q14 is supplied to a resistance R15 by the ratio of emitter areas TRs Q17 and Q18. Consequently, the current flowed to the resistance R15 is indicated by a formula (5) (where VF is the forward voltage between the base and the emitter of a TR and R is resistance values of resistances R12 and R13). Thus, (k) is varied to vary the signal gain from 1/alpha to 1 continuously.

Description

DETAILED DESCRIPTION OF THE INVENTION [Technical Field of the Invention] The present invention relates to a gain control circuit for varying contrast in, for example, television processing, and more particularly, to a gain control circuit suitable for low power supply voltage driving.

[Technical background of the invention]

A contrast control circuit provided in a video signal amplification stage of a television receiver or the like is a circuit that varies only the signal gain without changing the DC gain of the video signal.

FIG. 1 shows a gain control circuit used in a conventional contrast control circuit.

In FIG. 1, 1'81 is an input signal source, which is connected to the base of the signal source transistor Q1 via a capacitor C1. A DC voltage is applied to the base of this signal source transistor Q1 from a voltage source vX via a resistor R1, and an input signal from the input signal source 11 s 1 is led out to its emitter. Further, the collector of this signal source transistor Q1 is connected to the power supply terminal VccK, and the emitter is connected to a ground point through a resistor R8.

The emitters of the 1d-@ source transistors Q1 are connected to the emitters of the transistors Q2-Q11 via resistors Rs #R4, respectively, and signal components corresponding to the resistance values of the resistors R1a to R4 are transmitted to the transistors (h, Qa). The voltage source V1 is applied to the bases of these transistors Qx and Qll through a resistor R5, and the voltage source V1 is applied to the bases of these transistors Qx and Qll, respectively.
Ql+ is driven as a constant current source.

Furthermore, the emitters of the transistors (h and Qs are grounded through resistors r and R11+R7, respectively), while the collectors of the transistors Qx and Qs are connected to a first differential terminal consisting of X1 and a second transistor Q4-Qs. The emitters of the dynamic amplifiers are connected to a common connection point, and the emitters of a second differential amplifier consisting of the third and fourth transistors Qm and Qt are connected to a common connection point.

In the first differential amplifier and the second differential amplifier, the bases of the first and fourth transistors Qa and Qt are connected in common, and the bases of the second and third transistors Qs and Qs are respectively connected in common.
The bases of are connected in common. A control current Ic from a control voltage source v2 is supplied to the common base of the first and fourth transistors Q4 and Qt, and
A DC voltage from a voltage source v3 is applied to the common base of the second and third transistors Qs and Qa. Furthermore, the collectors of the first and third transistors Q4 and Qa are commonly connected, and a load resistor R8 is interposed between the connection point and the power supply terminal Vcc, and a signal formed across the load resistor am is The current is led out to the W terminal To as an output signal U( ) via the output transistor Q8. The collector of this output transistor Q@ is connected to the power supply terminal VCC, while the output terminal To Ic
The connected emitter is grounded via a resistor R9.

In the conventional control circuit 611 having the above configuration, for example, the resistors R6 and R7 have the same resistance value, and the resistance values are set by making the ratio of the resistors Rsh and R4 correspond to the maximum and minimum contrast ratios. , transistor Q
Collector current I of 3! and the collector current Ist of transistor Q3 have the same DC component and are constant;
The 4M components IS2 and IS3 become currents whose magnitude corresponds to the ratio of the resistors R3 and R4. These collector currents ① and 3 are connected to the first and second transistors Q4-
Qs and the third and sheath 4 transistors Q6. Each of the currents and the miter currents of Q7 are sucked depending on the magnitude of the control current Ic. Therefore, when the control current ic becomes large, the collector current of the first transistor Q4 becomes
becomes larger than the collector current of transistor Q@, and transistor Q! Collector current of 1. The signal component IS2 superimposed on the signal component Isa from the transistor Qs
The signal voltage flowing across the load resistor R, is applied to the base of the output transistor Q, and passes through the emitter of the transistor Q8. output signal and 1. is output. At this time, resistance ll! Most of the signal component Is2 of the transistor Q3 flows through. Also, the control current I
When c becomes smaller, the collector current of the third transistor Q6 becomes larger than the collector current of the first transistor Q6 (K < ftF),) superimposed on the collector current of the range nut Q8.
5- A larger amount of the signal component Isa than the signal component IS2 from the transistor Q2 flows through the load resistor ■ζB, and the signal voltage at both ends thereof is led out to the emitter of the output transistor Q8 as an output signal. At this time, most of the signal component Isa from the transistor Q3 flows through the resistor R8.

In addition, the DC components of the collector currents 2 and 2 of the transistors Q2 and Qa are constant, and the output transistor Q8
The average DC voltage derived at the emitter of is constant regardless of changes in control current Ic.

In this manner, by changing the control current Ic, it is possible to obtain an output signal in which only the signal component of the input signal is varied.

[Problems with background technology]

The conventional circuit described above is required to have a large contrast variable range, that is, a large signal amplitude change.

Further, even if the power supply voltage VCC is a low voltage, the contrast variable range is required to be wide.

When attempting to realize such a request with the conventional circuit described above, the output signal is obtained as the 6-4g voltage generated across the load resistor R, so when the gain of the circuit is increased, the amplitude of the signal also increases. The voltage across load resistor R increases. The voltage across this load resistor R is the power supply voltage V
Since it is limited by the size of CC, if you try to widen the contrast variable range, it is natural that it will change to Den III! It was necessary to increase the value of I city pressure VCC.

[Purpose of the invention]

The present invention has been made in view of the above-mentioned points, and provides a gain control circuit that can widen the gain DJ variation range of the circuit and widen the contrast variation range even when the power supply voltage is low. The purpose is to provide.

[Summary of the invention]

The present invention provides a first constant current source in which a signal current is superimposed on a connection point where the emitters of a first differential amplifier including first and second transistors are commonly connected. A second constant current source is connected to a connection point where the emitters of a second differential amplifier consisting of third and fourth transistors are connected in common, and the bases of the first and fourth transistors are connected to each other. In the variable gain amplifier, a control image signal from a control signal source is commonly supplied to the first and third transistors, and a DC voltage from a voltage source is commonly applied to the bases of the second and third transistors. The input terminals of third and fourth constant current sources with different small currents are connected to each differential output terminal of the second differential amplifier, and the output terminals of these third and fourth current sources are connected in common. ■ Force signal from the connection point 11
It is designed so that ysul can be used.

[Embodiments of the invention]

Hereinafter, the present invention will be described with reference to illustrated embodiments.

FIG. 2 is a circuit diagram showing a gain control circuit according to an embodiment of the present invention. Q9 is a transistor whose base is supplied with an input signal from an input signal source named V32 via a capacitor C2.

A DC voltage from a voltage source V4 is applied to the base of the transistor Q9 via a resistor R1tl, and a resistor R11 is connected between the emitter of the transistor Q9 and the ground point, and the input signal is superimposed as a signal current. 1 constant current source. Further, the voltage source v4 is applied to the base of the transistor Q1o via a resistor 111. This transistor Qso has a resistor between its emitter and ground. , and constitutes a second constant current source that supplies a current according to the magnitude of the DC voltage supplied by the voltage source v4.

The collectors of these transistors Q and Qlo are connected to the emitter common connection point of the first differential amplifier consisting of the first and second transistors Q+t Connected to the emitter common connection point of the differential amplifier.

The bases of the first and fourth transistors Qu and Q□4 are commonly connected to the output terminals T and t/C of a control signal source v5 that supplies a control current Ic. On the other hand, the bases of the second and fourth transistors Qu + Qts are commonly connected to the output terminal T2 of the voltage source v6.

1, the first and third transistors Qll * Qlm
The collectors of are commonly connected to the input terminal T of a third constant current source 19- which is constituted by a current mirror circuit including transistors Qts and Qlll. This third constant current source 1 is a transistor Q1. The collector and base of the transistor Q5s are shorted, and the voltage between the base and emitter of the transistor Q5s is
pressure and transistor Q1. By making the base-emitter voltages of the transistors equal, the sum of the collector currents of the first and third transistors Q+t + Qts is made equal to the current supplied to the charging resistor R15 of the transistor Qis. Note that each emitter of the transistor Q16°Qlg is connected to the power supply terminal VCCKMj:.

Further, the p-rectors of the second and fourth transistors Q1+014 are commonly connected to the input terminal T4 of the fourth constant current source 2, which is also made up of the multi-emitter transistor Qsy and the transistor Q+a of the current mirror circuit.

This fourth constant current source 2 transistors Ql? and Qu+
By making the respective emitter areas of the second and fourth transistors Q1! .

The sum of the collector currents of Q14 (the current at the input terminal T4 of the fourth constant current source 2) is constrained by the relationship of the emitter area ratio and is derived from the collector of the transistor QII. 15.

However, 1-1 such a configuration U) transistor Q1? and Q
Even when the emitter area ratio of ss is set to 111, by inserting a resistor of a predetermined value between the power supply terminal VCC and each emitter, the output current to the button spring resistor can be made different from the current at the input terminal. It may be possible to do so. The collector and base j of the multi-emitter transistor Q17 are short-circuited so that the base-to-emitter voltage of the transistor Q1t and the base-to-emitter voltage of the transistor Q11 are equal. Also, the transistor Q1y
Each emitter of +Qlg is connected to a power supply terminal Vcc.

ing. Further, the output terminal T5 is connected to the output terminal TOUT of the circuit.

The above advantages control the operation of the control circuit by resistors R11 and 1 (
The explanation will be made assuming that the values of 13 are equal. 8! ], transistors Qe and Qt serving as second constant current sources. II′i Current Ig+1 according to the magnitude of DC voltage from voltage source V4
1 to each collector. The current ■9 includes a signal component from the input signal source us2. Here, the DC voltage supplied by the voltage source V4 is V4, and each transistor Qs
+ VF is the forward voltage between the base and emitter of Qzo.

Resistance R1! I R1m resistance value R1 input signal UB
Then, the currents Ie and Is. ■・−V4−VF＋” ・・・・・・・・・・・・・・・
・・・・・・・・・・・・・・・ (1) It can be represented by R. The currents Is and Ito are the sum of the currents flowing through the collector-emitter paths of the first and second transistors Qll, Q12 and the third and fourth transistors Q1+11Q+4, respectively.
the respective currents flowing through the collector-emitter paths of the transistors Q111Q14 and the second and fourth transistors Qt
The ratio of the currents flowing through the collector-emitter paths of s and Q1g is varied depending on the magnitude of the control current Ic. Let this ratio be k (0≦≦1), and the transistor Q! that constitutes the fourth constant current source 2! The emitter area ratio of 7 and Qts is a
:1, the first and fourth transistors Qo, Q1
Each current flowing through the collector-emitter path of 4 is kk・■
1 and k.110, and the currents U flowing through the collector-emitter paths of the second and third transistors Qu and Qta become h(I-k).9 and (1k)111go. 1, the S current, which is the sum of the currents flowing through the emitter-collector paths of the second and fourth transistors Q1x and Qt4, is given by the ratio νζ of the emitter areas of the multi-emitter transistor Qlt and the transistor 018, and the allowable resistance is 1j15 K.
It is supplied at a rate of 1/a.

Therefore, the current 11s flowing through the valve resistance f, 5 is:
, and rearranging this results in the following. Substituting fil and the relationship in equation (2) into equation (4) yields.

13- In this equation (5), the coefficient of υS/H is a term (hereinafter referred to as signal gain) that varies the magnitude of the input signal νS, and is varied by the control signal Ic. Now, when k=00, the first and fourth transistors Q It *Q14
This is the case when the signal gain t is cut off.
d 1/a. It's a trench, when k=1, the second and third
This is a case where the transistors Qsz and Qss are cut off, and the signal gain at this time is 1.

Therefore, the signal gain is continuously variable from 1/a to 1, and by making a larger than 1 or smaller than 1, the variable range of the signal gain can be set in any way.

Note that the coefficient term of (Va VF)/R is a DC gain that sets the magnitude of the average DC voltage, and does not include the value of k that is varied by the control signal Ic, so it can always be constant.

According to such a circuit, transistors Qs and Qt.

Since the load (active load) is a diode connection in which the collectors and bases of the transistors Qss and Qty are short-circuited, the change in the amplitude of the signal current due to the variable gain increases the forward voltage VF between the base and emitter.
It is suitable for low voltage driving. Furthermore, since it is a current drive circuit, it has the advantage that it has good frequency characteristics and is also effective in controlling signal conduction.

〔Effect of the invention〕

As explained above/Thus, according to the present invention, the amplitude change of the input signal whose gain is varied is suppressed within the range of the PN junction forward voltage of the active element constituting the constant current source, and the gain υ is suppressed. This has the effect that the variable range can be widened and that it does not depend on the magnitude of the power supply voltage.

[Brief explanation of the drawing]

(b) A schematic diagram showing the gain control circuit of the first embodiment, and FIG.
FIG. 2 is a circuit diagram showing a circuit. 1.2... Constant current source, Q, ~(ha... Transistor, R11~RHs + R1s - Resistor, V4
+ V@... Voltage source, v5... Control signal source, "8
2...Input signal source. Agent (+l'J!, I Norichika Kensuke (and 1 other person) 15
−

Claims (1)

[Claims] A first constant current source on which an input signal is superimposed is connected to a common emitter connection point of a first differential amplifier made up of first and second transistors, and a second constant current source is connected to a common emitter connection point of a first differential amplifier made up of first and second transistors. A second differential amplifier comprising a transistor is connected to a common emitter connection point, the bases of the first and fourth transistors are commonly connected to this connection point, and a control signal source is connected to the second and third transistors. The bases of the transistors are connected in common and a voltage source is connected to this connection point, the collectors of the first and third transistors are connected in common, and the collectors of the second and fourth transistors are connected in common. The input terminals of third and fourth constant current sources with different output current values are connected to the commonly connected connection point, respectively, and the output terminals of these third and fourth constant current sources are connected in common. A gain control circuit configured to take out an output signal whose amplitude is varied by the control signal of the controllability No. 1 source at the connection point.