JPS6048525A - Microcomputer - Google Patents
MicrocomputerInfo
- Publication number
- JPS6048525A JPS6048525A JP58156076A JP15607683A JPS6048525A JP S6048525 A JPS6048525 A JP S6048525A JP 58156076 A JP58156076 A JP 58156076A JP 15607683 A JP15607683 A JP 15607683A JP S6048525 A JPS6048525 A JP S6048525A
- Authority
- JP
- Japan
- Prior art keywords
- channel length
- mosfet
- circuit section
- standby
- power source
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
- Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
- Y02D10/00—Energy efficient computing, e.g. low power processors, power management or thermal management
Landscapes
- Direct Current Feeding And Distribution (AREA)
- Power Sources (AREA)
- Microcomputers (AREA)
Abstract
Description
【発明の詳細な説明】
〔発明の属する技術分野〕
本発８Ａはマイクロコンピュータに関し、特に０Ｍ０８
ｍで１チツプに構成され、スタンバイ機能を有するマイ
クロコンピュータに関する。[Detailed description of the invention] [Technical field to which the invention pertains] The present invention 8A relates to a microcomputer, and in particular, 0M08
The present invention relates to a microcomputer configured with m chips on one chip and having a standby function.
従来、マイクロコンピーータの＜Ｋ頼性を上げるために
、スタンバイ機能？有するマイクロコンピーーメか使用
されている。Traditionally, standby functions have been used to increase the reliability of microcomputers. A microcomputer with a microcomputer is used.
第１図は従来のスタンバイ機能全有するマイクロコンピ
ー−夕の一例の要部のブロック図である。FIG. 1 is a block diagram of the main parts of an example of a conventional microcomputer having all standby functions.
このマイクロコンピュータは０ＭＯ８装置で１チツプに
作られるものである。第１図におＡて、ｌはＣＰＵ、２
にＲＯＭ、３はＲＡＭ、４は発振回路部、５はスタンバ
イ制御７リツプ７０ツブでめる。スタンバイ状態への移
行要求が発生すると。This microcomputer is made on one chip using 0MO8 equipment. In FIG. 1, l is the CPU, 2
ROM, 3 RAM, 4 oscillation circuit section, 5 standby control 7 lip 70 blocks. When a request to transition to standby state occurs.
ｅＰＵｌは、スタンバイ’＋ｔｌｌＮフリソゲ７ｏツブ
５ｔスタンバイ制御ノリノブ７０ソゲセント信号８でセ
ットし、発振回路部４全スタンバイ５ＢＩＪ御部５の出
力発振停止信号９で停止させて、チノグＰ′３部はスタ
ンバイ状態に入シ、几ＡＭ３のデータのみ全保持する。ePUl is set with standby' + tllN frisoge 7o knob 5t standby control knob 70 sogesent signal 8, and stopped with output oscillation stop signal 9 of oscillation circuit section 4 all standby 5 BIJ control section 5, and chinogu P'3 section is in standby state. At the beginning, only all data of AM3 is retained.
逆に、動作状態への移行に、外部制御端子７によってス
タンバイｆｔ１ｌＪ御フリツプ７０ツブ５全リセントし
、発振Ｎ踏部４全動作状態へ移行し、全体が動作状態に
入る。Conversely, when transitioning to the operating state, the external control terminal 7 causes the standby ft1lJ control flip 70 and knob 5 to all re-center, and the oscillating N-tread section 4 shifts to the operating state, and the entire unit enters the operating state.
しかし、集Ｕｔ度？上げる為に菓子の縮小（チャンネル
長會短くする）全行なうと、トランジスタの電流オフ特
性が悪くなシ、チャンネルでのり一タ嵐流が増加し、ス
タンバイ状態時の低消費電力化が困嬬になる欠点があっ
た。But the degree? If you try to reduce the size of the confectionery (shorten the channel length) in order to increase the power consumption, the current off characteristics of the transistor will deteriorate, and the current in the channel will increase, making it difficult to reduce power consumption during standby mode. There was a drawback.
本発明の目的は、上記欠点全除去し、スタンバイ状態で
もリーク電流を抑え、低ｖｆＪ費電力化を計ることので
きる０ＭＯ８Ｈのマイクロコンピュータ全提供すること
にある。An object of the present invention is to provide an entire 0MO8H microcomputer that can eliminate all of the above-mentioned drawbacks, suppress leakage current even in standby state, and achieve low VFJ cost and power consumption.
〔発明の（構成〕
本発明のマイクロコンピータは、電源部にドレインが接
続しゲートに入力式几る制御信号によりオンオンする相
対的にチャンネル長の長いＭ０８ＦＥ’ｌ’ト、該ＭＯ
８ＦＥＴ（Ｄ７−スに接続ｔ、相ｘ”を的にチャンネル
長の短いＭ ＯＳ Ｆ Ｅ ＴでＭｑ成される回路部と
、相対的にチャンネル長の長いＭＯＳＦＥＴで構成され
前記電源部に直接に接続する回路部と全含んで構成され
る。[Structure of the Invention] The microcomputer of the present invention has a drain connected to a power supply section and an M08FE'l' gate having a relatively long channel length, which is turned on by a control signal input to the gate.
8FET (connected to D7-phase, phase It consists of all the circuit parts to be connected.
上記の相対的にチャンネル長が短いＭＯ３１ｉ’ＥＴで
構成される回路部はＣＰＵ及びＲＯＭであル、相対的に
チャンネル長が長いＭＯＳＦＥＴで構成される回路部は
ＲＡＭ、発振回路部及びスタンバイ１ｔｉｔｌ Ｈ７リ
ツプフロツプである。The circuit section made up of the above MO31i'ET with a relatively short channel length is the CPU and ROM, and the circuit section made up of MOSFETs with a relatively long channel length is the RAM, oscillation circuit section, and standby 1titl H7. It's a lip flop.
次に、本発明の実施例について図面音用いて説明する。 Next, embodiments of the present invention will be described with reference to the drawings.
第２図は本発明の一実施例のブロック図である。FIG. 2 is a block diagram of one embodiment of the present invention.
この実施例は、電源部に接続する電源端子６にドレイ／
が接続し、ゲートに入力される制御信号によジオンオン
する相対的にチャンネル長の長いｆｖｌＯ８ｆ”ＥＴ
１１と、このＭＯ８Ｉ；’ｎＴ ｌ ｉのソースに接続
し相対的にチャンネル長の短いＭＯ３ＦｆｆＴで構成さ
れるＣＰＵＩ及びＲＯＭ２と、相対的にチャンネル長の
長いＭＯＳＦＥＴでｊＦＪ成され、電源部の電源端子６
に直接に接続する几ＡＭ３．発振回路部４及びスタンバ
イ制御ノリツブフロップ５と奮含んで４１４成される。In this embodiment, a drain/
fvlO8f”ET, which has a relatively long channel length, is connected and turned on by the control signal input to the gate.
11, the CPUI and ROM2 which are connected to the source of this MO8I;'nT l i and are composed of MO3FffT with a relatively short channel length, and a MOSFET with a relatively long channel length, and are connected to the power supply terminal of the power supply section. 6
Connect directly to AM3. The circuit 414 includes the oscillation circuit section 4 and the standby control control flop 5.
即ち、データ全保持する必要のおる回路部及び制御部は
チャンネル長の長いＭｏ５Ｆｒｒで栂成し、データの保
持の必要のない回路部はチャンネル長の短いＭＯ８ＩＮ
Ｅ’ｒで構成する。In other words, the circuit section and control section that need to hold all data are made of Mo5Frr, which has a long channel length, and the circuit section that does not need to hold data is made of MO8IN, which has a short channel length.
Consists of E'r.
次に、この実施例の動作について説明する。Next, the operation of this embodiment will be explained.
スタンバイ状態の要求がＣＰＵＩで発生した場合、スタ
ンバイ制御フリップフロップ５はスタンバイ制御ノリッ
グフロソプセット４に号８でセントぜれ、ＭＯ８Ｆ’Ｅ
Ｔ ｉ ｉ全ＭＯ８ＦＥＴ制御信号１９でオフ式せ、同
時に発振回路部４を制御して発振ケ停止させてスタンバ
イ状態へ移行し、ＲＡＭ３のデータとスタンバイ制御ノ
リツブフロップ５の出力の４企保持する。When a standby state request occurs on the CPUI, the standby control flip-flop 5 is sent to the standby control flip-flop set 4 at number 8, MO8F'E
All MO8FETs are turned off by the control signal 19, and at the same time, the oscillation circuit section 4 is controlled to stop oscillation and enter the standby state, and the data in the RAM 3 and the output of the standby control flop 5 are held. .
従って、几ＡＭ３．発振回路部４．スタンバイ制御フリ
ップノロツブ５とＭＯ８ｎ”ＥＴ １１をチャンネル長
の長いＭＯＳ）ランジスタで４８にする事によって低ス
タンバイ電源電流が達成される。Therefore, 几AM3. Oscillation circuit section 4. A low standby power supply current is achieved by setting the standby control flip knob 5 and MO8n''ET 11 to 48 with long channel length MOS transistors.
動作状態への移行は、外部からの１ｔｔｌＪ−信号７に
よってスタンバイｉｉｉ！ｌ ｆｌフリップフロップ５
奮リセットし、ＭＯＳＦＥＴ１１”ｃオンにし、かつ発
振回路部４全発振状態にして、内部クロツク１０全各回
路に供給して行なわれる。The transition to the operating state is made standby by external 1ttlJ-signal 7! l fl flip flop 5
This is done by quickly resetting the clock, turning on the MOSFET 11''c, bringing the entire oscillation circuit section 4 into an oscillating state, and supplying the internal clock 10 to all circuits.
本発明は、以上説ツＪしたように、 ＭＯＳ、ｉ’ＥＴ
１１とデータ保持の必要な回路部とその制御回路部全チ
ャンネル長の長いＭＯＳ）う／ジスタで宿成し、スタン
バイ時、リーク電ＩＩｆ、に抑え、低消費１４Ｌ刀化が
できかつデータ保持の必要のない回路部分でチャ／イ・
ル長の短い素子が使用出来る挙によシ果績度全高められ
る効果がある。As explained above, the present invention is applicable to MOS, i'ET
11, the circuit section that requires data retention, and its control circuit section (MOS) with a long total channel length. CH/I in unnecessary circuit parts
In addition to being able to use elements with short lead lengths, the overall performance can be improved.
１１図は従来のスタンバイ（戊能を有するマイクロニン
ピユータの一例の要部のブロック図、第２図は本発明の
一実施例のブロック図である。
ｌ・・・・・・ＣＰＵ膵、２・・・・・・ＲＯＭ部、３
・・・・・・１（ＡＮｌぴ、４・・・・・・発振回路部
、５・・・・・・スタンバイ制御フリップ７０ノブ、６
・・・・・・電源端子、７・・・・・・外部ｆｌｊｌＪ
御信号、８・・・・・・スタンバイ制御ノリツブ７０ツ
ブセツト信−号、９・・・・・・発振停止イば号、１０
・・・・・・内部タロツク信号、１１・・・・・・ＭＯ
８ｌｉ”ＥＴ、１９・・・・・・ＭＯ８Ｉ！’ＥＴ制呻
信号。
Ｕｉｎ −＼FIG. 11 is a block diagram of the main parts of an example of a conventional micronin computer with standby (standby) function, and FIG. 2 is a block diagram of an embodiment of the present invention. 2...ROM section, 3
......1 (ANlpi, 4...Oscillation circuit section, 5...Standby control flip 70 knob, 6
...Power terminal, 7...External fljlJ
Control signal, 8...Standby control knob 70 set signal, 9...Oscillation stop signal, 10
...Internal tarok signal, 11...MO
8li"ET, 19...MO8I!'ET suppressing signal. Uin -\
Claims (2)
制御信号によジオンオンする相対的にチャンネル長の長
いＭＯ８１１１ＥＴと、該ＭＯ８Ｆ’ＥＴのソースに接
続し相対的にチャンネル長の短いＭＯＳ Ｆ Ｅ Ｔで
構成される回路部と、相対的にチャンネル長の長いＭＯ
８Ｌ’１８Ｔで構成でれ前記電源部に直接に接続する回
路部とを含むことを特徴とするマイクロコンピュータ。(1) A MO8111ET with a relatively long channel length connected to the power source and turned on by a control signal input to the gate, and a MOS F with a relatively short channel length connected to the source of the MO8F'ET. A circuit section consisting of an ET and an MO with a relatively long channel length.
8L'18T, and a circuit section directly connected to the power supply section.
される回路部がＣＰＵ及びＲＯＭで必ハ相対的にチャン
ネル長が長いＭＯＳＦＥＴで構成される回路部がＲＡ
Ｍ 、発振回路部及びスタンバイ％１ｊ御フリップフロ
ップである特許請求の範囲１（ｘ）項り己載のマイクロ
コンピュータ。(2) The circuit section composed of MOSFETs with a relatively short channel length must be the CPU and ROM, and the circuit section composed of MOSFETs with a relatively long channel length must be the RA.
A microcomputer according to claim 1(x), wherein M is an oscillation circuit section and a standby control flip-flop.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP58156076A JPS6048525A (en) | 1983-08-26 | 1983-08-26 | Microcomputer |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP58156076A JPS6048525A (en) | 1983-08-26 | 1983-08-26 | Microcomputer |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS6048525A true JPS6048525A (en) | 1985-03-16 |
Family
ID=15619776
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP58156076A Pending JPS6048525A (en) | 1983-08-26 | 1983-08-26 | Microcomputer |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS6048525A (en) |
Cited By (9)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS63175909A (en) * | 1987-01-16 | 1988-07-20 | Nec Corp | One-chip microcomputer |
| JPH01138129U (en) * | 1988-03-14 | 1989-09-21 | ||
| JPH02151947A (en) * | 1988-12-02 | 1990-06-11 | Nec Ic Microcomput Syst Ltd | Microcomputer system |
| US6046604A (en) * | 1992-04-14 | 2000-04-04 | Hitachi, Ltd. | Semiconductor integrated circuit device having power reduction mechanism |
| US6621292B2 (en) | 1993-01-07 | 2003-09-16 | Hitachi, Ltd. | Semiconductor integrated circuits with power reduction mechanism |
| US7199490B2 (en) | 2000-06-14 | 2007-04-03 | Nec Corporation | Semiconductor device for preventing noise generation |
| USRE40132E1 (en) | 1988-06-17 | 2008-03-04 | Elpida Memory, Inc. | Large scale integrated circuit with sense amplifier circuits for low voltage operation |
| US7388400B2 (en) | 1993-01-07 | 2008-06-17 | Elpida Memory, Inc. | Semiconductor integrated circuits with power reduction mechanism |
| US10607663B2 (en) | 2017-05-24 | 2020-03-31 | Renesas Electronics Corporation | Semiconductor integrated circuit device and semiconductor device |
-
1983
- 1983-08-26 JP JP58156076A patent/JPS6048525A/en active Pending
Cited By (25)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS63175909A (en) * | 1987-01-16 | 1988-07-20 | Nec Corp | One-chip microcomputer |
| JPH01138129U (en) * | 1988-03-14 | 1989-09-21 | ||
| JPH0542505Y2 (en) * | 1988-03-14 | 1993-10-26 | ||
| USRE40132E1 (en) | 1988-06-17 | 2008-03-04 | Elpida Memory, Inc. | Large scale integrated circuit with sense amplifier circuits for low voltage operation |
| JPH02151947A (en) * | 1988-12-02 | 1990-06-11 | Nec Ic Microcomput Syst Ltd | Microcomputer system |
| US6281711B1 (en) | 1992-04-14 | 2001-08-28 | Hitachi, Ltd. | Semiconductor integrated circuit device having power reduction mechanism |
| US6046604A (en) * | 1992-04-14 | 2000-04-04 | Hitachi, Ltd. | Semiconductor integrated circuit device having power reduction mechanism |
| US6356119B2 (en) | 1992-04-14 | 2002-03-12 | Hitachi, Ltd. | Semiconductor integrated circuit device having power reduction mechanism |
| US6504402B2 (en) | 1992-04-14 | 2003-01-07 | Hitachi, Ltd. | Semiconductor integrated circuit device having power reduction mechanism |
| US7750668B2 (en) | 1992-04-14 | 2010-07-06 | Renesas Technology Corp. | Semiconductor integrated circuit device having power reduction mechanism |
| US6696865B2 (en) | 1992-04-14 | 2004-02-24 | Hitachi, Ltd. | Semiconductor integrated circuit device having power reduction mechanism |
| US6175251B1 (en) | 1992-04-14 | 2001-01-16 | Hitachi, Ltd. | Semiconductor integrated circuit device having power reduction |
| US6970019B2 (en) | 1992-04-14 | 2005-11-29 | Masashi Horiguchi | Semiconductor integrated circuit device having power reduction mechanism |
| US7312640B2 (en) | 1992-04-14 | 2007-12-25 | Renesas Technology Corp. | Semiconductor integrated circuit device having power reduction mechanism |
| US7215136B2 (en) | 1993-01-07 | 2007-05-08 | Elpida Memory, Inc. | Semiconductor integrated circuits with power reduction mechanism |
| US7242214B2 (en) | 1993-01-07 | 2007-07-10 | Elpida Memory, Inc. | Semiconductor integrated circuits with power reduction mechanism |
| US7023237B2 (en) | 1993-01-07 | 2006-04-04 | Hitachi, Ltd. | Semiconductor integrated circuits with power reduction mechanism |
| US6838901B2 (en) | 1993-01-07 | 2005-01-04 | Hitachi, Ltd. | Semiconductor integrated circuits with power reduction mechanism |
| US7388400B2 (en) | 1993-01-07 | 2008-06-17 | Elpida Memory, Inc. | Semiconductor integrated circuits with power reduction mechanism |
| US7667485B2 (en) | 1993-01-07 | 2010-02-23 | Elpida Memory, Inc. | Semiconductor integrated circuits with power reduction mechanism |
| US6621292B2 (en) | 1993-01-07 | 2003-09-16 | Hitachi, Ltd. | Semiconductor integrated circuits with power reduction mechanism |
| US8106678B2 (en) | 1993-01-07 | 2012-01-31 | Elpida Memory, Inc. | Semiconductor integrated circuits with power reduction mechanism |
| US7199490B2 (en) | 2000-06-14 | 2007-04-03 | Nec Corporation | Semiconductor device for preventing noise generation |
| US10607663B2 (en) | 2017-05-24 | 2020-03-31 | Renesas Electronics Corporation | Semiconductor integrated circuit device and semiconductor device |
| US10714154B2 (en) | 2017-05-24 | 2020-07-14 | Renesas Elelctronics Corporation | Semiconductor integrated circuit device and semiconductor device |
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