JPS6045044A - Ic package - Google Patents
Ic packageInfo
- Publication number
- JPS6045044A JPS6045044A JP58152702A JP15270283A JPS6045044A JP S6045044 A JPS6045044 A JP S6045044A JP 58152702 A JP58152702 A JP 58152702A JP 15270283 A JP15270283 A JP 15270283A JP S6045044 A JPS6045044 A JP S6045044A
- Authority
- JP
- Japan
- Prior art keywords
- internal wiring
- chip
- conductor
- package
- strip line
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/58—Structural electrical arrangements for semiconductor devices not otherwise provided for, e.g. in combination with batteries
- H01L23/64—Impedance arrangements
- H01L23/66—High-frequency adaptations
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
- H01L2224/491—Disposition
- H01L2224/4912—Layout
- H01L2224/49171—Fan-out arrangements
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/11—Device type
- H01L2924/14—Integrated circuits
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/1515—Shape
- H01L2924/15153—Shape the die mounting substrate comprising a recess for hosting the device
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/1517—Multilayer substrate
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/161—Cap
- H01L2924/1615—Shape
- H01L2924/16195—Flat cap [not enclosing an internal cavity]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/30—Technical effects
- H01L2924/301—Electrical effects
- H01L2924/3011—Impedance
Landscapes
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Lead Frames For Integrated Circuits (AREA)
Abstract
Description
【発明の詳細な説明】
本発明は、ＩＣチップを収納するパッケージ、特に高周
波域で動作するＩＣチ、プを収納するに適したＩＣパッ
ケージに関する。DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a package for housing an IC chip, and particularly to an IC package suitable for housing an IC chip that operates in a high frequency range.
一般のセラミックパッケージ集伊回路では、第１図に示
すように、ＩＣチップ４は、ＩＣ，＜ツケージのパッケ
ージ基板１の上面中央間みに固着され、凹み周辺の平坦
部にメタライズされた導体２の一端とポンディング線５
により接続され、導体２の他端は外部リード３に接続さ
れ、キャップ６で蓋をして気密封止されて−・る。この
ような集積回路において、従来は、ＩＣチップ４と夕１
部リード３との間にある導体（以下内部配線と（・５）
２につ（・ては、高周波域におけるインピーダンス等を
特に考慮したものはｉｔとんどη、かっ７こ。内部配線
２のメタライズパターンも、細（・もの、太（・もの、
また、テーバ状のものなど様々で、インピーダンスとし
ては全く不揃いであった。その結果、高周波域において
は、ＩＣチップとＴＣ夕４部回路間にお（・てインピー
ダンスの平爪−合を生じ、反射による損失が増加し、周
波数特性劣化の原因とムっていた。In a general ceramic package integrated circuit, as shown in FIG. One end of and bonding wire 5
The other end of the conductor 2 is connected to an external lead 3 and hermetically sealed with a cap 6. In such an integrated circuit, conventionally, an IC chip 4 and an IC chip 1 are connected to each other.
Conductor between lead 3 (hereinafter referred to as internal wiring (・5))
Second, the metallization pattern of the internal wiring 2 is also thin(・), thick(・), etc.
In addition, there were various types such as tapered ones, and the impedance was completely uneven. As a result, in the high frequency range, impedance matching occurs between the IC chip and the TC circuit, increasing loss due to reflection and causing deterioration of frequency characteristics.
本発明の目的は、収納したＩＣグツズとＩＣクト部回路
間のインピーダンスの不整合をたくりことのできるＩＣ
パッケージを提供するにある。An object of the present invention is to create an IC that can eliminate impedance mismatch between the stored IC goods and the IC block circuit.
There is a package to offer.
本発明のＩＣパッケージは、ＩＣチップと夕１部リード
との間の内部配線を、収納するＩＣヲソプと外部回路の
入出力インピーダンスに等しい特性インピーダンスをも
つストリップライン構造としている。よって、内部配線
のチップの動作特性に及ぼす影響が軽減される。In the IC package of the present invention, the internal wiring between the IC chip and the first lead has a stripline structure having a characteristic impedance equal to the input/output impedance of the IC chip and the external circuit. Therefore, the influence of internal wiring on the operating characteristics of the chip is reduced.
つぎに本発明を実施例により説明する。Next, the present invention will be explained by examples.
第２図は本発明の一実施例のＩＣパッケージを用いた集
積回路の断面図、第３図は、第２図に示す集積回路のキ
ャップを除いて示した平面図である。第２図において、
ポンディング線５と外部リード３間を接続する内部配線
２の下部に誘電体８を介して導電体７を設ける。導電体
７を接地することにより、内部配線２と導電体７とでス
トリップラインを構成する。内部配線２の巾（Ｗ）及び
誘電体８の厚さくｈ）は、ＩＣチップ及びＩＣ外部回路
の入出力インピーダンスに適合するよう決める。例えば
、誘電体８にアルミナセラミ、りを使用し、インピーダ
ンス５０Ωのストリップラインとするためには、Ｗ／ｈ
Ｔｈｌとする。導電体７は、第３図のようにすべての内
部配線２の下部全面に設けられ、すべての内部配線がス
トリップラインとして構成される。FIG. 2 is a sectional view of an integrated circuit using an IC package according to an embodiment of the present invention, and FIG. 3 is a plan view of the integrated circuit shown in FIG. 2 with the cap removed. In Figure 2,
A conductor 7 is provided below the internal wiring 2 that connects the bonding wire 5 and the external lead 3 with a dielectric 8 interposed therebetween. By grounding the conductor 7, the internal wiring 2 and the conductor 7 form a strip line. The width (W) of the internal wiring 2 and the thickness (h) of the dielectric 8 are determined to match the input/output impedance of the IC chip and the IC external circuit. For example, in order to use alumina ceramic or resin for the dielectric 8 and make a strip line with an impedance of 50Ω, W/h
Thl. The conductor 7 is provided on the entire lower surface of all the internal wirings 2 as shown in FIG. 3, and all the internal wirings are configured as strip lines.
第４図は、本発明の第２の実施例に係る集積回路のキャ
ップを取り除いた平面図であり、導電体９は内部配線２
のうち、一部の内部配線の下部に設けられ、特定の内部
配線がストリップラインとして構成されたものである。FIG. 4 is a plan view of an integrated circuit according to a second embodiment of the present invention with the cap removed.
Among these, the line is provided below some of the internal wiring, and the specific internal wiring is configured as a strip line.
なお、上記実施例では、水平方向に外部リードを出した
パッケージについて示しているが、外部リードが下方に
出るパッケージにつ（・ても、本発明を実施できる。Although the above-mentioned embodiment shows a package in which the external leads extend in the horizontal direction, the present invention can also be practiced in a package in which the external leads extend downward.
本発明は以上説明したように、内部配線をストリップラ
イン構造にすることにより、内部配線による高周波域で
のインピーダンス不整合が軽減され、内部配線がチップ
の特性に与える影響を軽減するという効果がある。As explained above, the present invention has the effect of reducing the impedance mismatch in the high frequency range due to the internal wiring by forming the internal wiring into a stripline structure, and reducing the influence of the internal wiring on the characteristics of the chip. .
第１図は従来のＩＣパッケージにＩＣチップを収納した
集積回路の断面図、第２図は本発明の一実施例にＩＣチ
、プを収納した集積回路の断面図、第３図は第２図の集
積回路のキャップを取り除（・た状態の部分平面図、第
４図は本発明の第２の実施例に係る集積回路のキ１ヤッ
プをを除（・た状態の部分平面図である。
ｌ、１１・・・・・・パッケージ基板、２・・・・・・
内部配線、３・・・・・・外部リード、４・・・・・・
ＩＣチップ、５・・・・・・ボンディング線、６・・・
・・・キャップ、７・・・・・・締型体層、８．９・・
・・・・ストリップライン接地導電体。
代理人 弁理士 内 原 晋FIG. 1 is a cross-sectional view of an integrated circuit in which an IC chip is housed in a conventional IC package, FIG. 2 is a cross-sectional view of an integrated circuit in which an IC chip is housed in an embodiment of the present invention, and FIG. FIG. 4 is a partial plan view of the integrated circuit according to the second embodiment of the present invention with the cap removed. Yes. l, 11...Package board, 2...
Internal wiring, 3...External lead, 4...
IC chip, 5... Bonding wire, 6...
...Cap, 7... Clamping body layer, 8.9...
...Stripline grounding conductor. Agent Patent Attorney Susumu Uchihara
Claims (1)
プと導ｔ１接続される外部リードとを備えたＩＣパッケ
ージにおいて、前記ＩＣグツズと外部リードとの間の配
線が所望する一定インピーダンスのストリップラインで
形成されて（・ることを特命とするＩＣパッケージ。In an IC package including a package substrate to which an IC chip is fixed and an external lead connected to the IC chip, the wiring between the IC goods and the external lead is formed of a strip line having a desired constant impedance. An IC package whose special mission is to
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP58152702A JPS6045044A (en) | 1983-08-22 | 1983-08-22 | Ic package |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP58152702A JPS6045044A (en) | 1983-08-22 | 1983-08-22 | Ic package |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS6045044A true JPS6045044A (en) | 1985-03-11 |
Family
ID=15546276
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP58152702A Pending JPS6045044A (en) | 1983-08-22 | 1983-08-22 | Ic package |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS6045044A (en) |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS62128549A (en) * | 1985-11-29 | 1987-06-10 | Nec Corp | Ic package |
| JPS62179135A (en) * | 1986-01-31 | 1987-08-06 | Mitsubishi Electric Corp | Microwave device module |
| EP0524763A3 (en) * | 1991-07-22 | 1994-02-16 | Motorola Inc |
-
1983
- 1983-08-22 JP JP58152702A patent/JPS6045044A/en active Pending
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS62128549A (en) * | 1985-11-29 | 1987-06-10 | Nec Corp | Ic package |
| JPS62179135A (en) * | 1986-01-31 | 1987-08-06 | Mitsubishi Electric Corp | Microwave device module |
| EP0524763A3 (en) * | 1991-07-22 | 1994-02-16 | Motorola Inc |
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