JPS6042896A - Method of producing printed circuit board - Google Patents
Method of producing printed circuit boardInfo
- Publication number
- JPS6042896A JPS6042896A JP15077983A JP15077983A JPS6042896A JP S6042896 A JPS6042896 A JP S6042896A JP 15077983 A JP15077983 A JP 15077983A JP 15077983 A JP15077983 A JP 15077983A JP S6042896 A JPS6042896 A JP S6042896A
- Authority
- JP
- Japan
- Prior art keywords
- aqueous solution
- hole
- electroless plating
- catalyst
- printed wiring
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Landscapes
- Printing Elements For Providing Electric Connections Between Printed Circuits (AREA)
Abstract
(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.
Description
【発明の詳細な説明】
本発明は印刷配線板の製造方法に関し、とくにスルホー
ル’を有する印刷配線板の製造方法に関する。DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a method for manufacturing a printed wiring board, and particularly to a method for manufacturing a printed wiring board having through holes.
従来、スルホールを有する印刷配線板は下記ののように
候嚢されている。まず、絶縁板の表面に銅張シした印刷
配線基板に真通孔を形成した後、塩化第一錫と塩化パラ
ジウムのa−8コロイド水溶液の無電解めっき触媒液に
&漬し、基板の表面及び孔壁上に無IM、# kt)?
き用触媒を付与する。次いで無1!解銅めっきで絶縁板
の表面及び孔壁上に無%L屏めつき換を形成し、電気銅
めつきで孔壁上の無電解め−)を膜を補強した後、印刷
−エツチング法で所望の等電回路を形成する。Conventionally, printed wiring boards having through holes have been encased as described below. First, after forming a straight hole in a copper-clad printed wiring board on the surface of an insulating plate, the surface of the board is soaked in an electroless plating catalyst solution of an A-8 colloidal aqueous solution of stannous chloride and palladium chloride. and no IM on the pore wall, #kt)?
Add a catalyst for oxidation. Then no 1! After forming a non-L refill on the surface of the insulating plate and the hole wall by copper-plating, and reinforcing the electroless plate () on the hole wall by electrolytic copper plating, a printing-etching method is applied. Form the desired isoelectric circuit.
しかし・、上記従来のスルホールを有する印刷配線板の
製造方法に・おいて、基板に貫通孔を形成した後、塩化
第一錫と塩化パラジウムの混合コロイド水溶液の無′&
屏めっき触媒液の処理1軛で無電解めっき用触媒によっ
て基板の孔壁が完全に被校嘔れない現象がしはしば生じ
る。そのため次工程の無電解メッキで形成する無vL解
めっき膜にピンホール等の欠陥を発生する原因となって
いた。塩化第一錫と塩化パラジウムの混合コロイド水溶
液のコロイド(無電解メッキ用触媒)の基板の孔壁への
吸看童は、基板孔壁面の帯電に影響され、特に孔壁表面
の負電荷によって影響される。無電解めっき用触媒によ
る基板の孔壁面の被後不良は、孔壁の表向の局部的負電
荷の蓄積のために生ずることが考えられる。However, in the above-mentioned conventional method for manufacturing a printed wiring board having through-holes, after forming through-holes in the substrate, a mixed colloidal aqueous solution of stannous chloride and palladium chloride is used.
A phenomenon often occurs in which the pore walls of the substrate are not completely covered by the electroless plating catalyst during one process of treating the plating catalyst solution. This causes defects such as pinholes to occur in the VL-free plating film formed in the next step of electroless plating. The adsorption of a mixed colloidal aqueous solution of stannous chloride and palladium chloride (catalyst for electroless plating) onto the pore walls of the substrate is affected by the charge on the pore wall surface of the substrate, particularly by the negative charge on the pore wall surface. be done. It is thought that defects in the pore wall surface of the substrate caused by the electroless plating catalyst occur due to local accumulation of negative charges on the surface of the pore wall.
゛本発明印刷配線板の製造方法は絶縁板に銅張した印刷
配線基板の所望の位置に貫通孔を形成する工程と、上記
基板の表面及び貫通孔壁を非貴金属コロイド水溶液の無
電解めっき触媒水溶液に浸漬し、第1の無電解めっき用
触媒を付与する工程と、上記基板の表面及び貫通孔壁面
に塩化第一錫と塩化パラジウムの混合コロイド水溶液の
無電解めっき触媒水溶液に浸漬し第2の無電解めっき用
触媒を付与する工程と、上lピ基板の表面及び貫通孔壁
向に無′IkL解めっき膜と電気めっき膜を順次形成す
る工程と、上記基板の表面に印刷−エツチング法によ)
所望の都電N路を形成する工程とを含むことを特徴とす
る。゛The method for manufacturing a printed wiring board of the present invention includes the steps of forming through holes at desired positions of a printed wiring board in which an insulating plate is coated with copper, and coating the surface of the substrate and the walls of the through holes with an electroless plating catalyst using a non-noble metal colloid aqueous solution. A step of applying a first electroless plating catalyst by immersing the substrate in an aqueous solution; a step of applying a catalyst for electroless plating, a step of sequentially forming a non-IkL deplated film and an electroplated film on the surface of the upper l-ply substrate and the wall of the through hole, and a printing-etching method on the surface of the substrate. yo)
The method is characterized in that it includes a step of forming a desired Toden N route.
本発明は基板の貫通孔壁面に挿置金塊コロイドの第1の
無電解めっき用触媒を付与した後、貴金属(パラジウム
)コロイドの第2の無電解メッキ用触媒を付与すること
に大きな%似があり、非資金編コロイドの第1の無電解
めっき用触媒の付与によって貫通孔壁面の局部的負電荷
の彰臀が減少し、貴会IF4(<’ラジウム)コロイド
の第2の無電解メッキ用触媒による貫通孔壁面の被〜率
が向上し、次の無電解めっき工程で析出した無X%めっ
き膜中のピンホール寺の欠陥の発生が防止され完成した
印刷配線板のスル、ホールの電気的接続の信頼性が著し
く向上する。The present invention is very similar to applying a first electroless plating catalyst of a gold bullion colloid to the wall surface of a through hole of a substrate, and then applying a second electroless plating catalyst of a noble metal (palladium) colloid. Yes, by applying a catalyst for the first electroless plating of the non-funded colloid, the local negative charge on the wall surface of the through hole is reduced, and the second electroless plating of the IF4 (<'radium) colloid is reduced. The coverage of the through-hole wall surface by the catalyst is improved, and the occurrence of pinhole defects in the X%-free plating film deposited in the next electroless plating process is prevented, and the electricity of the holes and holes in the completed printed wiring board is improved. The reliability of the connection is significantly improved.
以下、本発明の印刷配線板の製造方法の実施例を図面に
よシ説明する。Embodiments of the method for manufacturing a printed wiring board of the present invention will be described below with reference to the drawings.
第1図(aJ〜(e)Fi、本発明の詳細な説明するだ
めの印刷配線板要部の拡大断面図である。FIGS. 1(aJ to 1e)Fi are enlarged sectional views of essential parts of a printed wiring board for detailed explanation of the present invention.
第1図(a)のように絶鍬板の両面を銅張した基板10
の所望の位置にドリルを使用して貫通孔3を形成した。As shown in Fig. 1(a), a board 10 with copper cladding on both sides of the board
A through hole 3 was formed at a desired position using a drill.
なお、この基板10には、銅張エポキシカラス板を使用
した。次iで銅金縞コpイドを含有する非員金鵬コロイ
ド水溶液の無t′h4めっき触媒水溶液に基板10を浸
漬し、基板10の表面及び貫通孔3の壁面に第1の無1
に解めっき用触媒4を付与した(第1図中))。Note that, for this substrate 10, a copper-clad epoxy glass board was used. Next, in step i, the substrate 10 is immersed in a non-t'h4 plating catalyst aqueous solution containing a copper-gold-stripe colloid, and a first anhydride is applied to the surface of the substrate 10 and the wall surface of the through hole 3.
A deplating catalyst 4 was applied to the plate (see FIG. 1).
次Km(l−錫(8nCJ、)61/l、塩化パラジウ
ム(Pd c lt) 0.311/lを含有するコロ
イド水溶液の無電解めっき触媒水溶液に浸漬し、基板1
0の銅箔2の表面及び貫通孔3の壁面上に第2の無電解
めっき用触媒5を付与したく第1図(C))。なおル1
図(b)および(C)における第1及び第2の無電解め
っき用触媒4および5は印刷配線板の他の装部よ)さら
に拡大して示している。Next, the substrate 1 was immersed in an electroless plating catalyst aqueous solution of a colloidal aqueous solution containing Km (l-tin (8nCJ, ) 61/l and palladium chloride (Pd c lt) 0.311/l.
1(C)). Naoru 1
The first and second electroless plating catalysts 4 and 5 in Figures (b) and (C) are shown further enlarged (as compared to other parts of the printed wiring board).
次に液温25℃の無電解銅めっき液に約20分間浸漬し
、厚さ約0.5ミクロンの無電解鋼めつきJi16を基
板10の表面及び貫通孔3の壁面に析出−させた後、液
tM25℃の酸性硫酸鋼めっき液で電気鋼めっきを行な
い無電解銅めっき腺6上に淳さ約30ミクロンの電気銅
めつきa7を析出させた。Next, electroless steel plating Ji16 with a thickness of about 0.5 microns is deposited on the surface of the substrate 10 and the wall surface of the through hole 3 by immersion in an electroless copper plating solution at a temperature of 25° C. for about 20 minutes. Electrolytic steel plating was performed using an acidic sulfuric acid steel plating solution at 25° C., and electrolytic copper plating a7 having a thickness of about 30 microns was deposited on the electroless copper plating gland 6.
次いで、印刷−エツチング法によシ尋′−回路8を形成
し、スルホールをMする印刷配線板を製造した。なおこ
の実施例において基板100表面及び貫通孔3の壁面に
無電解鋼めっき展6を析出させた後、貫通孔3の壁面上
の無電解銅めつき腺の析出状態を電子顕微鏡で観察した
ところ、無電解銅めっき劇中にはピンホール等の欠陥は
観察でれなかった。また本発明によシ製造された印刷配
嶽板を温度260℃の絶縁油に2,0秒間浸漬した後、
液温25℃の1.1.’1−トソワロロエタン中に30
秒間浸漬する温度サイクルテストをlOプサイル繰返し
て実施したところ、スルホールの電気導通抵抗の変化は
、初期に比軟して5%以内であシ、本発明により製造さ
れた印刷配線板のスルホールの電気的接続信頼性、は著
しく尚いことが立証された。Next, a cross-circuit 8 was formed by a printing-etching method, and a printed wiring board with M through holes was manufactured. In this example, after electroless steel plating 6 was deposited on the surface of the substrate 100 and the wall surface of the through hole 3, the state of deposition of electroless copper plating glands on the wall surface of the through hole 3 was observed using an electron microscope. No defects such as pinholes were observed during electroless copper plating. Further, after immersing the printed mounting board manufactured according to the present invention in insulating oil at a temperature of 260°C for 2.0 seconds,
1.1 at a liquid temperature of 25°C. '1-30 in tosoiroloethane
When the temperature cycle test of dipping for 1 second was repeated for 10 psi, the change in the electrical conduction resistance of the through holes was within 5% compared to the initial softening. The connection reliability was proven to be significantly improved.
第1図(a)〜(e)は、本*l明の一実施例を説明す
るだめの印刷配線板要部の拡大l#r面図である。′l
・・・・・・絶縁板、2・・・・・・銅箔、3・・・・
・・貫通孔、4・・・・・・第1の無IIL解めっき用
触媒、5・・・・・・第2の無電層めっき用触媒、6・
・・・・・無電解銅めりき膜、7・・・・・・′眠気鋼
めっき展、8・・・・・・導電回路、10・・・・・・
基板。
″:!FIGS. 1(a) to 1(e) are enlarged 1#r side views of essential parts of a printed wiring board for explaining an embodiment of the present invention. 'l
...Insulating plate, 2...Copper foil, 3...
...Through hole, 4...First IIL-free deplating catalyst, 5...Second electroless layer plating catalyst, 6.
...Electroless copper plating film, 7...'Drowsy steel plating exhibition, 8...Conductive circuit, 10...
substrate. ″:!
Claims (1)
全形成ずゐ工程と、前記基板の衣向及び負通孔壁を非負
金輪コロイド水溶液の無゛−mめっき触媒水溶液に柾潰
し、第1の無電解めりき用触媒を杓与する1桂と、別記
基数の懺絢及び貰通孔壁面を塩化鵠1錫と塩化パラジウ
ムの混合コロイド水溶液の無−騎めっき触媒水溶液VC
技潰し、第2の無−解めりき用触媒を付与する工程と、
前tピ基板の鉄面及び貫通孔壁面に無電解めっき腹と電
気めっき#t)1次杉成するl−と、前記基板の表面に
印A11」−エツチング法によシ所望の=*(ロ)路を
形成する工程とを含むことを特徴とする印刷配線板の製
造方法。Completely form the shell through holes at the desired positions of the copper-plated printed wiring board, and then apply a non-negative plating catalyst aqueous solution of a non-negative gold colloid aqueous solution to the coating direction and the negative through hole wall of the board. The first electroless plating catalyst is crushed, and the through-hole walls of the separately specified base are covered with an electroless plating catalyst aqueous solution VC of a mixed colloidal aqueous solution of tin chloride and palladium chloride.
a step of applying a second non-decomposition catalyst;
Electroless plating and electroplating #t) are applied to the iron surface of the front substrate and the wall surface of the through-hole, and the desired =*( (b) A method for manufacturing a printed wiring board, comprising the step of forming a channel.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP15077983A JPS6042896A (en) | 1983-08-18 | 1983-08-18 | Method of producing printed circuit board |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP15077983A JPS6042896A (en) | 1983-08-18 | 1983-08-18 | Method of producing printed circuit board |
Publications (1)
Publication Number | Publication Date |
---|---|
JPS6042896A true JPS6042896A (en) | 1985-03-07 |
Family
ID=15504241
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP15077983A Pending JPS6042896A (en) | 1983-08-18 | 1983-08-18 | Method of producing printed circuit board |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS6042896A (en) |
Cited By (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH02297883A (en) * | 1989-01-26 | 1990-12-10 | Teledyne Inc | Printed wiring bdard which improved current control |
US6181219B1 (en) | 1998-12-02 | 2001-01-30 | Teradyne, Inc. | Printed circuit board and method for fabricating such board |
US7999192B2 (en) | 2007-03-14 | 2011-08-16 | Amphenol Corporation | Adjacent plated through holes with staggered couplings for crosstalk reduction in high speed printed circuit boards |
-
1983
- 1983-08-18 JP JP15077983A patent/JPS6042896A/en active Pending
Cited By (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH02297883A (en) * | 1989-01-26 | 1990-12-10 | Teledyne Inc | Printed wiring bdard which improved current control |
US6181219B1 (en) | 1998-12-02 | 2001-01-30 | Teradyne, Inc. | Printed circuit board and method for fabricating such board |
US7999192B2 (en) | 2007-03-14 | 2011-08-16 | Amphenol Corporation | Adjacent plated through holes with staggered couplings for crosstalk reduction in high speed printed circuit boards |
US8481866B2 (en) | 2007-03-14 | 2013-07-09 | Amphenol Corporation | Adjacent plated through holes with staggered couplings for crosstalk reduction in high speed printed circuit boards |
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