JPS6037620B2 - semiconductor storage device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a semiconductor memory device using memory cells that are optimal for high integration and high speed.

In recent years, the development of semiconductor memory has been remarkable.

Among them, MOS field effect dynamic memory is excellent in terms of high integration and low power consumption, and is widely used. One of the technologies that has enabled this remarkable development of dynamic memory is the one-transistor/cell system in which one memory cell is made of one MOS field effect transistor (hereinafter abbreviated as MOSFET) and one MOS capacitor. At the same time, we cannot overlook the flip-flop type sense amplifier, which has made it possible to implement one transistor/cell. One transistor/cell, which has been most widely used in dynamic memory to date, is one whose capacitor's charge is associated with binary information of "1" and "0"; 2 from the sound of
Since the charge accumulated in the capacitor is redistributed to the bit line which has a large electrostatic z amount, the signal input to the sense amplifier via the bit line becomes very small. Therefore, the performance of the sense amplifier is required to be highly sensitive so that it can sense very small signals, and it is also required to be sufficiently sensitive to the imbalance inherent in the sense amplifier, such as the difference in the voltage between the pair of drive transistors of the sense amplifier's flip-flop. I had to make it smaller. On the other hand, there is a 3-transistor/cell that was used in the dynamic memory cell prior to the 1-transistor cell.

This memory cell distinguishes between "1" and "0" of binary information by discharging or not discharging the bit line by a driver in the memory cell according to the stored information, and the signal amplitude appearing on the bit line is 1. It was incomparably larger than a transistor/cell. However, since the requirement of three MOSSFETs for one memory cell is fatally unsuitable for high integration, it has rarely been used in recent years. In the future, the demand for higher integration in semiconductor memories is expected to grow stronger, and dynamic memories will be no exception.

In order to achieve even higher integration, if we simply use the conventional one-transistor/cell and flip-flop sense amplifier and miniaturize it, the input signal to the sense amplifier will become smaller and smaller. On the other hand, the unbalance unique to the sense amplifier does not become so small, and eventually the signal and the unbalance (ie, noise) become approximately the same size, and the sense amplifier no longer operates properly. In view of the above points, the present invention has been developed so that even when miniaturized, the signal appearing on the bit line, that is, the input signal to the sense amplifier, does not decrease, and a sufficiently large input signal equivalent to that of the conventional 3 transistors/cell can be obtained.
The present invention also provides a semiconductor memory device having a memory cell structure suitable for highly integrated dynamic memory that can be realized with an area comparable to one transistor/cell.

FIG. 1 is an equivalent circuit diagram showing a memory cell according to an embodiment of the present invention. First MOSFET and second MOSFET
2 is an enhancement type M integrated on the same semiconductor substrate.
The gate of the first MOSFET I and the source of the second MOSFET 2 are connected by an OSFET, and this connection point is used as an information storage node 3. The source of the first MOSFET I is connected to the read word line WLR, and the drain is connected to the first bit line BL. The gate of the second MOSFET 2 is connected to the write word line W-, and the drain is connected to the second bit line BL. are connected to each. The structural features of MOSFETs 1 and 2 will be described later, but in this example, two MOS
Assuming that both FETs are made of N-channel MOSFETs, and considering the case where binary information is to be stored, node 3
When the potential is high, it is defined as "0", and when it is low, it is defined as "1".

First, I will explain how to read. During stand/stand mode, BL, BL, and WL are at high potential, and WLw is at low potential.
The selected WLR then drops to a low potential. If the stored information is "0", the first MOSFET I is turned on, current flows from BL to WLR, and the potential of BL decreases. On the other hand, if the stored information is "1", the first MOSFET I is off and the potential of BL does not fall. If the BL is kept floating during reading, the BL potential in the case of "0" can be lowered to OV. This point is fundamentally different from the conventional one transistor/cell and is an excellent point of the present invention. In actual operation, it is not necessary to reduce the potential of BL to OV using only the MOSFET of the memory cell, and it is quite possible to reduce the potential of BL by using a sense amplifier once it has fallen to a certain level.
In addition, when using a sense amplifier, there is a method of providing a load element that turns on when reading the bit line BL', or
In order to provide a reference level for 0” discrimination, the sense amplifier B
L to the opposite input end, the first MOSFE of the memory cell
A possible method is to provide a MOSFET that allows a current of about 1'2 to flow when the TI is on. For rewriting, the BL is set to the opposite state to the BL at the time of reading, that is, when BL is at a high potential, BL is set at a low potential, when BL is at a low potential, BL is set at a high potential, and WL is set at a high potential.
Turn on the second MOSFET2 by setting w to a high potential and turn on B.
Set the potential of L to node 3.

When the stored information is "0", BL is at a low potential and BL is at a high potential, so that a high potential is rewritten into the node 3. “1
”, the opposite is true. Writing is achieved by setting BL to the desired potential for writing, regardless of the previously stored information, at the time of rewriting. Figure 2 shows how this memory cell is arranged in a matrix. An equivalent circuit diagram for 4 bits is shown in the case of FIG.

Of course, the two MOSFETs that make up the memory cell can be made using a normal silicon gate process, but in the present invention, in order to achieve even higher integration, one of the MOSFETs
The source, drain, and channel regions are provided in the semiconductor substrate using the normal ET process, and the other MOS
The FET has a structure in which a source, drain, and channel region are provided in a polycrystalline semiconductor film provided on a semiconductor substrate.

The first MOSFETI in FIG. 1 has a normal structure,
FIG. 3 shows a schematic planar pattern when the second MOSFET 2 is made of a polycrystalline silicon film. 1st MOSF
ETI uses a first layer polycrystalline silicon film 11 formed on a p-type Si substrate via a gate insulating film as a gate electrode, and uses this polycrystalline silicon film 11 as a mask to form n+-type layers 12,1.
3 is diffused into the substrate to form source and drain regions. A second MOSFET 2 having a source, a drain, and a channel region is formed on an extension of the polycrystalline silicon film 11, which is the gate electrode of the first MOSFET I. The gate electrode of the second MOSFET 2 is made of an n+ type layer 14 which is opposed to this polycrystalline silicon film 11 and is diffused into the substrate via a gate insulating film. The bit line BL and the write word line WLw are made, for example, by forming a first layer polycrystalline silicon film 11, and then forming a second layer polycrystalline silicon IJ film via a CVD oxide film, and then further forming a CVD oxide film on top of the first layer polycrystalline silicon film 11. Bit line B is formed by depositing an AI film through the film.
L constitutes the output word line WLR. Bit line B
L is the n-type layer 1 which is the drain of the first MOSFETI
The write word line WLw is in contact with the n+ type layer 14 which is the gate of the second MOSFET2, and the logic word line WLR is in contact with the first MOSFET1.
The bit line BL is connected to the second MOSFET 2 of the polycrystalline silicon film 11.
It is connected to the drain part of the Note that in a normal silicon gate process, impurity diffusion does not end under the polycrystalline silicon film.

Therefore, at least the polycrystalline silicon film 1 of the n-type layer 14
The portion directly below the second MOSFET 2 to be used as the gate electrode needs to be formed in advance by ion implantation or the like before depositing the polycrystalline silicon film 11. With the above structure, the polycrystalline silicon film 11 is used as the gate electrode of one MOSFET I and at the same time as the source, drain and channel region of the other MOSFET 2, so the area occupied by the memory cell is extremely small. becomes.

For reference, FIG. 4 shows a schematic planar pattern when both the first and second MOSFETs 1 and 2 are formed by a normal silicon gate process. The first MOSFET 2 uses the polycrystalline silicon film 21 as the gate electrode, and the layers 22 and 23 diffused into the substrate as the source and drain regions.Similarly, the second MOSFET 2 uses the polycrystalline silicon film 24 as the gate electrode, and the mold layers 22 and 23 as the source and drain regions. n-type layers 25 and 26 diffused into the substrate
are used as the source and drain regions. As in the case of FIG. 3, the bit line BL and the write word line W- are formed of the second layer polycrystalline silicon film, and the bit line BL and the exposed word line WLR are formed of the AI film. In the case of Figure 4,
Since both MOSFETs have the same structure, the first M
The degree of integration is higher than in the case of FIG. 3 in that the contact hole 27 for contacting the polycrystalline silicon film 21, which is the gate of the OSFETI, and the n+ type layer 25, which is the source of the first MOSFET 2, is not required. This will be detrimental to improvement.

That is, as is clear from a comparison of one memory cell area A and B surrounded by broken lines in FIG. 3 and FIG. 4, the occupied area is smaller in FIG.
This is about a 50% decrease compared to Figure 4. In FIG. 5, contrary to FIG. 3, the second MOSFET 2 has a structure formed by a normal silicon gate process, and the first MOSFET I
This figure shows a schematic planar pattern when fabricated on a polycrystalline silicon film.

That is, the first layer polycrystalline silicon film 31 is used as a gate electrode,
A second MOSFET 2 is configured using n+ type layers 32 and 33 diffused in a p-type Si substrate as source and drain regions, and an n+ type layer 3 serving as a source of this second MOSFET 2
A source, a drain, and a channel region are formed on another first layer polycrystalline silicon film 34 which is disposed on the n-type layer portion formed continuously with the second layer as a gate electrode through a gate insulator. 1 MOSFETI is configured. It is the same as in the case of FIG. 3 that the bit line BL is written and the word line W* is formed of, for example, a second layer polycrystalline silicon film, and the bit image BL is read and the word line WLR is formed of a mountain film. Even with this structure, as a result of using the common n+ type layer 32 for the source region of the second MOSFET 2 and the gate electrode of the first MOSFET I, the contact hole 27 in FIG. 4 is unnecessary, and the memory cell area C is As in FIG. 3, the occupied area is small.

Note that in FIGS. 3 and 5, MOS transistors are shown in which source, drain, and channel regions are formed in a polycrystalline silicon film.
Although a polycrystalline layer diffused into the substrate is used as the gate electrode of the FET, it is not limited to an n+ type layer, and a polycrystalline silicon film, an AI film, or the like may be used as the gate electrode.

In addition, Mo film, MoSi
Modifications using two films, an AI film, etc. are also possible. FIG. 6 shows an equivalent circuit diagram of a memory cell according to another embodiment of the present invention.

In this embodiment, the drain of the second MOSFET 2 and the drain of the first MOSFET I are commonly connected to the bit line BL, and the bit line BL of the previous embodiment is omitted. M.O.S.
When both FETs 1 and 2 are formed of N-channel elements, the reading operation is the same as the embodiment shown in FIG. 1, but when rewriting, the potential of BL is the opposite of the readout, that is, if BL is at a high potential during reading. It is necessary to set the potential to a low potential during rewriting, and to set the potential to a high potential during rewriting if BL is a low potential during reading. In this sense, the operation is more complicated than the embodiment shown in FIG. 1, but the BL required in the embodiment shown in FIG.
This eliminates the need for wiring, allowing even higher integration. Note that in this case, the first MOSFETI is a P channel, the second MOSFETI is
By making MOSFET 2 of N-channel, it is possible to avoid the operational complexity that would occur if both were made of N-channel MOSFET.

In other words, it is “1” when node 3 is at high potential, and “0” when it is at low potential.
”, BL and WL are at high potential and WLw is at low potential during stand/stand.WLR is at low potential during reading.When it is “1”, MOSFETI is off, so the potential of BL is does not fall.When it is “0”, MOSFETI
turns on, current flows from BL to WLR, and the potential of BL decreases. After reading, BL is at a high potential when it is “1”, and is “0”.
", the potential is low. Therefore, for rewriting, set W★ to a high potential and write a potential to node 3. For simple writing, set BL to the potential you want to write at the time of rewriting. Seventh The figure shows an equivalent circuit diagram for 4 bits when the memory cells of FIG. 6 are arranged in a matrix.

In this embodiment, similarly to the previous embodiment, the MOSFET
By making one of them a structure using a normal silicon gate process and making the other a polycrystalline semiconductor film, the occupied area can be significantly reduced by 4.

As described above with reference to the embodiments, according to the present invention,
Since the current flows through the first MOSFET of the memory cell, the signal transmitted to the bit line can be much larger than the conventional one transistor/cell that reads the charge of the capacitor. Even when using the memory cell according to the present invention, it is thought that the memory operates more smoothly if the sense amplifier is shared, but in this case, the input signal to the sense amplifier can be large, so the sensitivity of the sense amplifier is It is no longer necessary to be as sensitive as in the conventional example, and therefore it becomes possible to connect a larger number of memory cells to one bit line than in the past, thereby increasing the degree of integration. Furthermore, since the sensitivity of the sense amplifier is not required to be as sharp as in the past, peripheral circuits related to sensing can be simplified accordingly, resulting in higher speed and lower power consumption. Also,
According to the present invention, since one of the two MOSFETs is formed using a polycrystalline semiconductor film, the memory cell area is reduced by about 50% compared to the case using a normal silicon gate process.

Therefore, 2 transistors/cell according to the present invention is 1.3 to 1 transistor/cell with similar pattern design rules.
The memory cell area is 1.4 times larger. If the area is reduced to this extent, it can be used in place of one transistor/cell. This is because the two transistors/cell of the present invention
Since the logic signal amount is larger than that of a transistor/cell, the peripheral circuits for detecting and amplifying it can be simplified. Furthermore, the simplification of peripheral circuits brings about another effect of reducing power consumption.

[Brief explanation of the drawing]

FIG. 1 is an equivalent circuit diagram of a memory cell according to an embodiment of the present invention;
Fig. 2 is an equivalent circuit diagram for 4 bits when this is arranged in a matrix, Fig. 3 is a schematic planar pattern showing a specific structural example of the memory cell of Fig. 1 according to the present invention, and Fig. 4 is a diagram. Similarly, FIG. 1 is a schematic planar pattern showing an example of a structure of a memory cell according to a conventional process, FIG. 5 is a schematic planar pattern showing another example of a structure according to the present invention, and FIG. 6 is another embodiment of the present invention. FIG. 7 is an equivalent circuit diagram of 4 bits when these memory cells are arranged in a matrix. 1...First MOSFET, 2...Second MOSFET, WLw...Write word line,
WL...Read word line, BL, BL...
- Bit line, 11, 31, 34... polycrystalline silicon film, 12, 13, 14, 32, 33... n-type layer. Figure 1 Figure 2 Figure 3 Figure 6 Figure 4 Figure 5 Figure 7

Claims (1)

[Claims] 1. Using a memory cell in which the gate of a first MOS field effect transistor integrated on a semiconductor substrate and the source of a second MOS field effect transistor are connected and this connection point serves as an information storage node, Information is written by making the second MOS field effect transistor conductive and controlling the voltage applied to its drain to set the information storage node to a predetermined potential. A semiconductor memory device in which information is read based on the magnitude of a current flowing when a voltage is applied between sources, wherein one of the first and second MOS field effect transistors has a source, a drain and 1. A semiconductor memory device having a channel region, the other having a source, a drain, and a channel region in a polycrystalline semiconductor film provided on a semiconductor substrate. 2. The first MOS field effect transistor has a source, a drain, and a channel region in a semiconductor substrate, and has a gate electrode made of a polycrystalline semiconductor film on this channel region with a gate insulating film interposed therebetween. The semiconductor memory device according to claim 1, wherein the field effect transistor has a source, a drain, and a channel region in a polycrystalline semiconductor film formed continuously with the gate electrode of the first MOS field effect transistor. . 3. The second MOS field effect transistor has a source, drain and channel region in the semiconductor substrate, and the first MOS field effect transistor has a semiconductor substrate formed continuously with the source region of the second MOS field effect transistor. Claim 1, wherein the impurity doped layer in the polycrystalline semiconductor film is used as a gate electrode, and the source, drain, and channel regions are provided in a polycrystalline semiconductor film provided on the gate electrode via a gate insulating film. Semiconductor storage device. 4 Arrange the memory cells in a matrix, connect the source of the first MOS field effect transistor of each memory cell to the read word line, connect the drain to the first bit line, and connect the gate of the second MOS field effect transistor to the write word line. 2. A semiconductor memory device according to claim 1, wherein the word line is connected to the second bit line, and the drain is connected to the second bit line. 5 Arrange the memory cells in a matrix, connect the source of the first MOS field effect transistor of each memory cell to the read word line, connect the gate of the second MOS field effect transistor to the write word line, and connect the source of the first MOS field effect transistor of each memory cell to the write word line. 2. A semiconductor memory device according to claim 1, wherein the drain of the MOS field effect transistor and the drain of the second MOS field effect transistor are commonly connected to a bit line. 6. Claim 2 in which the read word line is precharged during standby and only the selected read word line is discharged during read.
3. The semiconductor storage device according to item 3.