JPS6031127B2 - digital filter - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to digital filters, and more particularly to phase-linear acyclic digital filters with symmetrical coefficients.

A digital filter is a device configured to determine successive samples of a waveformed signal by multiplying each of a series of input signals by a coefficient and summing them.

For example, if the sample value of the input signal is xn and the sample value of the waveformed output signal is yn, then yn is expressed as in the following equation.

The filter expressed by this equation is called an N-order, (N11) tap acyclic filter.

As is clear from the above equation, implementing this filter requires (N11) multiplications and N additions. However, multipliers are expensive, and the number of required multipliers increases especially as the order increases, so a system that requires as few multiplications as possible is desirable. For this reason, various methods have been proposed to date to reduce the number of multipliers, among which are a memory in which all coefficient combinations are written, multiple full adders, and multiple 1-bit delay circuits. A circuit consisting of is very attractive for serial calculation systems. (In the following explanation, this circuit will be named a product-sum circuit.) This product-sum circuit has already been described in detail in US Pat. No. 3,777,13. In order to facilitate understanding of the present invention, a digital filter using a seed sum circuit will first be briefly explained.

FIG. 1 shows an example of a digital filter using a product-sum circuit, and for the sake of simplicity, it is applied to a non-recursive digital filter with four taps. As will be described later, a digital filter using a product-sum circuit can be applied not only to a non-recursive type but also to a recursive type if the output is fed back. A non-recursive digital filter with four taps is expressed as follows.

Yn=a〆n+a, Xn-, 10a2Xn-20a3Xn
-3 However, Xn is an input sample value, Yn is an output sample value, and ao, a, , a2, and a3 are coefficients.

Now, x is expressed as two's complement, x8, x;, x person, x3...
・If it is expressed in x tsubo, then Xn will be as follows. However, it is assumed that x8, x;, . . .

Therefore, Yn is expressed as follows. Yn=-(a〆80a
, approximately -, 10a is 8-20a3×8-3) ml+ Z 2
-Kne〆蚤10a, graduated-, k; 1 10a2 x Zenichi 20a3 x 5-3) As is clear from the above equation, the output sample value Yn can be obtained as follows.

By the combination of “0” and “1” for 1 bit of input, i.e.
Two combinations of the values 〆Yo + a, x Korea -, 10a2 graduation - 20a is 5-3) are written in the memory in advance. Also, the MSB is x8, x8-,, x8-2, x8
For -3 as well, the value -(a is 80a, approximately -, 10a2 is -20a3 is approximately -3) is written in the memory for the combinations.

Then, Yn can be obtained by reading out the memory according to the change in k and accumulating the result while shifting it by one bit. The circuit shown in FIG. 1 realizes this. In FIG. 1, 11, 12, and 13 are delay circuits that generate a delay of T, 20 is a memory, and three digit shift adder circuits. However, T is the sampling period. The operation of the circuit shown in FIG. 1 will be explained with reference to the timing chart shown in FIG. 2. Input terminal 1 in Fig. 1 is connected to
When the LSB (least weight digit) of
20, 130, as shown in FIG. 2 b, c, d,
B is output for xn-, xn-2, and xn-3, respectively. At this time, the input of the memory 20 is x8, x tsubo-,,
Since x history-2 and x history-3, the output is (aox history 10a, x re-, 10a is go-20a history-3), which is input to the digit shift addition circuit 30. . However, the data LS
It is assumed that all three digit shift adder circuits are reset immediately before B is input. Next bit, k=m
-1, the input of the memory 20 is x scale -1, x scale -1,
Since x is y, and x is mi, the output is (a.

xWI+a, x 畔, 10a2 pair:sa+a3×畔za), which is input to the digit shift addition circuit 301. However, 1
The bit previous data (father x insect ten a. , 縔-, 10a2 fever-
Since 20a is tsubo-3), the sum is .

In the same way, m Z 2-K (4 淋 10 a, gradation -, k = 1 10 a2 be done.

When the MSB is input, the control signal shown in FIG.
10a, approximately -, 10a2×8-20a3X8-3) is read out, and finally Y=-(a〆90a, approximately -, 10a22-
20a3 graduate-3) m10 × 2-KG + a, abbreviated -, k21 10a2 × 31 20a3 × 5-3> can be obtained.

In this example, a memory storing a negative value is required only when inputting the MSB, which doubles the amount of memory.

To eliminate this drawback, the control signals in FIG. 1 are removed, the memory is halved, and instead the memory
It is also possible to insert a circuit capable of taking two's complement numbers in response to a control signal between 0 and the digit shift adder circuit 30.
By the way, in this reference, we explained a non-recursive digital filter with 3 taps, but if the amount of memory is increased, it can be applied even when the number of taps becomes larger, and for example, instead of xn-3 If you use yn, you can easily overcome the recursive digital fill, and this means that
It can be applied to the same aircraft even if the order increases. However, there is a drawback that the required memory capacity increases exponentially as the number of taps increases. Therefore, the purpose of the present invention is to
It is an object of the present invention to provide a phase-linear acyclic digital filter configured so that the capacity of a memory lj can be reduced compared to the conventional one.

By the way, outside of the phase-linear acyclic digital fill,
It has symmetrical coefficients and is expressed as the following equation. however,
ak=aN-k (n, k are integers, N is an integer greater than or equal to 1), where xn is the input sample value, yn is the output sample value,
ak is a coefficient.

As is clear from the above equation, when N is an odd number, the same coefficient appears twice, and when N is an even number, the same coefficient appears twice, except for aN/2.

Therefore, the number of memory addresses in the seed sum circuit is
Generally speaking, 2N+1 are required, but considering the above, when N is an odd number, 2N11'2 are required, and when N is an even number, 2 is required, reducing the amount of memory. It becomes possible to significantly reduce the amount. The digital filter according to the present invention includes a plurality of delay circuits that delay a sampled input signal, a plurality of selection circuits that receive the input signal and the output signal of the delay circuit, and an output signal of the selection circuit. a programmable memory whose input address is , an accumulation circuit that accumulates the output of the memory, a delay circuit that delays an output signal of the accumulation circuit, an output signal of the delay circuit, and the accumulation circuit. The present invention is characterized in that the memory and the accumulation circuit are time-division multiplexed using a gate and a full adder circuit inputting the output signal of the memory, thereby making it possible to reduce the capacity of the memory.

Next, the present invention will be explained in detail with reference to the drawings.

As mentioned above, the configuration differs slightly depending on whether N is an odd number or an even number, so each will be explained separately below. Also, to simplify the explanation, N=
We will only explain the two cases 4 and 5, which are
No restrictions are placed on the size of N. First of all, the case where N=5 (odd number) will be explained.

FIG. 3 shows an embodiment of the present invention. Third
An input terminal 1 of the digital filter shown in the figure is supplied with a digit string xn of frequency 1/T. Figure 4a is
With input data xn sampled every 1/T, T/
During 2 hours, there is a certain number of bits of serial data, and it is ordered such that the least weighted digit is first. By the way, the digit string yn generated at the output terminal 3 of this digital filter can be obtained by the following calculation. yn=angle〆ntena,moten,tena2×n+20a2×
n+30a, ×n140a is n+5=yn(2)10yn
(1) However, yn(2)=a.

×n+a, ×n10, 10a2×n+2un(・)=a2X
N rudder 10a, X river 40a. Xm5As in the above equation, yn is y
yn can be obtained by dividing n(2) and yn(1) and finding them separately and then summing them. FIG. 3 shows a circuit that realizes this. In Figure 3, 11, 12
, 14, 15 are delay circuits giving a delay of T, 13, 16
is a delay circuit that provides a delay of T/2; 21, 22, and 23 are selection circuits; 3-way product-sum circuit; 40 is a full adder circuit; and 50 is a gate.

Now, when the LSB of the input data xn+5 shown in FIG. 4a is input to the input terminal 1 of the delay circuit 11, the output 110 of the delay circuits 11 and 12 as shown in FIGS. , 1201, xn+3 BBs are output, respectively. At this time, the control signal shown in FIG.
110 and 120 are selected and become inputs to the competition circuit 30. That is, the input address of the memory in the degree sum circuit 30 has x
Since n fences xn14 and xM3 are input, in the product-sum circuit, yn(1)=a2xn+30a. xn+40ao
xM5 is calculated and is delayed by T/2 from the input data, 3
Only 0 results will be output.

On the other hand, outputs 130, 140 of delay circuits 13, 14, 15
, 150 are designated as d, e, and f, respectively, on the timing chart of FIG.

By the way, during the period when the control signal input to the terminal 2 is "1", the selection circuits 21, 22, 23 select the outputs 150, 140, 140, which are the outputs of the delay circuits 15, 14, 13, respectively.
130 is selected. Therefore, now the output 1 of the delay circuit 13
30' At the time when the LSB of the data xn12 shown in FIG. 4d is output, as shown in FIG. 4e and f,
The LSBs of xn+, xn are output to the outputs 140 and 150 of the delay circuits 14 and 15, respectively. Therefore, the memory address inputs in the horizontal sum circuit 30 are xn, ×n0,
, xn+2, and at 3 0, yn(2)=ao&+
a, xn+, 10a2xn12 are calculated, and 3001 pieces are output during the same period as the input data X. This is shown in the timing chart of FIG. 4g. As is clear from the figure, y¥ki and yet al≧chi differ by T/2. Furthermore, the delay circuit 16 which receives the output 300 of the harmonic circuit 30 can obtain a delay of T/2. A timing chart of the output 400 of delay circuit 16 is shown in FIG. Therefore, at the output of the full adder circuit 40 which receives the output 300 of the product-sum circuit 30 and the output 400 of the delay circuit 16,
10yriki-, are output alternately during a period of T/2.

However, since the desired output is yn=yAI)+yA2), if the gate 50 is controlled by the control signal Z shown in FIG. 4j, the final output yn can be obtained as shown in FIG. 4i. can. Next, referring to Figure 5, N
An example in the case of =4 (even number) will be described. In this case, the sum of the number of coefficients is an odd number, and the case where N=3 is
Although the circuit configuration is slightly different, the operating principle is exactly the same.

As in the previous example, this will be explained using the timing chart of FIG. In FIG. 5, 11, 14, and 15 are delay circuits that produce a delay of time T, and 13 and 16 are delay circuits that produce a delay of time T/2. Further, 21, 22, and 23 are selection circuits, a Mitsukawa sum circuit, 40 is a full adder circuit, and 50 is a gate. Now, when the LSB of the input data xn+4 is input to the input terminal 1 of the delay circuit 11, the output of the delay circuit 11 is 1 1 0
Then, the LSB of xn+3 is output.

This is shown in the timing charts in FIGS. 4b and 4c. From this point until the end of MSB, T/
2, that is, the fourth input terminal 2 in FIG.
During the period when the control signal Z shown in FIG.
” is selected and becomes the address input of the memory in the product-sum circuit 30. Therefore, the address input of the memory in the product-sum circuit 30 becomes xn+4, xn13, “0”, and the address input of the memory in the product-sum circuit 30 becomes Then, yAI)=a〆n+40a,xn+3 is calculated, and the result is outputted with a delay of T/2 time.On the other hand, a timing chart of the outputs of delay circuits 13, 14, and 15 is shown. These are shown in Figure 4 d, e, and f.

By the way, during the period when the control signal Z shown in FIG. 4j is "1", the selection circuits 21, 22, and 23
150, which are the outputs of delay circuits 15, 14, and 13, respectively.
, 140, 130 are selected. Now, at a time delayed by T/2 from the time when the LSB of xn+3 is input to the input terminal 1 shown in FIG. 4b, the delay circuits 13 and 14 , 15 outputs are x
The LSB of n12, xn+, , xn is output. From this point on, during period T/2, xn+2, xn+, . . . Therefore, the address input of the memory of the harmonic circuit 30 is xn 12, x sail, x
n, and in the product-sum circuit 30, yA2)=aoxn+a
, ~+, 10a2 yagura 12 calculations are performed, and the results are outputted for 30 minutes after a delay of T/2 hours. The timing chart in FIG. 4g shows these. As is clear from the figure, the difference between yA Mimoto and YButi is T/2. Further, the delay circuit 16 which receives the output 300 of the multiplication circuit 30 can obtain a delay of T/2. The output 400 of the delay circuit 16 is shown in FIG. 4e.
Therefore, the output of the full adder circuit 40 which receives the output 300 of the diluted sum circuit 30 and the output 400 of the delay circuit 16 is as follows.
yn=yAI)+yA2) and yA3KyApayment-.
are output alternately during a period of T/2.

However, the desired output is that yn=y is also 1) ten ynA2
), so by the control signal Z shown in Fig. 2 i,
By controlling the gate 50, the final output yn can be obtained as shown in FIG. 4i. In this way,
By time-division multiplexing the product-sum circuit, it is possible to significantly reduce the memory capacity.

In the embodiment, only two cases of N=4 and 5 have been described for simplicity, but this does not impose any restrictions on N.

[Brief explanation of drawings]

FIG. 1 shows an example of a digital filter using a conventionally known product-sum circuit.
2 is a delay circuit, 20 is a memory, and 30 is a digit shift adder circuit. FIG. 2 is a diagram showing the timing relationship of the circuit shown in FIG. 1. FIG. 3 shows an embodiment of the digital filter according to the present invention, where N is an odd number. In Figure 3, 11, 12, 14, 15 are 13, 1 of T.
6 is a delay circuit that causes a delay of T/2, 21, 22, 23
30 is a selection circuit, 30 is a product-sum circuit, 40 is a full adder circuit, and 6 gates. FIG. 4 is a diagram showing the timing relationship of the circuits shown in FIGS. 3 and 5. FIG. 5 shows another embodiment of the digital filter according to the present invention, where N is an even number. Hiiragi / Figure Z Figure Figure 3

Claims (1)

[Claims] 1 A plurality of delay circuits that delay a sampled input signal, a predetermined pair of signals from among the input signal and the output signal of the delay circuit are supplied as input, and one of the signal pairs is selected and output. a programmable memory whose input address is the output signal of the selection circuit; an accumulation circuit which accumulates the outputs of the memory; and a delay which delays the output signal of the accumulation circuit. circuit and
A digital filter comprising a full adder circuit which receives the output signal of the delay circuit and the output signal of the accumulation circuit.