JPS6030281A - Signal processor - Google Patents

Abstract

PURPOSE:To obtain a signal processor which performs interlacing easily and has the small possibility of smear generation by driving specific one of horizontal shift registers and distributing its output to plural vertical shift registers. CONSTITUTION:Each horizontal shift register 4 is so constituted as to perform photoelectric conversion by itself and, for example, 525 registers are arranged corresponding to one frame of a TV screen. Further, vertical shift registers 5 have bits at least as many as the horizontal shift registers 4. When a pulse phi1 is inputted to a shift register 8, outputs A-D of the shift register 8 are switched to a high-level signal in order and passed through AND gates 7 to drive horizontal shift registers 4. At this time, odd-numbered lines of the horizontal shift registers are read out in sequence firstly and even-numbered lines are read successively to output one-frame information as a two-field signal, so that a leak of the signal and crosstalk are reduced.

Description

DETAILED DESCRIPTION OF THE INVENTION (Technical Field) The present invention relates to a signal processing device that handles image signals, and particularly to a signal processing device that has an imaging function.

(Prior art) Conventionally, for example, in order to convert one image's worth of image information into two fields' worth of sequential signals, an interline transfer type C was used.
'It was considered to use a CD+MO8 type senna.

However, these sensors had the disadvantage of having transfer paths, gates, etc. within the light-receiving surface, resulting in smaller apertures and lower sensor sensitivity.Also, from the perspective of semiconductor manufacturing technology, high integration is required. This method has the disadvantage that the yield is low because it requires a high resolution, and the number of pixels cannot be increased.

On the other hand, if a frame transfer type COD is used, these drawbacks can be eliminated, but it has been said that the frame transfer type cannot convert one image into a two-field sequential signal. - (Objective) It is an object of the present invention to provide a novel semiconductor imaging device or semiconductor signal processing device and a signal processing apparatus including the same, which can solve the drawbacks of such conventional techniques.

(Example) A The present invention will be described in detail below based on Examples.

1 to 3, 1 is a memory section, 2 is a switch section, and 3 is a drive signal source, and these switch section 2, signal source 3, etc. constitute the control drive means of the present invention. 4
is a CCD type horizontal shift register, 5 is a CCD type vertical shift register, 6 is a charge voltage conversion amplifier (output amplifier) as an output means, 7 is an AND gate, and 8 is a shift register. The shift register 8 may be of a CCD type. LS is an optical system that inputs the image of the object into the memory part l.

In the embodiment shown in FIG. 1, the horizontal shift register 4 itself is configured to perform a photoelectric conversion function, and in the still mode in which only an image is captured, the incidence of the light beam is controlled by the shutter SHT. Further, in FIG. 5, for the sake of simplicity, an example of 4×4 pixels will be used for explanation. For example, 525 registers are arranged corresponding to one frame of the TV screen.

Further, the vertical shift register 5 has at least the number of bits corresponding to the number of horizontal shift registers 4. Note that the shift register may simply be a lead wire.

The shift register 8 sequentially switches and outputs the level signals to the terminals A to D into which the pulse φ is input. father,
When pulse φ8 is input...the irregular signal returns to terminal AK.

Note that φ3 is a nox that drives the register 5, and
φ2A to φ2D are pulses for driving the first to fourth horizontal shift registers 4 counting from the bottom in the figure, respectively. φ is a clock pulse.

The operation of the signal processing device of the present invention configured in this manner will be explained in the third section.
This will be explained using figures.

The first pulse φ8 sets the terminal A of the register 8 to no\repel, thereby selecting the first row, which is an odd number line, and then supplying the pulse φ2^ and the pulse φ3 as shown in FIG. Read out.

Next, by supplying two pulses φ2, the terminal B is brought to a high level to select the third row, and by supplying pulses φ2C+φ, the charges C1 to C4 are read out.

Next, once the register is returned to A by the reset pulse φR, the terminal B is set to high level by supplying one pulse φ1), and the second
Read the line. Then pulse φ.

After supplying two pulses φ201φ, the fourth row is read out.

In this way, the horizontal shift register is selected by the switch circuit 2, and by first sequentially reading out, for example, odd-numbered lines and then sequentially reading out even-numbered lines, it is possible to sequentially output one frame of information as two-field signals, one field at a time. Since the output amplifier is common, the configuration is simplified, and since the path to the common output amplifier 6 in the center is a common charge transfer path, there is less signal leakage and crosstalk.

Note that the timing shown in Figure 3 is used for movie mode, that is, continuous imaging; in still mode, that is, when capturing images for one frame, the shutter SHT is used, and the shutter is opened for a predetermined period of time before reading starts. After that, the shutter is kept closed during the readout period.

In this case, the read operation may be similar to that shown in FIG.

It goes without saying that a ring counter or the like may be used in place of the register in the first illustrated embodiment. (A) Next, FIG. 4 shows a second embodiment of the signal processing device of the present invention. In the figures shown, the same reference numerals as in FIG. 1 indicate the same elements.

Another feature of this embodiment is that a color filter having a plurality of color parts is arranged in the signal processing device, and each color signal component read out from a plurality of horizontal shift registers is distributed to a plurality of transfer paths and read out. At the point.

In the figure, QA-QD are transistors whose gate electrodes are controlled by terminals A to D of the shift register 8, and constitute the AND gate 7 in FIG. 1, respectively. 48 to 4D are horizontal shift registers, each consisting of six pixels in this embodiment. Of course, in reality, for example, 490V
It is desirable that the number of pixels is about 7001 (about
) Color separation stripe filter C consisting of repeating color spectral characteristics of Φy (blue), G@:), and R (red)
8 is placed.

Here, the filters for each color are horizontal shift registers 48 to 4D.
are arranged to match the pitch of each pixel.

5B, 5G, and 5R are vertical shift registers, respectively, and shift registers 5B, 5G, and 5B are shift registers for reading out signals corresponding to the blue filter, green filter, and red filter, respectively.

In addition, each shift register 5B, 5G, 51 (, is driven by a common driving pulse φ, and '1'' is a gate electrical connection, and the gate pulse φ7 collects the charge under the gate electrode during the bias period. , the pulse φd falls, and the charge under this electrode is shifted to the pixel of the register next to the left in the figure.

12] 3,12G.

121 and register 513. This is an amplifier for increasing the output of 5(J, 51(, rlJ).

(C) FIG. 4(B) is a diagram showing an example of the TM and pole configuration of such a signal processing device, and in this embodiment, an example of 1iJ and pole configuration in the case of a one-phase drive system is shown.

The hatched area in the lower right corner of the figure indicates a transparent transfer electrode or gate electrode. Of these, 13 is the horizontal transfer electrode of the horizontal shift register, 14 is the vertical transfer electrode of the vertical shift register, T is between the horizontal shift register and the vertical shift register,
and a gate electrode provided between the vertical shift registers, 1
Reference numeral 6 indicates a channel stop for preventing the movement of charges between the horizontal shift registers 48 to 4D, and 17 indicates a channel stop provided in the vertical shift register. In addition, 18 indicates the range of one pixel. Each transfer electrode and gate electrode is provided to the semiconductor substrate via an insulating layer, and a potential barrier of a predetermined level is formed by KH ion implantation within the semiconductor substrate. . For example, the potential level (hereinafter abbreviated as potential) seen from electrons in the I region under the electrode is always set to be higher than the potential in the ■ region. Further, the potential of the region 111 which is not covered by the electrode is always set high (as compared to the potential of the N region).

Also, this 11. The potential in the IV territory is fixed.

Further, the potential in the I and fJ regions increases and decreases depending on the voltage applied to the transfer electrode. For example, if the substrate is P type and a high level voltage is applied to the transfer electrode, the potential of the I and l regions becomes ■.

It is lower than the potential in the N region, and when a low level is applied, it rises above the potential in the N region.

Therefore, when high-level and low-level pulses are supplied to each transfer electrode, the charges in the substrate are sequentially increased to 1, n, Hl, IL.
1. H-mountain - (moving in the D direction) In the fourth period, the signal processing device of this example was used and 48-4
Only part D is exposed, and the other parts are shielded from light.

In this signal processing device 1, the horizontal shift registers A to D to be read are selected by select pulses φi to φ0 from the switch section 2, respectively.

Further, this switch section 2 receives a clock pulse φ from a drive signal source 3 as a drive means of the present invention.

It is controlled by φ2 and φRV.

Further, pulses -5 and φ are outputted from the drive signal 'm3. In this embodiment as well, the driving means is formed from the switch section and the signal source. 19 is a △ inch circuit, and each vertical shift register 5B.

Signals read from 5G, 5R OUT B, 0I
JTG and OU1'R are sequentially switched at predetermined frequencies and output to the low-pass filter 20 at the subsequent stage. Here, the frequency of the switch circuit 19 corresponds to the filter pitch of the color filter C8. The low-pass filter 20 forms a luminance signal free from aliasing distortion by limiting this high-frequency point-sequential signal to a predetermined band. 21 is a process circuit that performs various corrections (γ correction,
Aperture correction, black level clamp.

Apply white clips, etc.). A low-pass filter having a relatively low cutoff of 22 to 24 orders of magnitude is used to cut off high-frequency components contained in each color signal to prevent moiré.

25 to 27 are r correction circuits which nonlinearly amplify the input/output characteristics of each color signal. 28 to 30 are aperture correction circuits that compensate for contours.

Reference numeral 31 denotes an IJ circuit which forms, for example, a color difference signal and a corrected luminance signal from the luminance signal and each color signal. 32 is an encoder which modulates the color difference signal and the luminance signal to produce a predetermined standard television signal (NTSC, PAL).

Si3CAM#) is formed.

(E) No. 41 is a diagram showing the drive timing of the signal processing device as an image pickup device.

First, φ is inputted at time t1 in synchronization with the vertical synchronizing signal of the standard television signal, and the register 8 is reset.

Therefore, a high level is output from the terminal of the register 80A, the transistor QA is turned on, and the pulse φ is supplied to the horizontal shift register 4A to shift the three pixels of the register 4A to the left in the figure from time t to time t. Also, at this time-
When T is also supplied in the same phase as the pulse φ2, the charge of the pixel Al-A3 becomes the pixel Bl of the vertical shift registers 5B to 51Mo, (
)l, ■lKw is multiplied.

Next, by supplying one pulse of pulse φ at time t4, the charges in each vertical shift register 5B, 5G, and 5R are transferred to t, to t6 via amplifiers 128, 12G, and 12, and are also shifted horizontally by pulse φA, -. Shift register 4A is 3
The charges of pixels 4 to 86 shifted to the left by a pixel amount are transferred to registers 5B and 5G.

Shifted to 5R pixels Bl, Gl, and ELl.

7) These are read out by the pulse φ at a later time "t".

At the same time, two pulses φ are supplied, so the C terminal of the register 8 becomes high level, the transistor Qc is turned on, and the pulse φC is supplied to the horizontal shift register 4C.

Thereafter, three pulses are supplied to the pulse φC1φ1 from time t to time t, thereby increasing the charge force of the pixel C1-03 to the pixel B3. G3. R3 respectively, and the time tto
This charge is read by supplying three pulses to ~t, , K multiplied by φ. Also, by applying the -C1φT K3 pulse again over tIt~t,,K, the pixels C4~C6 become the pixel B3. This charge is read by shifting to G3 and R3 and supplying three pulses of φ from time t14 to ti11. Thereafter, the contents of the horizontal shift register are similarly read out every other line, and the charges of the remaining horizontal lines are sequentially read out in the next field period. In this way, the horizontal shift register 8 is switched and read every horizontal synchronization of the standard television.

Since this embodiment is configured in this way, the structure of the light receiving section can be simplified. Therefore, the aperture ratio is greatly improved, and the chip area is increased by about 3 AKL compared to the conventional frame transfer type. In addition, since interlacing can be easily performed and each color signal can be read out separately, there is little 0 or smear, which greatly simplifies the subsequent signal processing circuit. (F) (4-
Figure 4 □□□, (to) 3rd page. The fourth embodiment is an example in which the horizontal shift register group 4' is used purely as a memory, and a C-type light receiving section 10 is provided separately, and in the latter case, the memory section 10 is provided separately. register group 4 as
For each register ', 7 characters are not required in the vertical transfer mode.

That is, after imaging for a predetermined period of time, the information of the light receiving section is temporarily stored in the memory section 4.
'The following is a diagram showing the third commercial arrangement.In the embodiment shown in the figure, a light receiving element 9 as a photoelectric conversion means is connected to each bit of a horizontal register 4, and registers 4, 5, etc. By opening the gate between each light-shielded light-receiving element 9 and each bit of the register 4 with a pulse φSH, the charge of the light-receiving element 9 is stored in the register 4. In this way, there is no need to use a shutter even in the still mode. That is, by defining the accumulation time based on the supply interval of this pulse φIII, tFIJτ can be determined. In the figure, the same reference numerals as in FIG. 5 indicate the same elements.

In the figure, QCLR is a photodiode 9 as each light receiving element.
This is a clear gate provided between the cathode of the diode 9' and the drain 1) FL.
Discharge to B. QIIHA~Qgun is diode 9'
These are shift gates for shifting the charges accumulated in the horizontal shift registers 48 to 4D, respectively, and pulses φ8HA to φ8D are supplied to the control electrodes of each gate, respectively, and the Noculus φIIIHA to φSHD are used as shift gates. In between, those within diode 9' represent the same element.

In the figure, 34 is a clock generator with a pulse of φ2
A~φ2p@φl1HA~φBHD s φC1,R
Outputs timing pulses for A to φel, RD, etc.

35 is a Drino (- circuit (r)) as a driving means, which forms a driving pulse as shown in FIG. The charge accumulation time at 37 is controlled.

Specifically, this accumulation time control circuit includes a setting means for manually or automatically setting the accumulation time, and the output of this setting means determines the phase relationship between the pulses φCLRA to φCLRD and the pulses φ8HA to φ8HD.
The optical image is incident on the light receiving element 9 or 9' at 37. Also, 33 is a sample and hold circuit for increasing the duty of the output signal from the signal processing device 36.

Also, there are 38 to 40 sample and hold circuits, and from among the point sequential signal outputs via the sample and hold circuit 33, I
(In the timing diagram showing the output pulses for separating each color signal of G and B, the charge of the diode 9' is first shifted to four shift registers during the horizontal blanking period, and then the horizontal shift register 48 performs horizontal scanning. During the period, the pulse φ is driven by two people.

Next, in the same way, the charge of the diode is transferred to the shift register 4B.
After being shifted to , this register 4B is driven.

In this way, the four horizontal shift registers - 4D are driven sequentially in the horizontal scanning period, and the registers 48 - 4D are driven every V vertical periods.

Further, when the time value T is set in the accumulation time control circuit 36, the pulses φCLRA to φCLRD are thereby set.
are output sequentially. Each of these pulses φCLRA to φCL
RD is the time '1'M for each pulse φ2A to φ2D.
Therefore, each light receiving diode 9' is configured so that the output is output at a phase earlier than V-1 in the vertical period V.
The charge accumulated during the period TM) is discharged, and as a result, the accumulation time becomes .

As described above, according to this embodiment, it is possible to obtain a photographing effect similar to that of a focal V-shape shutter consisting of a leading curtain and a trailing curtain in silver halide photography. Moreover, conventional interline type CO
It has the effect of being less likely to cause the besmear phenomenon compared to D and flamm transfer type COD.

(Effects) As explained above, according to the present invention, it is possible to obtain a processing device No. 1'1 which not only can reduce the chip area, but also allows interlacing to be performed extremely easily and has little risk of smearing.

[Brief explanation of drawings]

FIG. 1 is a diagram showing a first embodiment of the essential parts of the signal processing device of the present invention, FIG. 2 is a diagram showing an example of the configuration of the signal processing device of the present invention, and FIG. 3 is a diagram showing the control operation by the control means. 4(A) is a diagram showing the configuration of the second embodiment of the signal processing device of the present invention, and FIG. 4(B) is a timing diagram for explaining the signal processing of FIG. 4(A). A diagram showing an example of a color filter suitable for using the device as an imaging device, FIG. 4(c) I
iA diagram showing the electrode configuration of the main parts of the signal processing device in FIG. 4(A), FIG. 4CD) IiA diagram showing an example of a signal processing circuit when the signal processing device in FIG. 4(A) is used in an imaging device , Figure 4(E)
is the timing diagram of Fig. 4 (D), Fig. 4 (F'), (
G is the third aspect of the present invention. A diagram showing the fourth embodiment, Fig. 5 (
A) is a diagram showing the fifth embodiment of the present invention, FIG.
5(B) is a diagram showing a configuration example of an imaging device using the signal processing device of FIG. 5(B), and FIG. 5(1,) 11 is a timing diagram thereof. l...part of memory, 2...switch section, 3...drive signal source as drive means, 51(, 5G, 513...
・Vertical shift register, 4.4A to 4D...Horizontal shift register, 9...Photodiode as B-C electric conversion means, 6... Charge voltage conversion amplifier as output means. Patent applicant: Canon Co., Ltd. VOUT Aovou7

Claims (2)

[Claims] (1) Drive a plurality of horizontal shift registers, a plurality of vertical shift registers provided for the horizontal shift registers, and a predetermined one of the plurality of horizontal shift registers to output the same to the plurality of vertical shift registers. A signal processing device having a drive means for distributing and supplying. (2) A matrix consisting of rows and columns) A plurality of photoelectric conversion means arranged in an IJ box shape, a plurality of horizontal shift registers that accumulate signals of the photoelectric conversion means of the corresponding row, and signals in the plurality of horizontal shift registers. 1 driving means for sequentially reading and driving l lines at a time; vertical transfer means for vertically transferring signals read out from the horizontal shift register by the driving means;
and a signal processing device comprising output means for outputting the signal transferred by the vertical transfer means.