JPS6024434B2 - electronic clock - Google Patents

Abstract

A time-measuring device having a quartz oscillator (4) as time standard contains, inter alia, two logic circuits (5, 6), one logic circuit (6) receiving signals independent from one another in parallel and relaying the information contained therein as a time-division multiplex signal. The invention is used, in particular, for quicker detection of very slight time deviations. <IMAGE>

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to an electronic timepiece using a variable frequency divider that changes a frequency division ratio for rate adjustment, and particularly to an electronic timepiece that allows easy rate measurement.

The object of the present invention is to externally transmit a logic processing state that determines the frequency division ratio of a variable frequency divider using electromagnetic waves or acoustic signals, including electric field and magnetic field light, which can be received by a suitable measuring device without changing the identification of the normal display state. The purpose of the present invention is to manufacture an electronic clock that facilitates rate measurement by transmitting a signal and has good repairability.

Another object of the present invention is to manufacture an electronic timepiece that facilitates rate measurement and is highly repairable by transmitting a logic state by means of a magnetic field, electromagnetic waves including electric field light, or sound by external operation, or by displaying it on a display device. There is a particular thing.

An example of the configuration of a secondary electronic timepiece is shown in FIG. 1, where 1 is a piezoelectric oscillator, and 2 is a logic circuit, which usually includes a frequency divider and a display drive device.

3 is a display device, which is a member normally driven by an electromagnetic motor;
It consists of a liquid crystal display device driven by an electric field, a light emitting diode, etc., and is also equipped with an acoustic device such as a buzzer or bell.

The display device may display not only the time but also various nominal functions such as calculation results. Such conventional electronic clocks have the following drawbacks. If the periodic characteristics of the piezoelectric oscillator are corrected during the assembling process by using a variable frequency divider circuit and changing the division ratio by changing the state of the logic storage device or logic storage circuit, the output periodic signal may have time irregularities. Because of this, there is a risk that the rate measuring device may be unable to measure or give a false indication.

This phenomenon significantly impairs repairability and hinders the spread of electronic watches using variable frequency dividers. The present invention eliminates such drawbacks, and FIGS. 2 and 3 show block diagrams of examples of its application.

In FIG. 2, 4 is an oscillator, 5 is a logic circuit including a variable divider and frequency division ratio setting means, and 6 is a readout circuit which converts a part of the frequency division ratio setting state of 5 into a time function of current or electric field. , 7 is a display drive circuit, and 8 is a display device.

Here, the additional circuit 6 outputs the frequency division ratio setting state along with the time signal to the display device. In Figure 3, 9 is an oscillator, 10
1 is a logic circuit, 11 is a switch which is an electric switch, and 12 is a readout circuit for converting signals of 10 logical states, which is controlled by the switch 11. 13 is a display drive circuit or a signal generator drive circuit.

14 is a display device or a signal generator, which corresponds to the description of 13 above.

The readout circuit 12 normally supplies a time signal to the display device 14 in accordance with the operation of the switch 11. switch 1 1
When the rate measurement state is set by the operation, the signal representing the frequency division ratio setting state of the logic circuit 10 is converted into a signal suitable for signal generation by the logic circuit 14, and is supplied to the logic circuit 14. FIG. 4 shows a circuit diagram of a specific example of application of the present invention. The operation will be explained below with reference to the figures. 15 is a piezoelectric oscillator.

16 is an inverter with the function of a driving amplifier; 17,1
8 is a phase adjustment resistor and a bias resistor, and 19 is a period adjustment capacitor.

From the above, a Shoden oscillator oscillator like a crystal oscillator is constructed. 20, 21, 22, 23, and 24 are branching devices.

25, 26, 27 for 22, 23, 24 frequency dividers
When the state setting of , that is, the same state as the signal of the storage device, the signals of the extractor circuits 28, 29, and 30 become HIGH signals, and the frequency dividers 22, 23, and 24 are reset by the output of the AND circuit 31. Ru.

The output of the AND circuit 31 simultaneously becomes a frequency-divided output signal and is input to the frequency divider 33. The output period of the AND circuit 31 changes depending on the states of the switches 25, 26, and 27, and as a result, the frequency division ratios of the frequency dividing circuits 25, 26, and 27 change. In this embodiment, switches 25, 26, and 27 serve as frequency division ratio setting means. The output of the splitter 33 passes through 46 OR circuits and 48 display drive circuits and is displayed on 49 display devices. With the above explanation, the watch can be operated as a normal watch except for 46. Additional circuitry for logic reading, including 46, will be explained below.

32, 34 to 45 in FIG. 4 correspond to the readout circuits in FIG. 2, FIG. 6, and FIG. 3, 12.

When the output signal 31 changes from a HIGH state to a LOW state, the frequency dividers 37, 38, and 39 are reset by an inverter 32, a delay circuit 34, an inverter 35, and an AND circuit 36.

The frequency dividers 37, 38, and 39 have structures corresponding to those 22, 23, and 24. As a result, the output mirrors of the screw-or circuits 40, 41, and 42 are outputted from 43. At this time, the frequency dividers 37, 38, and 39 have been reset, so the output of the inverter 44 is 25, 26, and 27.
HIG unless all are set to LOW.
It becomes an H signal. As a result, a relatively fast clock pulse before the frequency divider 21 is inputted to the frequency divider 37 via the AND circuit 45. 37, 38, 39 frequency divider is 25, 2
When the state is the same as the set state of 6, 27, 40, 41
, 42, the output of 43 becomes the mGH state.

The output of 45 becomes LOW through the inverter 44, and is clamped in this state until it is reset again by the signal 31.

Until it is reset and clamped, the output signal 45 is input to the OR circuit 46 and output to the display device via the display drive circuit 48. The number of pulses of this signal obtained as a function of the time of the oscillator is equal to the set count number of 22, 23, and 24, and by measuring this number of pulses with an external measuring device via a display device, the setting state of the minute ratio can be determined. It can be known from the outside. Note that as a display method, depending on the type of display, a state that can be received by the measuring device as a magnetic field, electric field, acoustic signal, or optical signal can be used.
As described above, the present invention allows the frequency division ratio to be known from outside the watch, making it extremely easy to measure the rate of an electronic watch using a variable frequency divider without opening the lid of the case. .

Furthermore, the present invention is extremely effective in a timepiece that changes the frequency division ratio in response to changes in the temperature characteristics of a crystal resonator. FIG. 5 shows an example in which the present invention is applied to an electronic timepiece that performs temperature correction by changing the division ratio according to temperature data. In this application, two pressure force oscillator oscillators are provided and their beat signals are used as temperature signals. 56 and 57 are pressure oscillator oscillators, 59 is a frequency divider, and 58 is 56
, 57, that is, a beat signal circuit that generates a beat signal.

60 is controlled by the outputs of 59 and 58 and outputs a divided signal adjusted according to a predetermined logic to the OR circuit of 66.
A signal is output to the display drive circuit or magnetic field signal generation circuit 7.

61 is a logic state reading circuit for reading out the logic control state of 60, and 37 to 4 in FIG.
Corresponds to 5.

This logic state reading circuit 61 includes 63 electrical switches and 6
2 circuit and 68 appropriate clock pulses.
Perform reading as shown in the figure. With the above configuration, in this embodiment, the frequency division ratio setting state of the logic circuit 60 including the variable frequency divider can be sequentially output in accordance with temperature changes, and the correction state of the electronic timepiece with temperature correction can be easily detected.

Note that this embodiment has a configuration in which it is also possible to detect individual output signals of the oscillators 56 and 57 after reading out the frequency division ratio setting state. That is, after reading out the logic state, 62 controls 64 and 65, and sequentially reads out the cycles of 57 and 56 via the OR circuit 69. During this time, 58 signals are controlled by 701. The periodic signals 56 and 57 are generated by a display device or an electric field, magnetic field, acoustic, or optical signal generator 67.

In this case, it is of course possible to design a dedicated display so that the status can be identified on the display device. As described above, according to the present invention, the frequency division ratio setting state of the variable frequency divider can be outputted to the outside of the watch using the display means, so that rate measurement can be easily performed without opening the hair flap of the case. I can do it.

Further, according to the present invention, there is an advantage that the temperature correction state of an electronic timepiece that performs temperature correction by changing the frequency division ratio depending on the temperature can be easily inspected.

[Brief explanation of the drawing]

FIG. 1 is a block diagram of an example of a subordinate electronic timepiece. FIGS. 2 and 3 are block diagrams of the configuration of the present invention. Fourth
FIG. 5 is a circuit diagram and a block diagram of a specific example of application of the present invention. O-zu spear 2 picture spear 3 picture O 4 Nada spear S prisoner

Claims (1)

[Claims] 1. An oscillation circuit, a variable frequency divider that divides the signal of the oscillation circuit, a display device that displays time based on the output of the variable frequency divider, and a frequency division ratio that sets the frequency division ratio of the variable frequency divider. An electronic timepiece comprising a setting means, comprising a readout circuit that changes the frequency division ratio setting state by the frequency division ratio setting means into a time function signal and outputs the signal, and the output of the readout circuit is supplied to the display device. An electronic clock characterized by: