JPS60236244A - Manufacture of semiconductor device - Google Patents

Abstract

PURPOSE:To simultaneously form narrow and wide separations in a self-aligning manner with the surface in a flat state by selectively etching by thin fluid organic film by the simply step of masking only once. CONSTITUTION:Separating grooves 2, 3 are formed on a p type silicon substrate 1, and a NSG film 4 is accumulated. A silicon nitride thin film 8 is accumulated, and quinone diad resist 6 having fluidity is coated. When the resist film 6 is etched and finished in the state that silicon nitride film 8 is exposed, resist films 6B, 6C remain on the separated portions 2A, 3A. The film 8 is etched with the films 6B, 6C as masks, and removed. The film 4 is etched and selectively removed. The film 8A and the resist 6B are lifted off on the narrow separated portion 2A. The films 8B and 6C on the wide separated portion 3A are removed so that the surface of the substrate 1 becomes completely flat.

Description

DETAILED DESCRIPTION OF THE INVENTION Field of the Invention The present invention relates to a method for manufacturing a semiconductor device, and more particularly to a method for isolating elements of a semiconductor device.

Problems with the structure of the conventional example Conventionally, as a method for isolating elements of a semiconductor device, there is a method of burying an insulator in an isolation trench. An example of the prior art will be explained in FIG. 1 K j , 9. Isolation grooves 2.3 having a depth of about 1 μm are formed on the silicon substrate 1 using photoetching technology (see FIG. 1). Next, by CVD method etc., the thickness is about 1 μm.
An insulator 4 is deposited to a thickness of . At this time, the separation width of the separation groove 2 is approximately 0.5 to 2 μm, and the separation width of the separated separation groove 3 is several tens to several hundreds of μm. The two people are buried almost flat,
The insulator 3AVi of the isolation trench 3 has a step 5 of approximately the same depth as the depth of the isolation trench 3.

Next, a photosensitive resist film 6 for photolithography is applied to a thickness of about 1 μm. At this time, the narrow separation part [registration of two people]・M6Vi becomes almost completely flat. In addition, the resist film 6 on the wide separation part 3A becomes slightly buried and thickened, but the step part 5 remains (
Figure 1C). Next, by a reactive ion etching method, the resist film 6 and the insulating film 4 are simultaneously etched with ions 7 in a plasma atmosphere with an etching gas C3'8 or CHF 3 and 02 at a mixing ratio of about 30:1. Etching is finished when the substrate 1 is exposed (FIG. 3D). At this time, it is possible to bury an insulating film in a relatively narrow isolation region of about 2 to 3 μm in a completely flat state for two people, but it is possible to bury an insulating film in a completely flat state,
It is almost impossible to embed parts of the wide isolation region 3B.

In this way, with conventional embedding separation technology, it is only possible to embed flatly up to a radius of a few μm, and it is impossible to embed a wide area of several 100 μm at the same time in the same process, so a mask process is added. Therefore, it is necessary to embed and separate the narrow region and the wide region separately, which creates an economical problem in manufacturing as the process becomes complicated.

OBJECTS OF THE INVENTION In view of these conventional problems, the present invention provides a method for simultaneously performing both narrow and wide separations in a self-aligned manner without increasing the number of photomask steps. In particular, it has a great effect on isolation between elements in a highly integrated, high-density MO3LSI.

Structure of the Invention In the present invention, after forming isolation grooves with various widths on a semiconductor substrate, a first insulating film is deposited, and a second thin film (for example, silicon nitride, etc.) resistant to fluorine etching is deposited. Form. After that, apply a fluid third organic thin film (for example, a resist film, a glue film, or a polyimide),
The third organic thin film is etched by dry etching, and the process ends when the second thin film is exposed. At this time, it is possible to leave a thin third organic thin film on the separation part J-, and by selectively etching the second thin film using this organic thin film on the separation part as a mask, a self-line is formed only in the separation part J-. The first insulating film is then selectively removed by isotropic etching, leaving the second thin film as a mask. Finally, by removing the third and second thin films on the isolation part, a nearly completely flat surface is obtained, and it is possible to simultaneously insulate and isolate the wide and narrow parts without using a mask. Becomes Noh.

DESCRIPTION OF THE EMBODIMENTS An embodiment of the present invention will now be described in detail with reference to FIG. 2 in connection with the manufacture of an MO3 type integrated circuit. After forming isolation grooves 2 with a width of about 1 μm and isolation grooves 3 with a width of about 100 μm with a depth of about 1 μm on a P-type (1o○) silicon substrate 1 using photoetching technology, an NSG film is formed using an atmospheric pressure CVD method. 4
(non-doped silicate glass) is deposited to a thickness of about 1 μm (FIG. 2A).

At this time, the surface on the narrow separation part 2A is deposited almost flat, but on the wide separation part 3A there is a stepped part 6 equivalent to the depth of the separation groove.
occurs.

Next, a silicon tinide film 8 that is resistant to a hydrogen fluoride-based etching solution is deposited to a thickness of about 0.04 μm using a low-pressure CVD method, and then a quinone diato-based positive resist 6 that has fluidity is deposited. is applied to a thickness of approximately 1 μm (Fig. 2B). At this time, the resist film 6 above the two narrow separation areas is almost completely flattened, and the resist film e above the wide separation area 3A is almost completely flattened.
Aij: Although it does not become flat, it becomes about 20% thicker. This is because the resist film having high viscosity and fluidity has the effect of alleviating the level difference. Next, this resist film 6 is
After heat treatment for 10 minutes at 0'C, the entire surface of the resist film 6 is etched in the 02 plasma atmosphere 9, and when the silicon nitride film 8 is exposed, two narrow separation areas are formed as shown in FIG. 2C. Minimum approximately 0 on top and wide separation section 3A
．． Resist films 6B and 6C remain with a thickness of about 27xm. Note that a thicker resist film 6C remains on the edge portion 3C of the wide separation portion 3A (FIG. 2C).

Next, in a CF4,02 and N2 atmosphere, the silicon tinide film 8 is coated with C, C, and C using the resist films 6B and 6C as masks.
It is selectively removed by DJ (chemical dry etching) (FIG. 2D).

Next, using the resist films 6B and 6C1 and the silicon tinide film 8 and 8B remaining in the separation part as masks, NSCS was applied using an aqueous solution of hydrogen fluoride and ammonium fluoride.
Etch on C and selectively remove. In this case, since the etching occurs isotropically, as shown in FIG. 2, the NSCSC above the two narrow separation areas is almost completely removed, and the silicon nitride film 8A and the resist 6B are lifted off and removed at the same time. . In addition, the vicinity of the edges of the three wide separated parts are removed by isotropic etching to make them nearly flat.

Next, the silicon dioxide film 8B and the resist film 6C on the wide separation part 3A are subjected to 02 rinsing, and then OF 4 i02
By removing C and D in an N2 atmosphere, the surface of the semiconductor substrate 1 becomes almost completely flat, and a narrow isolation region and a wide isolation region can be simultaneously formed in a self-alignment manner without using a mask. It becomes possible to form. Furthermore, instead of the resist film 6, it is also possible to use a fluid material such as silica film or polyimide. The inventors of the present invention have confirmed that it is possible to similarly form a flat embedding separation even when the separation width is about 200 I1 m using the above method.

Effects of the Invention As described above, according to the present invention, not only a narrow separation but also a wide separation can be formed simultaneously with a flat surface using a simple process that requires only one mask process, so that high efficiency can be achieved. It exhibits important value in manufacturing highly integrated LSIs.

[Brief explanation of the drawing]

FIG. 1 (Al-(If)) is a process cross-sectional view of a conventional device isolation method, and FIGS. 2(A) to (F) are cross-sectional views of a device isolation method according to an embodiment of the present invention. 1...Silicon substrate, 2.3...Isolation groove, 4.
...Absolute RpH, 8...Silicon film, 6...Resist film. Name of agent: Patent attorney Toshio Nakao and 1 other person No. 1
Figure 1 Figure 2 Figure 2-

Claims (1)

[Claims] forming a groove for forming insulation isolation on the semiconductor substrate;
depositing a first layer of insulating thin film on the substrate;
a step of depositing a second layer thin film having etching resistance for selectively removing the first layer insulating thin film; a step of applying a third layer organic thin film having fluidity; a step of selectively removing the organic thin film of the second layer while leaving it around the groove and the gap for forming the insulation isolation; a step of selectively removing the second layer thin film using the organic thin film as a mask;
isotropically etching the first insulating thin film using the organic thin film and the second thin film as masks to leave the insulating material flat only in the groove; A method for manufacturing a semiconductor device, comprising the step of removing a thin film consisting of two layers.