JPS60214122A - Frequency converter - Google Patents

Frequency converter

Info

Publication number
JPS60214122A
JPS60214122A JP59070423A JP7042384A JPS60214122A JP S60214122 A JPS60214122 A JP S60214122A JP 59070423 A JP59070423 A JP 59070423A JP 7042384 A JP7042384 A JP 7042384A JP S60214122 A JPS60214122 A JP S60214122A
Authority
JP
Japan
Prior art keywords
circuit
frequency
local oscillation
output
amplifier circuit
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP59070423A
Other languages
Japanese (ja)
Inventor
Hisao Tateishi
立石 久男
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Nippon Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp, Nippon Electric Co Ltd filed Critical NEC Corp
Priority to JP59070423A priority Critical patent/JPS60214122A/en
Publication of JPS60214122A publication Critical patent/JPS60214122A/en
Pending legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H04ELECTRIC COMMUNICATION TECHNIQUE
    • H04BTRANSMISSION
    • H04B15/00Suppression or limitation of noise or interference
    • H04B15/02Reducing interference from electric apparatus by means located at or near the interfering apparatus
    • H04B15/04Reducing interference from electric apparatus by means located at or near the interfering apparatus the interference being caused by substantially sinusoidal oscillations, e.g. in a receiver or in a tape-recorder
    • H04B15/06Reducing interference from electric apparatus by means located at or near the interfering apparatus the interference being caused by substantially sinusoidal oscillations, e.g. in a receiver or in a tape-recorder by local oscillators of receivers

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Networks & Wireless Communication (AREA)
  • Signal Processing (AREA)
  • Picture Signal Circuits (AREA)
  • Structure Of Receivers (AREA)
  • Superheterodyne Receivers (AREA)
  • Noise Elimination (AREA)

Abstract

PURPOSE:To reduce radiation and parasitic spurious radiation of a local oscillating frequency by forming a frequency converting circuit, a local oscillation circuit, an amplifier circuit and a frequency divider circuit on a monolithic substrate. CONSTITUTION:The frequency converting circuit 3, an IF amplifier circuit 5, the local oscillating circuit 7, the local amplifier circuit 8' and the frequency divider circuit 9 are formed on a monolithic substrate. After an output of the local oscillating circuit 7 is amplified by the amplifier circuit 8', the signal is fed respectively to the converting circuit 3 and the frequency divider circuit 9. Thus, the external radiation of the local oscillation frequency is reduced remarkably. Further, a common point between the converting circuit 3 and the amplifier circuit 5, a common point between the oscillating circuit 7 and the amplifier circuit 8' and a common point of the frequency divider circuit 9 are connected electrically and they are separated from the standpoint of layout. Thus, the parasitic spurious radiation in one monolithic chip is reduced.

Description

【発明の詳細な説明】 この発明は、周波数変換装置に関し、特にテレビジ璽ン
受像機の周波数変換装置に関する。
DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a frequency conversion device, and particularly to a frequency conversion device for a television receiver.

〔従来技術〕[Prior art]

従来の標準型のテレビジョン受像機の周波数変換装置は
、例えば第1図に示すように、所望の放送信号をアンテ
ナ1で受信し、高周波増幅回路2で増幅し、周波数変換
回路3で局部発振回路7の発振信号と、前記増幅回路2
の出力を理容して中間周波数信号に変換し、所定帯域内
のみを通過させる中間周波数−波回路4t−介し、直接
あるいは1膜種度の中間周波数増幅回路5t−介して、
中間周波数出力端子6に、その中間周波数信号を出力す
る。
For example, as shown in FIG. 1, a conventional standard frequency conversion device for a television receiver receives a desired broadcast signal with an antenna 1, amplifies it with a high frequency amplification circuit 2, and converts it to local oscillation with a frequency conversion circuit 3. The oscillation signal of the circuit 7 and the amplifier circuit 2
directly or via an intermediate frequency amplification circuit 5t, which converts the output into an intermediate frequency signal and passes only within a predetermined band.
The intermediate frequency signal is output to the intermediate frequency output terminal 6.

さらに1蛭斬デジタルチユーニングシステム(DTS 
)の技術を用いて、局部発振回路7の出力を、局部発振
周波数増幅回路8を介し、周波数分周回路9に入力して
その周波数を分周したあと、PLL回路10に入力し、
その内部でさらに可変分周したものと、内部の基準発振
周波数との差に応じた直流電圧を局部発振回路7に帰還
することにより、発振周波数を安定化する。
In addition, Hiruzan Digital Tuning System (DTS)
), the output of the local oscillation circuit 7 is input to the frequency divider circuit 9 via the local oscillation frequency amplification circuit 8 to divide the frequency, and then input to the PLL circuit 10.
The oscillation frequency is stabilized by feeding back to the local oscillation circuit 7 a DC voltage corresponding to the difference between the internally further variably divided frequency and the internal reference oscillation frequency.

、 上記の各回路を、モノリシ、りな集積回路チップ(
すなわち、複数個の能動素子と関連回路要素とが、ひと
つの共通基板上に、同時く形成され、相互に接続された
ソリッドステート)とするのが有利なことが認められて
い°る。
, Each of the above circuits can be integrated into a monolithic or linear integrated circuit chip (
That is, it has been found advantageous to have a plurality of active devices and associated circuitry formed simultaneously on a common substrate and interconnected (solid-state).

例えば、このモノリシックな構成技術の利用によって、
分離された素子や関連要素を用いる従来の回路構成に比
べ、大きさ、重さおよび信頼性的に於き、多くの利益が
得られ、また、価格的にも比較的安価に構成できる。
For example, by using this monolithic construction technology,
Compared to conventional circuit configurations using separate components and related components, many advantages are achieved in size, weight, and reliability, and the circuit configuration is relatively inexpensive.

このようなテレビジョン受像機の周波数変換装置の集積
回路化はむずかしく、実用化されていなかった。DTS
システムを構成するための周波数分周回路9及びPLL
回路10は集積回路化されているが、その他の回路2.
7.4.5.8は個別の半導体で構成されている。この
従来の装置の欠点は、局部発振回路7の出力を周波数変
換回路3と、局部発振増幅回路8を介して周波数分周回
路9へ配分する必要があシ、安定した発振を行うために
は充分外電力を与えてやる必要があることである。特に
プリント基板上の配線を介してこれらを接続するため、
パッケージのビン間におる容量及びパッケージのピン間
を接続するリード線の持つ容量とインダクタンスなどの
要素に対して安定な発振及び発振電圧レベルを保証する
ために、各ICの入出力部の回路構成に十分な配慮が必
要である。例えば、出力回路では、バイアス電流を充分
大きな値にしたり、各IC間の配置を最短にしたシする
ことが2要である。また、不要輻射の配慮のために、例
えば局部発振回路7と周波数変換回路3を銅板を用いシ
ールド効果を持たせるなどの注意が必要だった。
It is difficult to integrate the frequency converter of such a television receiver into an integrated circuit, and it has not been put to practical use. DTS
Frequency divider circuit 9 and PLL for configuring the system
Although the circuit 10 is an integrated circuit, other circuits 2.
7.4.5.8 consists of individual semiconductors. The disadvantage of this conventional device is that it is necessary to distribute the output of the local oscillation circuit 7 to the frequency division circuit 9 via the frequency conversion circuit 3 and the local oscillation amplifier circuit 8, which is necessary for stable oscillation. It is necessary to provide sufficient external power. Especially since these are connected via wiring on the printed circuit board,
In order to guarantee stable oscillation and oscillation voltage level with respect to factors such as the capacitance between the package bins and the capacitance and inductance of the lead wires connecting between the package pins, the circuit configuration of the input/output section of each IC is sufficient consideration is required. For example, in the output circuit, it is necessary to set the bias current to a sufficiently large value and to minimize the distance between the ICs. Further, in order to prevent unnecessary radiation, it was necessary to take precautions such as using copper plates for the local oscillation circuit 7 and the frequency conversion circuit 3 to provide a shielding effect.

テレビジョン受像機の周波数変換装置全体の集積回路化
が、従来、技術的に不可能であると考えられていた理由
は、 1)900MHz帯の信号を処理するために、トランジ
スタの動作時のfTを最大にするために、バイアス電流
を5〜10mA必要とし、集積化した場合には、消費電
力がモールドパッケージの許容値を越えてしまうこと、 2)また、集積化した場合に、線素子数が500素子前
後となシ、10〜12μm2のエミッタサイズのトラン
ジスタではチップ寸法が増大すること、 3)雑音指数上1周波数変換回路及び中間周波数増幅回
路は、7〜10 dBの雑音指数が要求されるのに対し
て、周波数分周回路は雑音指数的な設計思想はなく、デ
ジタル的に高速スウィッチングすることが要求され、同
種の製造方法が採用できないこと、 4)また、周波数分周回路の分周された周波数信号が、
接地ライン及び電源ラインを介して周波数変換回路に影
響を与え、寄生スプリアスを発生することである。
The reasons why it was previously thought that it was technically impossible to integrate the entire frequency conversion device of a television receiver into an integrated circuit were as follows: 1) In order to process signals in the 900 MHz band, fT during operation of transistors In order to maximize 3) In terms of noise figure, frequency conversion circuits and intermediate frequency amplification circuits are required to have a noise figure of 7 to 10 dB. On the other hand, frequency divider circuits do not have a noise figure design concept and require high-speed digital switching, so the same manufacturing method cannot be used. The divided frequency signal is
This is because it affects the frequency conversion circuit through the ground line and power supply line, and generates parasitic spurious signals.

しかし、最近、トランジスタ製造技術の向上によシ、低
バイアス電流(1〜3mA)で、動作時のfrt最大に
できる様になり、また、微細加工技術の向上により、エ
ミッタ・サイズを1〜3μm2まで微細化できる様にな
り、さらに、トランジスタのベースひろがシ抵抗の低減
等により、高速スイッチングで雑音指数の低く、かつ集
積度の高い製造技術が確立して来ている。
However, with recent improvements in transistor manufacturing technology, it has become possible to maximize frt during operation with a low bias current (1 to 3 mA), and improvements in microfabrication technology have made it possible to increase the emitter size to 1 to 3 μm2. Furthermore, due to reductions in transistor base width resistance, manufacturing technology with high-speed switching, low noise figure, and high degree of integration has been established.

〔発明の目的〕[Purpose of the invention]

本発明の目的は、上記の高度な製造技術を背景にして、
従来の問題である、局部発振周波数の輻射及び周波数分
周回路の分周された周波数信号が周波数変換回路に影響
を与え寄生スプリアスを発生することを解消し、安定な
機能を有する周波数変換装置を提供することにある。
The purpose of the present invention is to solve the following problems based on the above advanced manufacturing technology:
We have solved the conventional problems of local oscillation frequency radiation and the frequency divided frequency signal of the frequency divider circuit affecting the frequency conversion circuit and generating parasitic spurious, and created a frequency conversion device with stable functions. It is about providing.

〔発明の構成〕[Structure of the invention]

本発明の周波数変換装置は、局部発振回路と、この出力
を増幅する2出力の増幅回路と、この増幅回路の出力の
一方によって、入力される高周波信号を中間周波信号に
変換する周波数変換回路と、前記増幅回路の出力の他方
を分周する分周回路と、この出力が所定周波数にロック
するように前記局部発振回路の周波数を制御する制御回
路とt有し、前記周波数変換回路1局部発振回路、増幅
回路。
The frequency conversion device of the present invention includes a local oscillation circuit, a two-output amplifier circuit that amplifies the output of the local oscillation circuit, and a frequency conversion circuit that converts an input high frequency signal into an intermediate frequency signal using one of the outputs of the amplifier circuit. , a frequency dividing circuit that frequency divides the other output of the amplifier circuit, and a control circuit that controls the frequency of the local oscillation circuit so that the output is locked to a predetermined frequency, and the frequency conversion circuit 1 has a local oscillation circuit. circuit, amplifier circuit.

分周回路を同一モノリシック上に構成したことを特徴と
する。
A feature is that the frequency dividing circuits are constructed on the same monolithic board.

〔実施例〕 第2図は、本発明の実施例を示すもので、破線内の回路
、つまり、周波数変換回路3.中間周波数増幅回路52
局部発振回路7.1局部発振周波数増幅回路8′2周波
数分周回路9vi−1同一のモノリシックな集積回路チ
ップ上に製造しである。局部発振回路7から、直流的あ
るいは交流的に局部発振周波数増幅回路8′に入力され
、同増幅回路8′で増幅された信号は、周波数変換回路
3と周波数分周回路9に各々入力される。このことによ
シ従来の構成に比べて、一度、パッケージの外部に出る
ことなく、ハラケージ内部で伝達されるために、局部発
振周波数の外部への輻射が大幅に低減でき、また従来各
回路のス出力部でパッケージのピン間に存在する容量や
、プリント基板上の配線の持つ容量及びインダクタンス
等の寄生要素を考慮していた部分がなくなシ局部発振回
路7の負荷が軽くなる。このため局部発振回路7の電力
を小さくすることができる。
[Embodiment] FIG. 2 shows an embodiment of the present invention, in which the circuit within the broken line, that is, the frequency conversion circuit 3. Intermediate frequency amplifier circuit 52
Local oscillator circuit 7.1 Local oscillation frequency amplifier circuit 8'2 Frequency divider circuit 9vi-1 are fabricated on the same monolithic integrated circuit chip. The local oscillation circuit 7 inputs DC or AC signals to the local oscillation frequency amplification circuit 8', and the signals amplified by the amplification circuit 8' are input to the frequency conversion circuit 3 and the frequency division circuit 9, respectively. . As a result, compared to the conventional configuration, the local oscillation frequency is transmitted inside the Hara cage without going outside the package, which greatly reduces the radiation of the local oscillation frequency to the outside. The load on the local oscillation circuit 7 is reduced by eliminating the need to consider parasitic elements such as the capacitance existing between the pins of the package, and the capacitance and inductance of the wiring on the printed circuit board in the output section. Therefore, the power of the local oscillation circuit 7 can be reduced.

また、周波数分周回路9の分周された周波数信号により
、周波数変換回路3で寄生スプリアスが発生することを
なくすために、周波数分周回路9で、スイッチングする
トランジスタを、差動増幅器を用いて導通、非導通する
トランジスタヲAC的に対称動作を行なう回路構成にす
ることによシ、電源ライン、接地ラインからの影響を押
さえるとともに、第3図に示す様に1周波数変換回路3
に対して、前記差動増幅器を構成する対のトランジスタ
12を、構造上、変流的に対称動作する配置にし、さら
に、周波数変換回路3と中間周波数増幅回路5の接地点
と、局部発振回路7と局部発振周波数増幅回路8′の接
地点と、周波数分周回路9の接地点とを電気的には接続
し、レイアウト上分離することによシ、同一モノリシッ
クなチップ内での寄生スプリアスを低減することができ
る。
In addition, in order to prevent parasitic spurious from occurring in the frequency conversion circuit 3 due to the frequency signal divided by the frequency division circuit 9, the switching transistors in the frequency division circuit 9 are replaced by differential amplifiers. By configuring the circuit configuration in which conductive and non-conductive transistors operate symmetrically in AC terms, the influence from the power supply line and the ground line can be suppressed, and as shown in FIG.
In contrast, the pair of transistors 12 constituting the differential amplifier are structurally arranged to operate symmetrically in terms of current transformation. 7, the ground point of the local oscillation frequency amplifier circuit 8', and the ground point of the frequency divider circuit 9 are electrically connected and separated in terms of layout, thereby reducing parasitic spurious within the same monolithic chip. can be reduced.

第2図の各回路を同一モノリシックなチップ上に構成し
た配置図を第4図に示す。アンテナ及び高周波増幅回路
を介した受信信号は、端子P2よシ、周波数変換回路3
に入力され、局部発振回路7の発振周波数を、前記周波
数変換回路3に入力することKよシ、端子P14.P1
5に周波数変換された中間周波数信号が出力され、その
出力は1.“戸波回路4を介し、端子P13よシ中間周
波数増幅回路5に入力され、増幅された信号を端子P1
2に出力する。一方、前記局部発振回路7の発振周波数
は、端子P4 、 P5 、 P6に接続される回路構
成で決定され、その発振周波数は、局部発振周波数増幅
回路8′で増幅され、その出力は、周波数分周回路9に
入力され、周波数を分周された信号を端子P10に出力
するもので、端子P3.P7.P16は、夫々前記周波
数変換回路3.前記局部発振周波数増幅回路8′及び前
記中間周波数増幅回路5のコンデンサーを介してAC的
に接地されたバイパス端子で、端子P1は、前記周波数
変換回路と前記中間周波数増幅回路の接地端子で、端子
P8は前記局部発振回路7と前記局部発振周波数増幅回
路8′の接地端子で、端子pHは前記周波数分周回路9
の接地端子であり、端子P9は電源端子である。
FIG. 4 shows a layout diagram in which each circuit in FIG. 2 is constructed on the same monolithic chip. The received signal via the antenna and the high frequency amplification circuit is sent to the terminal P2 and the frequency conversion circuit 3.
In order to input the oscillation frequency of the local oscillation circuit 7 to the frequency conversion circuit 3, the terminal P14. P1
The intermediate frequency signal frequency-converted to 1.5 is output, and the output is 1.5. “The signal is input to the intermediate frequency amplification circuit 5 from the terminal P13 via the Tonami circuit 4, and the amplified signal is sent to the terminal P1.
Output to 2. On the other hand, the oscillation frequency of the local oscillation circuit 7 is determined by the circuit configuration connected to the terminals P4, P5, and P6, and the oscillation frequency is amplified by the local oscillation frequency amplification circuit 8', and its output is divided by the frequency. A signal inputted to the frequency circuit 9 and having its frequency divided is outputted to the terminal P10, and the terminals P3. P7. P16 are the frequency conversion circuits 3. The terminal P1 is a bypass terminal grounded in an AC manner through the capacitors of the local oscillation frequency amplification circuit 8' and the intermediate frequency amplification circuit 5, and the terminal P1 is a ground terminal of the frequency conversion circuit and the intermediate frequency amplification circuit. P8 is the ground terminal of the local oscillation circuit 7 and the local oscillation frequency amplification circuit 8', and terminal pH is the ground terminal of the frequency divider circuit 9.
The terminal P9 is the ground terminal of the terminal P9, and the terminal P9 is the power supply terminal.

〔発明の効果〕〔Effect of the invention〕

以上のことにより、本発明によれば、局部発振周波数の
不要輻射がなく、寄生スプリアスの発生もなく、周波数
特性のすぐれた周波数変換装置を、経済的に安価に実現
することが可能である。
As described above, according to the present invention, it is possible to realize economically and inexpensively a frequency conversion device that does not cause unnecessary radiation of the local oscillation frequency, does not generate parasitic spurious, and has excellent frequency characteristics.

【図面の簡単な説明】[Brief explanation of the drawing]

第1図は従来例を示すブロック図、第2図は本発明の実
施例を示すブロック図、第3図は第2図中の周波数分周
回路の配置図、第4図は第2図の配置例を示す配置図で
ある。 1・・・・・・アンテナ、2・・・・・・高周波増幅回
路、3・・・・・・周波数変換回路、4・・・・・・ろ
波回路、5・・・・・・前置中間周波数増幅回路、6・
・・・・・中間周波数出力端子、7・・・・・・局部発
振回路、8.8’、12 ・・・・・・局発増幅回路、
9・・・・・・周波数分周回路、10・・・・・・PL
L回路。 結4凶
Fig. 1 is a block diagram showing a conventional example, Fig. 2 is a block diagram showing an embodiment of the present invention, Fig. 3 is a layout diagram of the frequency dividing circuit in Fig. 2, and Fig. 4 is a block diagram showing an embodiment of the present invention. It is a layout diagram showing an example of layout. 1... Antenna, 2... High frequency amplification circuit, 3... Frequency conversion circuit, 4... Filter circuit, 5... Front intermediate frequency amplification circuit, 6.
...Intermediate frequency output terminal, 7...Local oscillation circuit, 8.8', 12...Local oscillation amplifier circuit,
9...Frequency divider circuit, 10...PL
L circuit. Kyu 4 kyou

Claims (1)

【特許請求の範囲】[Claims] 局部発振回路と、この出力を増幅する2出力の増幅回路
と、この増幅回路の出力の一方によって、入力される高
周波信号を中間周波信号に変換する周波数変換回路と、
前記増幅回路の出力の他方を分周する分周回路と、この
出力が所定周波数にロックするように前記局部発振回路
の周波数を制御する制御回路とを有し、前記周波数変換
回路1局部発振回路、増幅回路2分周回路を同一モノリ
シック上に構成したことを特徴とする周波数変換装置。
a local oscillation circuit, a two-output amplifier circuit that amplifies the output, and a frequency conversion circuit that converts an input high frequency signal into an intermediate frequency signal using one of the outputs of the amplifier circuit;
The frequency conversion circuit 1 has a frequency dividing circuit that divides the frequency of the other output of the amplifier circuit, and a control circuit that controls the frequency of the local oscillation circuit so that the output is locked to a predetermined frequency. A frequency conversion device characterized in that an amplifier circuit and a divide-by-2 circuit are constructed on the same monolithic board.
JP59070423A 1984-04-09 1984-04-09 Frequency converter Pending JPS60214122A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP59070423A JPS60214122A (en) 1984-04-09 1984-04-09 Frequency converter

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP59070423A JPS60214122A (en) 1984-04-09 1984-04-09 Frequency converter

Publications (1)

Publication Number Publication Date
JPS60214122A true JPS60214122A (en) 1985-10-26

Family

ID=13431049

Family Applications (1)

Application Number Title Priority Date Filing Date
JP59070423A Pending JPS60214122A (en) 1984-04-09 1984-04-09 Frequency converter

Country Status (1)

Country Link
JP (1) JPS60214122A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH02170627A (en) * 1988-12-23 1990-07-02 Hitachi Ltd Receiver made into ic

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH02170627A (en) * 1988-12-23 1990-07-02 Hitachi Ltd Receiver made into ic
JP2659573B2 (en) * 1988-12-23 1997-09-30 株式会社日立製作所 IC receiver

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