JPS6016175A - Digital controller of controlled rectifier - Google Patents

Digital controller of controlled rectifier

Info

Publication number
JPS6016175A
JPS6016175A JP12236183A JP12236183A JPS6016175A JP S6016175 A JPS6016175 A JP S6016175A JP 12236183 A JP12236183 A JP 12236183A JP 12236183 A JP12236183 A JP 12236183A JP S6016175 A JPS6016175 A JP S6016175A
Authority
JP
Japan
Prior art keywords
frequency
control
pulse
signal
phase angle
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP12236183A
Other languages
Japanese (ja)
Inventor
Teruyoshi Shimizu
清水 照喜
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Toshiba Corp
Original Assignee
Toshiba Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Toshiba Corp filed Critical Toshiba Corp
Priority to JP12236183A priority Critical patent/JPS6016175A/en
Publication of JPS6016175A publication Critical patent/JPS6016175A/en
Pending legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H02GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02MAPPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
    • H02M7/00Conversion of ac power input into dc power output; Conversion of dc power input into ac power output
    • H02M7/02Conversion of ac power input into dc power output without possibility of reversal
    • H02M7/04Conversion of ac power input into dc power output without possibility of reversal by static converters
    • H02M7/12Conversion of ac power input into dc power output without possibility of reversal by static converters using discharge tubes with control electrode or semiconductor devices with control electrode
    • H02M7/145Conversion of ac power input into dc power output without possibility of reversal by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a thyratron or thyristor type requiring extinguishing means
    • H02M7/155Conversion of ac power input into dc power output without possibility of reversal by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a thyratron or thyristor type requiring extinguishing means using semiconductor devices only

Landscapes

  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Rectifiers (AREA)
  • Power Conversion In General (AREA)

Abstract

PURPOSE:To prevent commutation failure caused by variations in frequency by detecting the variation in the power source frequency and correcting the control phase angle. CONSTITUTION:A frequency detector 11 which inputs a reference pulse theta0 from a zero cross detector 10 and outputs a frequency detection signal (f) is provided, and a pulse generator 8A has an input terminal for reading out the signal (f) as a correction signal. The detector 11 has a clock pulse generator for generating a pulse at every prescribed period and a counter for counting the pulse during a period of the pulse theta0, and outputs the counted value of the counter as the signal (f). Accordingly, when the frequency of the power source is small, the counted value (f) of the counter is large, and when the frequency is high, the counted value (f) is, on the contrary, small, and the generator 8A performs the correcting operation so that the value (f) becomes zero correction in case of rated frequency f0.

Description

【発明の詳細な説明】 〔発明の技術分野〕 本発明はディジタル制御装置に係り、特に制御整流器の
制御タイミングをディジタル制御で行う際に電源周波数
の変動による制御位相角の変動を補正する様に構成した
制御整流器のディジタル制御装置に関する。
[Detailed Description of the Invention] [Technical Field of the Invention] The present invention relates to a digital control device, and particularly to a digital control device that corrects fluctuations in a control phase angle due to fluctuations in power supply frequency when controlling the control timing of a control rectifier by digital control. The present invention relates to a digital control device for a controlled rectifier.

〔発明の技術的背景とその問題点〕[Technical background of the invention and its problems]

従来の制御整流器のディジタル制御装置による電流制御
の例を第1図のブロック図に示す。
An example of current control by a conventional digital control device for a controlled rectifier is shown in the block diagram of FIG.

交流電源lから電力全供給された制御整流器2は、交流
電圧を直流電圧に変換して負荷3に電流を流す。この電
流は電流検出回路5で検出され電流の平均値に比例した
値の電流検出信号をディジタル値で出力して電流制御回
路6に入力される。
The control rectifier 2, which is fully supplied with electric power from the AC power source 1, converts the AC voltage into a DC voltage and causes the current to flow through the load 3. This current is detected by a current detection circuit 5, and a current detection signal having a value proportional to the average value of the current is output as a digital value and inputted to a current control circuit 6.

この電流検出信号は電流制御回路6により電流基準回路
4からディジタル値で入力された電流基準信号と比較さ
れ差分比例積分演算されたディジタル値の位相制御回路
又として出力される。この位相制御信号Xは関数回路7
に人力され―−1xに変換されディジタル値の制御位相
角信号θとして出力されパルス発生回路8に入力される
This current detection signal is compared with the current reference signal input as a digital value from the current reference circuit 4 by the current control circuit 6, and outputted as a phase control circuit or a digital value obtained by differential proportional integral calculation. This phase control signal
The control phase angle signal .theta. is inputted manually, converted to -1x, outputted as a digital value control phase angle signal .theta., and inputted to the pulse generation circuit 8.

一方、パルス発生回路8には交流電源1の電圧極性が反
転する毎に零クロス検出回路10から発生する基準パル
スθ0が入力され、電源電圧が制御位相角信号θに対応
した位相角となったとき制御パルスCを発生してパルス
増幅回路9に入力する。
On the other hand, the reference pulse θ0 generated from the zero cross detection circuit 10 is input to the pulse generation circuit 8 every time the voltage polarity of the AC power supply 1 is reversed, and the power supply voltage has a phase angle corresponding to the control phase angle signal θ. At this time, a control pulse C is generated and input to the pulse amplification circuit 9.

パルス増幅回路9は制御パルスCにより制御整流器2を
構成する各制御整流素子2人の導通非導通を制御するゲ
ート信号GPを出力し負荷3に流れる電流を電流基準信
号に対応した値に制御している。
The pulse amplification circuit 9 uses the control pulse C to output a gate signal GP that controls the conduction and non-conduction of each of the two control rectifier elements constituting the control rectifier 2, and controls the current flowing through the load 3 to a value corresponding to the current reference signal. ing.

パルス発生回路8は図示1〜ない高周波の一定周期のク
ロックパルスを発生するクロックパルス発生回路と、そ
のクロックパルスを計数して周期τ!でチェックパルス
CPを発生する分周回路と、基準ハルスθoヲ検知した
後のチェックパルスCPの数が位相制御信号θに対応し
たパルス数になったとき制御パルスcf発生する制御パ
ルス発生回路を内部に備え、位相制御信号θのインクリ
メントは電源周波数が定格周波数foのときの周期τ1
に対応した増分位相角として与えられる。
The pulse generation circuit 8 includes a clock pulse generation circuit that generates high-frequency clock pulses with a constant period (not shown), and counts the clock pulses to obtain a period τ! A frequency divider circuit that generates a check pulse CP at In preparation for this, the increment of the phase control signal θ is equal to the period τ1 when the power supply frequency is the rated frequency fo.
is given as the incremental phase angle corresponding to .

従って、定格周波数foの増分位相角(周期で1)単位
で与えられた制御位相角信号θに対応した電源電圧e1
の制御位相角は、第2図のタイムチャートに示した様に
電源電圧esの極性が反転した時刻t1から制御位相角
信号θで与え″られた数のチェックパルスCPが発生し
た時刻t2、即ち、tlからτ2経過後の位相角となる
Therefore, the power supply voltage e1 corresponding to the control phase angle signal θ given in units of incremental phase angle (1 in period) of the rated frequency fo
As shown in the time chart of FIG. 2, the control phase angle of is determined from time t1 when the polarity of the power supply voltage es is reversed to time t2 when the number of check pulses CP given by the control phase angle signal θ is generated, i.e. , tl is the phase angle after τ2 has elapsed.

しかしながら、上述構成の従来のディジタル制御装置で
は、電源の周波数が定格周波数がfoからずれると制御
位相角もずれてくる。例えば第2図の電源電圧e、′に
示す様に電源周波数が低下してflになると位相角に対
する時間が増加するが制御位相角信号θによる制御時間
τ2は定格周波数f、の場合と変らず制御位相角はf1
/ foだけ少なくなり誤差を生じてくる。この制御誤
差は制御ゲインの変化となって表れると共に電流制御回
路6の内部に有する図示しない制御位相角制限値(αリ
ミット、βリミット)に無視できない誤差を生じさせ転
流失敗を引き起す問題点となって表れる。
However, in the conventional digital control device having the above configuration, when the frequency of the power source deviates from the rated frequency fo, the control phase angle also deviates. For example, as shown in the power supply voltage e,' in Fig. 2, when the power supply frequency decreases to fl, the time for the phase angle increases, but the control time τ2 by the control phase angle signal θ remains the same as in the case of the rated frequency f. The control phase angle is f1
/fo decreases, causing an error. This control error appears as a change in control gain, and also causes a non-negligible error in the control phase angle limit values (α limit, β limit, not shown) inside the current control circuit 6, causing a commutation failure. It appears as

〔発明の目的〕[Purpose of the invention]

本発明は上述問題点を除去するために外されたもので、
電源周波数の変動を検出して制御位相角を補正し、電源
周波数が変動しても位相制御信号による制御位相角の誤
差が大きくならない様にして信頼性の向上した制御整流
器のディジタル制御装置を提供するのが目的である。
The present invention has been removed in order to eliminate the above-mentioned problems,
Provides a digital control device for a controlled rectifier that detects fluctuations in the power supply frequency and corrects the control phase angle to prevent the error in the control phase angle caused by the phase control signal from increasing even when the power supply frequency fluctuates, improving reliability. The purpose is to.

〔発明の概要〕[Summary of the invention]

本発明は上記目的を達成するために交流電源から電力が
供給され負荷に電力を供給する制御整流器と、前記交流
電源の電圧極性が反転する毎に基準パルスを発生する零
クロス検出回路と、ディジタル値の制御位相角信号と前
記基準パルスが入力され前記制御位相角信号に対応した
電圧位相で前記制御整流器を位相制御する位相制御回路
を具備した制御整流器のディジタル制御装置に於て、所
定の周期でチェックパルスを発生するチェックパルス発
生手段と、前記基準パルスで定まる所定のタイミングで
前記制御位相角信号で定まる値が初期設定され前記チェ
ックパルスを前記初期設定のパルス数だけ計数したとき
制御位相角タイミング信号を出力するチェックパルス計
数手段と、前記交流電源の周波数に対応したディジタル
値の周波数検出信号を検知する周波数検出手段と、前記
周波数検出信号により前記制御位相角タイミング信号を
補正する周波数補正手段を設は電源周波数が変動しても
前記制御位相角信号に応じた正確な制御位相角で前記制
御整流器を制御することが可能となり信頼性の向上した
制御整流器のディジタル制御装置である。
In order to achieve the above object, the present invention includes a controlled rectifier that is supplied with power from an AC power source and supplies power to a load, a zero-cross detection circuit that generates a reference pulse every time the voltage polarity of the AC power source is reversed, and a digital rectifier that supplies power to a load. In a digital control device for a controlled rectifier, the digital control device for a controlled rectifier includes a phase control circuit that receives a controlled phase angle signal of a value and the reference pulse and controls the phase of the controlled rectifier with a voltage phase corresponding to the controlled phase angle signal. a check pulse generating means for generating a check pulse at a predetermined timing determined by the reference pulse; and a value determined by the control phase angle signal is initially set at a predetermined timing determined by the reference pulse, and when the check pulse is counted by the initially set number of pulses, the control phase angle is determined. check pulse counting means for outputting a timing signal; frequency detection means for detecting a frequency detection signal of a digital value corresponding to the frequency of the AC power source; and frequency correction means for correcting the control phase angle timing signal using the frequency detection signal. This is a digital control device for a controlled rectifier that can control the controlled rectifier with an accurate control phase angle according to the controlled phase angle signal even if the power supply frequency fluctuates, and has improved reliability.

〔発明の実施例〕[Embodiments of the invention]

本発明の制御整流器のディジタル制御装置を第3図のブ
ロック図に示す一実施例を用いて説明する。同図に示し
た各要素の符号に於て第1図と同じ符号はその機能も同
じであることを示す。
A digital control device for a controlled rectifier according to the present invention will be explained using an embodiment shown in the block diagram of FIG. The same reference numerals as in FIG. 1 indicate that the functions of the elements are the same.

第3図の実施例では零クロス検出回路10からの基準パ
ルスθof入力して周波数検出信号fを出力する周波数
検出回路11が新に設けられ、パルス発生回路8Aには
この検出信号ff:補正信号として読込む入力端子が新
に設けられている。
In the embodiment shown in FIG. 3, a frequency detection circuit 11 is newly provided which inputs the reference pulse θof from the zero cross detection circuit 10 and outputs a frequency detection signal f, and the pulse generation circuit 8A receives this detection signal ff: a correction signal. A new input terminal has been provided to read the data as .

周波数検出回路11の内部には図示しない一定周期毎に
パルスを発生するクロックパルス発生回路と、そのパル
スを基準パルスθ0の周期間に計数するカウンタを備え
、このカウンタの計数値を周波数検出信号fとして出力
する。従って、電源の周波数が低いときカウンタの計数
値fは大きく、周波数が高いとき計数値fは逆に小さく
なり、パルス発生回路8人は電格周波数f、のときの計
数値fが零補正となる様に補正動作を行っている。
The frequency detection circuit 11 includes a clock pulse generation circuit (not shown) that generates pulses at regular intervals and a counter that counts the pulses during the period of the reference pulse θ0, and the count value of this counter is used as the frequency detection signal f. Output as . Therefore, when the frequency of the power supply is low, the count value f of the counter is large, and when the frequency is high, the count value f becomes small, and in the case of the 8 pulse generation circuits, the count value f when the power supply frequency is f is zero correction. Correcting operations are being carried out to ensure this.

第4図はパルス発生回路8Aの動作を説明するためのフ
ローチャートであり、第5図はその機能ブロック構成図
である。即ち、パルス発生回路8人の内部には基準パル
スθ0のタイミングで制御位相角信号θを読込む位相制
御信号読込手段21と、周波数検出信号fi読込む周波
数検出信号読込手段22を有し、位相制御信号読込手段
21は制御位相角信号θによりチェックパルス計数手段
23を初期設定し、周波数検出信号読込手段22は周波
数検出信号fiチェックパルス周期補正手段24に設定
してチェックパルス発生手段25で発生するチェックパ
ルスの周期τ1全周波数検出信号fに比例する様に補正
する。この場合、前述した様に電格周波数f、に於て零
補正となる様に設定される。。
FIG. 4 is a flowchart for explaining the operation of the pulse generating circuit 8A, and FIG. 5 is a functional block configuration diagram thereof. That is, the eight pulse generating circuits have a phase control signal reading means 21 for reading the control phase angle signal θ at the timing of the reference pulse θ0, and a frequency detection signal reading means 22 for reading the frequency detection signal fi. The control signal reading means 21 initializes the check pulse counting means 23 using the control phase angle signal θ, and the frequency detection signal reading means 22 sets the frequency detection signal fi in the check pulse period correction means 24 and generates it in the check pulse generating means 25. The period τ1 of the check pulse to be detected is corrected so that it is proportional to the total frequency detection signal f. In this case, as described above, the electric rating frequency f is set to zero correction. .

チェックパルス発生手段25から得られたチェックパル
スCPはチェックパルス計数手段23で計数され初期設
定された制御位相角信号θの値に達すると制御パルス発
生手段26から制御ノくルスctl−出力する様に指令
を出す。
The check pulse CP obtained from the check pulse generating means 25 is counted by the check pulse counting means 23, and when it reaches the initially set value of the control phase angle signal θ, the control pulse CP is outputted from the control pulse generating means 26. issue instructions to.

従って、電源周波数が変化して交流電圧の周期が変化し
てもチェックパルスの周期τlも同様に補正され制御整
流器2を制御位相角信号θで与えられた位相で制御パル
スCにより正確に制御することができる。
Therefore, even if the power supply frequency changes and the period of the AC voltage changes, the period τl of the check pulse is similarly corrected, and the control rectifier 2 is accurately controlled by the control pulse C at the phase given by the control phase angle signal θ. be able to.

〔発明の他の実施例〕[Other embodiments of the invention]

本発明の制御整流器のディジタル制御装置によるパルス
発生回路8Aの他の実施例を第6図のフローチャートと
第7図の機能ブロック図に示す。
Another embodiment of the pulse generating circuit 8A using the digital control device for a controlled rectifier according to the present invention is shown in the flowchart of FIG. 6 and the functional block diagram of FIG. 7.

本実施例ではチェックパルスの周期τ1では一定として
チェックパルス計数手段23に初期設定される制御位相
角信号θの値を補正する様に構成している。即ち、周波
数検出信号読込手段22で読込まれた周波数検出信号f
を除算手段27に入力し検出周波数fの電格周波数fO
に対する周波数比K (’/fo )を演算して乗算手
段28に入力す2)。
In this embodiment, the control phase angle signal θ initially set in the check pulse counting means 23 is corrected by keeping the period τ1 of the check pulse constant. That is, the frequency detection signal f read by the frequency detection signal reading means 22
is input to the dividing means 27 to obtain the electric rating frequency fO of the detection frequency f.
The frequency ratio K ('/fo) is calculated and inputted to the multiplier 28 (2).

乗算手段28はこの周波数比Kを制御位相角信号θに乗
じてθs (=K・θ)を演算し、この補正しt―制制
御位相角信号型1よりチェックパルス計数手段23を初
期設定する。
The multiplier 28 multiplies this frequency ratio K by the control phase angle signal θ to calculate θs (=K·θ), corrects this, and initializes the check pulse counting means 23 from the t-controlled control phase angle signal type 1. .

従って、周波数の変化に応じて初期設定値が補正される
ので一定周期のチェックパルスを計数することにより周
波数が変化した場合でも制御位相角信号θで与えられた
位相で制御パルスCを発生することができる。
Therefore, since the initial setting value is corrected according to the change in frequency, even if the frequency changes by counting check pulses at a constant period, the control pulse C can be generated with the phase given by the control phase angle signal θ. I can do it.

〔発明の効果〕〔Effect of the invention〕

本発明によれば電源の周波数が変動しても制御整流器の
制御位相が正しく制御されるので周波数変動に起因した
転流失敗全防止でき、信頼性の向上した制御整流器のデ
ィジタル制御装置を提供することができる。
According to the present invention, the control phase of the controlled rectifier is correctly controlled even if the frequency of the power source fluctuates, thereby completely preventing commutation failures due to frequency fluctuations, and providing a digital control device for the controlled rectifier with improved reliability. be able to.

【図面の簡単な説明】[Brief explanation of drawings]

第1図は従来の制御整流器のディジタル制御装置のブロ
ック図、第2図は動作説明のためのタイミングチャート
、第3図は本発明による制御整流器のディジタル制御装
置のブロック図、第4図は本発明のパルス発生回路8A
’r説明するためのフローチャート、第5図はその機能
ブロック図、第6図は本発明の他の実施例によるパルス
発生回路8Aを説明するためのフローチャート、第7図
はその機能ブロック図である。 l・・・交流電源 2・・・制御整流器2人 ・・・制
御整流素子 3・・・負荷4・・・電流基準回路 5・
・・電流検出回路6・・・電流制御回路 7・・・関数
回路8.8A ・・・パルス発生回路 9・・・パルス増幅回路 IO・・・零クロス検出回路
11・・・周波数検出回路 21・・・位相制御信号読込手段 22・・・周波数検出信号読込手段 23・・・チェックパルス計数手段 24・・・チェックパルス周期補手段 25・・・チェックパルス発生手段 26・・・制御パルス発生手段 27・・・除算手段 28・・・乗算手段(7317)
 代理人 弁理士 則 近 憲 佑(ほか1名)第1図 第2図 1 第3図 1ね 第4図 第5図 θ f 第6図
FIG. 1 is a block diagram of a conventional digital control device for a controlled rectifier, FIG. 2 is a timing chart for explaining the operation, FIG. 3 is a block diagram of a digital control device for a controlled rectifier according to the present invention, and FIG. 4 is a block diagram of a digital control device for a controlled rectifier according to the present invention. Pulse generating circuit 8A of the invention
5 is a functional block diagram thereof; FIG. 6 is a flowchart illustrating a pulse generation circuit 8A according to another embodiment of the present invention; and FIG. 7 is a functional block diagram thereof. . l... AC power supply 2... Control rectifier 2 people... Control rectifier element 3... Load 4... Current reference circuit 5.
...Current detection circuit 6...Current control circuit 7...Function circuit 8.8A...Pulse generation circuit 9...Pulse amplification circuit IO...Zero cross detection circuit 11...Frequency detection circuit 21 ...Phase control signal reading means 22...Frequency detection signal reading means 23...Check pulse counting means 24...Check pulse period complementing means 25...Check pulse generating means 26...Control pulse generating means 27... Division means 28... Multiplication means (7317)
Agent Patent Attorney Noriyuki Chika (and 1 other person) Figure 1 Figure 2 Figure 1 Figure 3 Figure 1 Figure 4 Figure 5 θ f Figure 6

Claims (3)

【特許請求の範囲】[Claims] (1)交流電源から電力が供給され負荷に電力を供給す
る制御整流器と、前記交流電源の電圧極性が反転する毎
に基準パルスを発生する零クロス検出回路と、ディジタ
ル値の制御位相角信号と前記基準パルスが入力され前記
制御位相角信号に対応した電圧位相で前記制御整流器を
位相制御する位相制御回路を具備した制御整流器のディ
ジタル制御装置に於て、所定の周期でチェックパルスを
発生するチェックパルス発生手段と、前記基準パルスで
定まる所定のタイミングで前記制御位相角信号で定まる
値が初期設定され前記チェックパルスを前記初期設定の
パルス数だけ計数したとき制御位相角タイミング信号を
出力するチェックパルス計数手段と、前記交流電源の周
波数に対応したディジタル値の周波数検出信号を検知す
る周波数検出手段と、前記周波数検出信号により前記制
御位相角タイミング信号を補正する周波数補正手段を設
けたことを特徴とする制御整流器のディジタル制御装置
(1) A control rectifier that is supplied with power from an AC power source and supplies power to a load, a zero cross detection circuit that generates a reference pulse every time the voltage polarity of the AC power source is reversed, and a control phase angle signal that is a digital value. In a digital control device for a control rectifier including a phase control circuit which receives the reference pulse and controls the phase of the control rectifier with a voltage phase corresponding to the control phase angle signal, a check pulse is generated at a predetermined period. pulse generating means; and a check pulse for outputting a control phase angle timing signal when a value determined by the control phase angle signal is initially set at a predetermined timing determined by the reference pulse and the check pulse is counted by the initially set number of pulses. A counting means, a frequency detection means for detecting a frequency detection signal of a digital value corresponding to the frequency of the AC power supply, and a frequency correction means for correcting the control phase angle timing signal using the frequency detection signal. Control rectifier digital controller.
(2)前記周波数補正手段を前記周波数検出信号に応じ
て前記チェックパルスの周期を補正するチェックパルス
周期補正手段とし、前記チェックパルス発生手段を前記
チェックパルス周期補正手段からの指令に基づいて前記
チェックパルスを発生する様に構成し次前記特許請求の
範囲第1項記載の制御整流器のディジタル制御装置。
(2) The frequency correction means is a check pulse period correction means for correcting the period of the check pulse according to the frequency detection signal, and the check pulse generation means performs the check pulse period correction means based on a command from the check pulse period correction means. A digital control device for a controlled rectifier as claimed in claim 1 and configured to generate pulses.
(3)前記周波数補正手段を、前記周波数検出信号と定
格周波数で定まる信号により周波数比を演算する除算手
段と、前記制御位相角信号と前記周波数比の積を演算す
る乗算手段とし、この積の値を前記チェックパルス計数
手段に初期設定する様に構成した前記特許請求の範囲第
1項記載の制御整流器のディジタル制御装置。
(3) The frequency correction means includes a division means for calculating a frequency ratio using the frequency detection signal and a signal determined by the rated frequency, and a multiplication means for calculating the product of the control phase angle signal and the frequency ratio, 2. A digital control device for a controlled rectifier according to claim 1, wherein a value is initially set in said check pulse counting means.
JP12236183A 1983-07-07 1983-07-07 Digital controller of controlled rectifier Pending JPS6016175A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP12236183A JPS6016175A (en) 1983-07-07 1983-07-07 Digital controller of controlled rectifier

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP12236183A JPS6016175A (en) 1983-07-07 1983-07-07 Digital controller of controlled rectifier

Publications (1)

Publication Number Publication Date
JPS6016175A true JPS6016175A (en) 1985-01-26

Family

ID=14833984

Family Applications (1)

Application Number Title Priority Date Filing Date
JP12236183A Pending JPS6016175A (en) 1983-07-07 1983-07-07 Digital controller of controlled rectifier

Country Status (1)

Country Link
JP (1) JPS6016175A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2008172931A (en) * 2007-01-11 2008-07-24 Toshiba Corp Phase controller
US9666772B2 (en) 2003-04-30 2017-05-30 Cree, Inc. High powered light emitter packages with compact optics

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US9666772B2 (en) 2003-04-30 2017-05-30 Cree, Inc. High powered light emitter packages with compact optics
JP2008172931A (en) * 2007-01-11 2008-07-24 Toshiba Corp Phase controller

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