JPS60151760A - System electronic device - Google Patents

Abstract

PURPOSE:To secure the optimum access for each internal memory and to improve the overall system efficiency by providing a holding circuit to the main body of an electronic device and an external memory respectively then applying the wait to a CPU after selecting the outputs of both holding circuits. CONSTITUTION:When only the main body 3 of an electronic device is used, the level is always biased to logic ''1'' since the reversed wait signal which is applied to a NOR gate 310 does not exist. Therefore the wait is applied to a CPU 301 for a period of time corresponding to the set value output of a holding circuit 304 when the CPU301 gives an access to an internal memory 302. In case an auxiliary memory 4 is connected to the main body 3, the wait is applied to the CPU301 for the periods optimum to the internal and external memories according to the set values of the circuit 304 and a holding circuit 402 respectively when the CPU301 gives an access to the memory 302 or an external memory 401.

Description

DETAILED DESCRIPTION OF THE INVENTION [Technical Field] The present invention relates to system equipment consisting of, for example, microprocessors and memories, and in particular to system equipment that facilitates connection or integration of equipment groups in an IJ-like manner, such as functional expansion of system equipment. The present invention relates to system electronic equipment that can be separated.

[Prior art] The recent development of ')(j/- technology has been remarkable. In particular, the highly integrated ICs have made it possible to produce extremely small, low-priced, high-performance electronic devices such as burner continuators and word-folders. Processors, office computers, etc. have come to be realized.

However, with the development of technology, these electronic devices have become widespread in various fields, and the way they are used is becoming extremely diverse depending on the usage of each user. Therefore,
Even if the same electronic device is used, the required specifications and performance vary widely depending on the power of use. In this case, the quality may be too high for some users, resulting in a device with poor cost performance as a whole.

To deal with this, the following methods are generally used. In other words, the main body of the electronic device is equipped with only the essential functions, and other electronic devices according to each user's specifications, such as an expansion memory or an expansion character generator, etc. This is the way to connect. These are called ROM cartridges, RAM cartridges, etc., and are used to expand the functions of electronic devices, increase the number of types of character phono I, etc. that can be handled, or temporarily store various data.
An example of this is the one used for the purpose of extension A.

FIG. 1 depicts the main functions of an example of conventional system electronic equipment. The figure above shows things related to memory access functions. In the figure, 11 inch system tun f-4
A device, for example the main body of a personal computer 9, contains a central processing unit (CPU) IOJ, which is the main controller of the system device.
ROM and RA for storing the operating program “9”
An internal memory 102 consisting of M is included. Also, the built-in way l' +A ``'j generator] 03 generates C by the weight signal of the line 104 which is its output.
It functions to make the operation of PUl0I wait like -.B5.

In general, when the CPU writes to or writes to internal memory, in order to match the access time (memory cycles) of that memory with the control speed of the CPU, each memory access requires a fixed amount of time. Keep the CPU waiting,
For example, the read data from the memory is completely valid before outputting the 1-1 strobe, or the data from the /\ bus is completely write-enabled before the write strobe wait signal is output. ``1-03'' is used to give this waiting time, and when accessing CPUIOI or internal memory 102, 1-'
CPU for a predetermined period of time
It has a function of applying weight to I O l. 2 is the aforementioned ROM cartridge and RAM cartridge'
It is an auxiliary storage device that has a phase with 9, and is ROM or RAM.
It has a built-in external memory 201 consisting of. Normally, the external memory 201 uses a memory element whose access time is the same as that of the internal memory 102.
3 is C P U i. .

When accessing the external memory 101, the CPU IOI is operated in the same way as when accessing the internal memory 102, so that the CPU IOI is weighted during daylight saving time. Thus, by connecting the auxiliary storage device 2 to the main body 1 of the system unit, it is possible to expand the functions of the entire system as if the internal memory 102 had been expanded. 'il
j1 equipment had the following drawbacks.

That is, the external memory 201 always contains the internal 743 memory 102.
This means that the accesses 11+j and 11+j are the same, or the high-speed memory element r must be used for 4-. As mentioned above, the recent development of ``Subject technology'' (which is quite alarming, as well as the increase in memory storage and faster operation speeds for memory devices), and the 1°f from cheap depending on performance
A wide variety of things or rivers, up to 71 valence A] have been described. - In the system electronic equipment that is the subject of the present invention, 1
Since the main units of the devices are the same, it is necessary to use a variety of auxiliary storage devices depending on the user's processing needs and desired prices.

That is, each auxiliary storage device and 1-, -C. It is desired that the user be able to use the optimal mesenary element f from the viewpoint of [loss]・niya+1 function', j. On the other hand, in conventional system sub-devices, the access time of the external memory 201 on the auxiliary storage device 2 side is changed to the internal memory of the device body 1 as described above. It was necessary to increase the access time to 1iI or equal to or longer than the access time of 0.02. For this reason, the degree of freedom in selecting a memory element to be used in the auxiliary storage device 2 is extremely limited in terms of cost and performance.

In addition, in order to eliminate this drawback, auxiliary storage devices with various rated access times can be used freely.
-J'- In some cases, the wait time for the CPU in the main body of the device is set aside to 1 minute in advance. However, in this case, even if you want the auxiliary storage to operate at high speed by using a memory element with a short access time, the external memory will always be loaded with more time than is safe, and the performance of the auxiliary storage will deteriorate. There were inconveniences such as the inability to perform to the best of one's ability.

[1-1] The present invention has been made in view of the above-mentioned shortcomings of the prior art, and its purpose is to enable users to use the system in accordance with the processing purpose and price of electronic equipment. To provide a system device that can always maximize the performance of each storage device even when an auxiliary storage device with a high performance is installed.

Embodiment] Hereinafter, one embodiment of the present invention will be described in detail with reference to the drawings.
Explain.

FIG. 7 is a block diagram illustrating the functional configuration of a system according to an embodiment of the present invention.

In FIG. 1, numeral 3 denotes the main body of the system element device, and numeral 4 denotes an auxiliary storage device provided in the main body 3 in a removable manner. In addition, other devices such as a normal keyboard and display device can be connected to the main body 3 as shown in the figure. Next, in main body 3, 30
1 is a central processing unit (CPU) that handles the main control of system electrical equipment, and 3C12 is a CPU 301.
The internal memory 303 of the main body 3 consisting of RAM and ROM used by the CPU 301 is composed of a pass line for outputting data, address messages, etc. through a memory common bus of the CPU 301.

Further, 304 is a holding circuit that holds information regarding the rated access time of the internal memory 302, and 305 is a presec pull counter circuit whose initial count value can be set from its parallel data input terminal. Further, in the auxiliary storage device 4, 401 is an external memory consisting of a RAM or ROM provided removably attached to the internal memory 302, and 402 is information regarding the rated access time of the external memory 401. a holding circuit that holds lu;
403 is a presec pull counter circuit that can set the initial value of Callan 1 from its parallel data input terminal /-D.

The operation of the above configuration will be described in detail below. CPU
301 normally accesses the internal memory 302 each time an instruction is executed. Also, if the CPU 301 addresses the external memory 401 in the same way, the external memory 401
The contents of 1 are accessed. In this way, the CPU 301
Which memory to access is determined simply by the value of the address signal placed on the memory common path 303. Normally, the higher address between address rooms is assigned to the external memory 401. Therefore, the main body 3 of the system component device operates without any problem even when the auxiliary storage device 4 or the device i is not connected. However, if you wish to execute a particularly large program, for example, simply load this auxiliary storage device 4 into the main body 3 and you will be able to execute it. In this way, electrical contact between the main body 3 and the auxiliary storage device 4 is made via the connect means configured to be detachable. The line 404 and the signal line 404 that transmits the output signal of the calafter 1tJJ path 403 have high impedance.In the main body 23, the level of path belief in this state is left to the control of the main body. (The configuration is complete. For example, the memory cell 303 is operated at 3-stay 1 and element f, and the signal line 404 is at the logic level 1 unless an external signal is applied to the line.) Therefore, at this time, the belief is 1.
The belief on the bow line 404 is +<Hatake, which is the level of logic l. On the other hand, a holding circuit 304 in the main body 3 is set so as to output a predetermined dental signal. Its(11'
f is a value determined by the rated access 115 of the internal memory 302, and CP 1. It is held as a complement of a number equivalent to several machine clocks of J301. Holding circuit 3
04 outputs a binary ♀ consisting of logical 1 and 0 levels, 1 inch to the field, and its concrete rl'J configuration includes 1-i,
For example, micro tip switch, wire ay v-)
It is suitable that l nap''≦. This also applies to the holding circuit 402.
The i1fi output is sent to the counter circuit 30 via line 306.
5's parallel take input terminal - (power, counter circuit 305's counter) J end fC has C
P U 301 or machine clock or line 307
It is constantly being read through. In addition, the input terminal 305 is connected to the counter circuit 305 from the internal memory 302 via the line 308.
It is now possible to obtain

Count 11 Seishinyumi 1 sun CPIJ301 or internal memory 3
Logic 1 whenever initiating memory access of 02
The level of the students is questioned. In other words, the memory common path 303
Whenever the address signal - points to the internal memory 302, its (+l'i) is decoded in the internal memory 302 to become the selector of the internal memory 30z and the CPi node 301. Which timing signal of J9i is rotated at 5th hour and the count is 1 to the level of logic 1?
・You will be attacked. Is this for internal memory 302? The same applies to no 1 cycle and write cycle. Then, the value of the parallel data input terminal fD is preset to the counter circuit 301 by this step (1), and from then on, it is counted up until it reaches the most significant bit of the counter circuit 305 or the level of logic J. Ru. Also, the top 4 of the counter circuit 305 is a hit! l!
Until it reaches the level I, the output at the logic O level is connected to the NOR cables 1 and 3 via its output I''o and line 309.
The logic 1 level of its inverted output is applied to the weight input terminal rW of the CPU 301. In this state, the CPU 301 is a weight-like piece. In other words, Tammy's time is spent internally.

When the highest value of the counter circuit l183 o5 reaches the logic 1 level, the counter circuit 305 internally registers 1. The level of 1 - 1, which at the same time stops the count of 1, is input to NORK 310 via output f-0 and line 309 . Therefore, this time, the logic O level of the inverted output is applied to the wait input terminal W of the CPU 301. In this state, CPU301
is divided by the way[-state or 1f'h''.If we look at it differently in such an operation, the way I signal on line 311 is the initial setting of 8305 (start of memory access) at the counter time. !J) to Ae J!l',
This signal is set to the logic 0 level and returns to the logic 0 level after a predetermined time period based on the counting operation of the counter circuit 305 has elapsed. That is, the wait operation within C'P'U 301 is activated only while the wait signal is at a logic I level. The CPU 3, 01 uses this wait time to delay the strobe pulse for writing to or reading from the internal memory 302. In this manner, when one memory access to internal memory 302 is completed, the count signal on line 308 is deactivated to a logic zero level. Then, if 1) and memory access from the CPU 301 is required, two consecutive operations are executed.

Next, the operation in the external memory 401 in the auxiliary storage device 4 is also similar to that described above. In other words, the holding circuit 4
02 is set to output a predetermined digital signal. The value is determined by the rated access time of the external memory 401, and is held as a complement of the number of machine clocks of the CPU 301. The set value output of the holding circuit 402 is input to the +b column data input terminal of the counter circuit 403 via a line 406. When the auxiliary storage device 4 is connected to the main body 3, the machine clock from the CPU 301 is input to the clock input terminal (-C) of the counter circuit 403 via the line 307.
A count activation signal is applied to -H from the external memory 401 via a line 405. The count enable signal is asserted to a logic 1 level whenever CPU 301 or external memory 401 initiates a memory access. In other words, whenever address 14 of memory common path 303 points to external memory 401, its target is decoded in external memory 401 and stored in external memory 401.
The selection activation signal becomes 01, and the count activation signal is activated to the logic 1 level in synchronization with a predetermined timing signal from the CPU 301. The subsequent operations are the same as those described for the main body 3. That is, line 3
The wait signal No. 11 is set to the logic 1 level when the counter circuit 403 is initialized, and after a predetermined period of time according to the counting operation of the counter circuit 403 has elapsed, the wait signal is returned to the logic 0 level. In this way, only while the wait signal on line 311 is at the logic 1 level, the CPU 30
According to a preferred aspect of this embodiment, the rated access time of the external memory 401 is longer than the rated access time of the internal memory 302. In other words, a memory element r- having a slow rated memory cycle is used. Therefore, the time when the wait signal on line 311 is at the logic 1 level is
It takes longer to access the external memory 401 than to access 02. Furthermore, there is no need for the CPU 301 to be concerned with the generation control of such wait signals having different time widths for each of the 4Ns. It is clear from the above description that the CPU 301 only needs to access the internal memory 302 or the external memory 401 according to the normal program execution process]'+nn.

According to another desirable aspect of this embodiment, the rated access time of the external memory 401 is longer than that of the internal memory 30.
This is more interesting than the >if case access time of 2. In other words, it is a memory element with a fast rated memory cycle. In this case as well, the CPU 301 only needs to access the internal memory 302 and the external memory 401 according to the beauty processing procedure of the normal program. In this case, the holding circuit 402 holds a setting value that generates a wait signal with a shorter time width than that of the internal memory 302, so the internal memory 302 also holds a setting value that generates a wait signal with a shorter time width than that of the internal memory 302.
The best 'A' for each person! access time.

In this way, the system unit of this embodiment is used, for example, as follows. First, if the main body 3 is used only and the auxiliary storage device 64 is not connected, the NOR gate 3 is connected to the counter circuit 403 via the line 404.
This level is always biased to logic 1 since there is no inverse of the weight signal input to 10. Therefore, when the CPU 301 accesses the internal memory 302, the CPU 301 waits for a period of time corresponding to the output of the holding circuit 304 (+ri).Furthermore, when the auxiliary storage device 4 is connected, the CPU 301
02 or when accessing external memory 401
The setting of the holding circuit 304 (based on the iri and the setting value of the holding circuit 402) is the optimum time for each memory (CPU
Weight is applied to 301. Furthermore, no matter how long the path access ITν of the memory element r- used for the internal memory 302 and the external memory 401 is), C
The PU 301 can efficiently load the REIT or LIE 1 of both memories at the optimal way i and time. Further, as the external memory 401, there is another auxiliary storage device 4' using another storage device 4' with a different rated access time.
Even when connected, the holding circuit 4 set there
Based on the configuration of 02', the CPU 301 can always read or write the internal memory 302 and the external memory 401' in an optimal access time.

In this embodiment described above, the inverted signals of the weight signals with different time widths are collected by the NOR cable 1-310 and sent to the CP.
Having described the configuration for outputting to U301, the configuration of another embodiment according to the present invention is shown in FIG. Here, NOR Kate 31 in Figure 2
Instead of using 0, the CPU 301 outputs through the line 313 a selection signal which selects and outputs the - from the input numbers 309 and 404A:+ to the line 31.1. line selector circuit 312i, -c, 11/) Does the CPU 301 use the internal memory 302 or the external memory 4゜l, or whether there is an external memory 401' connected in parallel? If the external memory 401' is to be used, the selection result is output to the line selector circuit 3]2, and then the selected memory is connected to the selected line. It may be configured to perform a series of accesses. In this case, as described for the embodiment of FIG.
1" Counts the signal on line 308 or 405 only when its memory is accessed.
The so-called Tecoat machine Zushichi, which outputs to , becomes haunted.

Therefore, in this case, even if the CPU 301 accesses the memory, all the counter circuits 305, 403, . . . are activated. However, the line selector circuit 3]2 corresponds to the way l'ii<
Since only 'j is selectively output, any memory can be accessed in the optimal access time, similar to the embodiment shown in FIG.

Furthermore, in the embodiments of FIGS. 2 and 3 described above, 4
Even if a plurality of auxiliary storage devices equipped with external memories 401 of different characteristics are connected in parallel, each of them can be
By increasing the input terminal -f of the NOR cable 1-310 or by increasing the input terminal f- of the line selector 312, the weight signal output from each auxiliary storage device is transferred to the weight input terminal of the CPU 301. If allocated appropriately, all memory will be accessed with optimal access time.

Furthermore, the system device of the present embodiment described in (-) may be configured such that the main body 3 and the auxiliary storage device 4 are not detachable but integrated.

[Effects] As described above, according to the present invention, what kind of access I
T! Even with an auxiliary storage device composed of 7 memories, it is possible to match M1 very easily.

Moreover, since the memory elements of each auxiliary storage device are always accessed at their own optimum memory access time, the efficiency of the system electronic equipment as a whole is extremely high. Therefore, the user can select and use the most suitable auxiliary storage device in consideration of the purpose of processing and economic efficiency.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing the main functional configuration of a conventional system electronic device, FIG. 2 is a block diagram showing the main functional configuration of a system electronic device according to an embodiment of the present invention, and FIG. 3 is a block diagram showing the main functional configuration of a conventional system electronic device. It is a block diagram showing the main functional composition of system electronic equipment which is another example concerning the present invention. Here, 1.3... electronic equipment system body, 2゜4.
...Auxiliary storage device.

Claims (4)

[Claims] (1) A system 'tun I' device configured with one access stage by installing one stage of fu number 1-1 self-memory-1, with nine information processing stages and the information processing stage. Use at least 1
71j means for outputting a signal to change the rated access time when accessing the lower storage stage; Memory - furthermore, another wait control means for outputting a wait signal for obtaining the rated access time when accessing the details storage means; When accessing the second stage, the output of the wait control means 1 also transmits 4+i to the information processing means, and when accessing the information processing stage Pl'T or the other memory -1 stage, The other waiting system (1)
The waiting information outputted by the means 11 is sent to the lower stage of the information processing.
), and 11) control means for controlling the waiting period 1111 necessary for accessing the memory means. System 1 with l+f characteristics,'
Shigeko equipment. (2) an information processing means, at least one memory 1' used by the information processing means, and a waiting time 1' for obtaining the rated access time when accessing the memory means;
1 standby control means for outputting the bow is located in the main body of the system 18 device, and (J) is provided with another storage stage 1,
Another waiting control means that outputs the waiting %-'+'r to obtain the 1-case access 11+f when accessing the lower row of memory of details is the liquor tax 1 in the main body of the system electronic equipment.
4. Be in auxiliary storage configured in 1. The system 1 according to claim 1(a), which is characterized by 'r', 'il
j (equipment. (3) A system element device configured to have a storage lower stage that is removably attached (one storage unit) and has zero access capability, including an information processing means, at least one storage means used by the information processing means, A wait control means outputs a waiting signal to obtain the rated access time when accessing the first storage stage, and a signal output by another storage means that may be installed and accesses the lower storage stage of details. an input/output means for outputting a belief output by another waiting control means, which outputs a waiting signal for obtaining the rated access time, through a part of the mechanism configured to be detachable; When accessing the storage means in stage 1 or above,
A wait signal output from the lower wait control section of the information processing means is given to the information processing means, and when accessing the other storage means to which the information processing stage 1 may be installed, the wait signal output from the wait control means of the second storage is applied to the information processing means. 1. A system ``IL+ equipment'' characterized by comprising a control means for controlling a waiting time for accessing said storage means. (4) Memory] A system electronic device that is configured to have at least one removable 71 removable system for an electronic device that blocks an information processing means that is configured to have one removable 7i removable side and access it. Storage means and under a wait control for outputting a wait signal for increasing its rated access time when accessing the storage means. 111" memory t.
311 stages of human output signal and the waiting; 1) input/output stage for human outputting the waiting signal output from the control means through a portion of the mechanism configured to be freely attachable/detachable; System electronics.