JPS60132421A - Multi-point analog output circuit - Google Patents

Abstract

PURPOSE:To obtain an inexpensive multi-point analog output circuit by using a memory circuit which converts the digital quantity into the analog quantity and holds the analog quantity. CONSTITUTION:The output of a basic clock generator 1 is applied to a binary counter 2 and a frequency divider 3, and the counter 2 supplies the output signal A to a memory circuit 5 as well as to a switch signal generator 12. The divider 3 supplies the signal C obtained by dividing the basic clock to a latch circuit 6 and the generator 12. The circuit 5 supplies the corresponding digital data to the circuit 6, and the signal latched by the circuit 6 is converted into an analog quantity by a D/A converter 9. The generator 12 delivers successively control signals G, H and I with inputs of signals A and C to close switches 13-15. Then capacitors C19-21 are charged successively by the analog quantity given from the converter 9 via resistances 16-18. The voltage of these capacitors are applied respectively to the plus terminals of amplifiers 22-24. When switches 13- 15 are turned off, the voltage of the C19-21 are stored and delivered as they are since the input impedances of the amplifiers 22-24 are high.

Description

DETAILED DESCRIPTION OF THE INVENTION [Technical Field of the Invention] The present invention relates to a multi-point analog output circuit.

[Prior art]

Conventionally, there is a device shown in FIG. 1 as such a device.

In the figure, 1 is a basic clock generator, 2 is a binary counter that inputs the clock code of the basic clock generator 1, and 6
is a frequency divider that divides the clock signal of the basic clock generator 1; 4 is connected to the outputs of the binary counter 2 and the frequency divider 6;
A timing generator 5 generates latch timing for the latch circuit 6°7.8, and 5 is a storage device that receives the output of the binary counter 2 and outputs output digital data. 6゜7
．． 8 is a multi-bit latch circuit, and 9.10.11 is a digital-to-analog converter that receives the output of the latch circuit 6.7.8 and converts a digital quantity into an analog quantity.

Next, the operation will be explained. The output of the storage device 5 receives the output signal of the binary counter 2 and outputs the corresponding digital data. In FIG. 1 and FIG. 2 showing the operation timing, A is the output of the binary counter 2, and B is the output of the storage device 5.
The output shows the state of 111 or 101 of a plurality of bit outputs.

A latch timing generator 4 receiving the outputs of the frequency divider 6 and the binary counter 2 generates a latch timing signal for the latch circuit 6.7.8. C in the figure is the output signal of branch unit B,
D, E, F are the output signals of the latch timing generator.

The latch circuit 6.7.8 latches the output signal of the storage device 5 in synchronization with the output signal of the latch timing generator 4, and outputs it to the digital-to-analog converter 9, 10.
The digital-to-analog converter 9.10.11 converts the input digital quantity into an analog quantity and outputs it.

Multi-point analog output is executed as described above.

Conventional multi-point analog output circuits are constructed as described above, but have the drawbacks of requiring a latch circuit and a digital-to-analog converter for each point, and being expensive and having many components.

[Summary of the invention]

This invention has been made to eliminate the drawbacks of the conventional ones as described above, and provides an inexpensive multi-point analog output circuit by including a circuit for storing digital quantities converted into analog quantities. It is an object.

[Embodiments of the invention]

An embodiment of the present invention will be described below with reference to the drawings. 8th
In the figure, 1 is a basic clock generator, 2 is a binary counter, 6 is a frequency divider, 5 is an output digital data storage device,
6 is a latch circuit, 12 is a signal generator that receives the outputs of binary counter 2 and frequency divider 6 and generates open/close signals for switches 16°14.15, and 1!1.14.15 is a digital circuit.
a switch connected to the output of the analog converter 9; 16.
17 and 18 are resistors, and 19, 20, and 21 are capacitors connected to the non-inverting input terminals of operational amplifiers 22, 23, and 24. 22, 23, and 24 are operational amplifiers, the outputs of which are connected to each inverting input terminal.

Next, the operation will be explained.

, the output of the basic clock generator 1 is applied to a binary counter 2. The output of binary counter 2 is shown in FIG. 4A. The frequency divider 6 inputs the output of the basic clock generator 1,
The output shown in FIG. 4C is generated. The storage device 5 inputs the output of the binary counter 2 and outputs the corresponding digital data to the latch circuit 6, which latches the digital data. The output of the latch circuit 6 is converted into an analog quantity by a digital-to-analog converter 9.

The opening/closing signal generator 12 inputs the outputs of the binary counter 2 and the frequency divider 6, and is connected to G and H in FIGS. 8 and 4.

Generates the output shown by ■. While G, H, and I are set to HIGH level, the corresponding switches 13.
14.15 is closed and charges the capacitor 19.20.21 to the output voltage of the digital-to-analog converter 9 via the resistor 16.17.18. Next switch 13
．． 14.15 is opened, operational amplifier 22.23.2
Since the input impedance of the non-inverting input terminal 4 is high, the charge stored in the capacitor 19, 20, 21 is held, and the output of the operational amplifier 22, 26, 24 is equal to the input voltage, so the switch 13 , 14° and 15 remain at a voltage equal to the voltage that charged the capacitors 19, 20, and 21 until they are closed. After converting the digital quantity into an analog quantity as described above, by storing the cough analog quantity K, it is possible to generate analog outputs at multiple points.

In the above embodiment, the analog output is 8 points, but by increasing the number of circuit components, it is possible to control a larger number of points.

〔Effect of the invention〕

As described above, according to the present invention, since a storage circuit is provided for holding the analog quantity after converting a digital quantity into an analog quantity, the number of latch circuits and digital-to-analog converters may be one set, and the apparatus can be It can be made cheap.

[Brief explanation of the drawing]

FIG. 1 is an electrical connection diagram showing a conventional multi-point analog output circuit, FIG. 2 is a timing diagram showing the operation timing of a conventional multi-point analog output circuit, and FIG. 8 is an electrical connection diagram showing the operation timing of a conventional multi-point analog output circuit. FIG. 4 is a timing diagram showing the operation timing of an embodiment of the present invention. 1... Basic clock generator, 2... Binary counter,
6... Frequency divider, 4... Latch timing generator, 5
...Storage device, 6.7.8...Latch circuit, 9.1
0゜11...Digital-analog converter, 12...
・Opening/closing signal generator, 13.14.15...switch,
16°17.18...Resistor, 19.20.21...
・Capacitor, 22.23.24... operational amplifier. In the figures, the same reference numerals indicate the same or equivalent parts. Patent applicant: Mitsubishi Electric Corporation Figure 1 Figure 2 Figure 3

Claims (1)

[Claims] In a multi-point analog output circuit having a timing generator, a latch circuit operating based on the output of the timing generator, and a digital-to-analog converter inputting the output of the latch circuit, the digital-to-analog converter is a digital converter. A multi-point analog output circuit characterized by comprising a storage circuit that holds the analog quantity after converting the quantity into the analog quantity.