JPS60121756A - Semiconductor integrated circuit device - Google Patents

Abstract

PURPOSE:To avoid the concentration of wirings to the center of a chip, and to equalize the conditions of arrangement of unit cells by determining the arrangement and space of a plurality of unit cell aggregates and the number of the unit cells made to be contained in each unit cell aggregate so as to satisfy specific conditions. CONSTITUTION:Unit cell aggregates 13Li and 13Ri with Ni unit cells 12 on the right and the left separated only by distances li from the center are disposed so that their long sides coincide in the (y) direction. Rectangular unit cell aggregates 13Ui and 13Di are arranged so that the directions of their long sides coincide in the (x) direction while being separated only by a distance L1 in the vertical direction to these aggregates 13Li and 13Ri. There is the relationship of Ni+1>Ni and li+1>li between the number Ni of the cells 12 made to be contained in the No.i unit cell aggregate 13 at the distance li from the center O and the number Ni+1 of the cells 12 made to be contained in the adjacent No.i+1 aggregate 13 at the distance Li at that time. Regarding spaces L among adjacent aggregates 13, there is the relationship of Li+1>Li, and more wiring regions are ensured in the aggregates 13 in fringe sections in which the number of the cells 12 is increased.

Description

DETAILED DESCRIPTION OF THE INVENTION [Technical Field of the Invention] The present invention relates to a master slice type semiconductor integrated circuit device, and is particularly used for semiconductor integrated circuit devices that are produced in a wide variety of small quantities.

[Technical background of the invention]

The master slicing method is a chip construction method that is often used especially in large-scale integrated circuits (LSI) that are produced in high-mix, low-volume production. A plurality of columns 3 in which a plurality of unit cells 2, which are basic element aggregates such as the like, are arranged are arranged with a predetermined wiring region 4 in between. Such wiring within cell 2 and column 3 allows the logic unit l? By creating and further wiring between the logic units in the wiring area 4, a desired circuit can be easily formed.

Conventionally, the aggregates (columns) of unit cells as described above have the same shape within a chip and are arranged in the same direction.

[Problems with background technology]

However, in such a master slice type semiconductor integrated circuit device, when the logic units are arranged and mutually arranged l1 in order to obtain a desired semiconductor integrated circuit, the logic unit in the center is connected to the logic units arranged in the periphery. On the other hand, although wiring is required, the wiring of the logic unit arranged on one periphery is directed toward the center, so the number of wiring is increased at the center of the chip. When wiring is concentrated in the center like this, it not only becomes difficult to automate wiring, but it also causes a decrease in reliability.
! In order to avoid the concentration of wiring, it is necessary to take a detour of the wiring, which causes a problem in that characteristics deteriorate as impedance increases.

In addition, in a conventional master slice type semiconductor integrated circuit device, all unit cell aggregates are arranged in the same direction, so the arrangement of the unit cells in the chip differs when viewed from each side, and as a result, the input section Another problem is that the electrical characteristics may be different depending on whether the output section is located on the X side or on the Y side perpendicular thereto.

[Purpose of the invention]

The above invention has been made in view of the above ratio 1^, and an object of the present invention is to provide a semiconductor integrated circuit device that can avoid wiring concentration at the center of the chip and make the arrangement of unit cells equal when viewed from each side of the chip. With the goal.

[Summary of the invention]

To achieve the above object, in the present invention, in a master slice type semiconductor integrated circuit device, a plurality of unit cell aggregates are arranged symmetrically with respect to the center of the chip so that the number of unit cells is equal in the X direction and the Y direction. In addition, the number of unit cells included in each unit cell aggregate increases as the distance from the center of the chip increases, and the interval between unit cell aggregates increases, making the wiring density almost uniform within the chip. Furthermore, variations in characteristics due to differences in chip direction are not caused.

[Embodiments of the invention]

Hereinafter, some embodiments of the present invention will be described in detail with reference to FIGS. 2 to 4. FIG. 2C is a plan view showing the unit cell arrangement of the semiconductor integrated circuit device according to the present invention, and is a unit cell assembly 13 in which a plurality of unit cells 12 are arranged.
are arranged around the chip center 0 in the lateral force (X direction) and in the vertical direction (X direction). That is, rectangular unit cell aggregates 13LI and 13FIIY having N1 unit cells on the left and right sides separated by a distance of 11 from the center 0 are arranged so that their long sides coincide with the X direction, and there are distances above and below them. Rectangular unit cell aggregates 13u separated by Ll, and ]:3pu Y whose long side direction is
Place it so that it matches the direction, repeat the same way as the sickle, and press X.
Unit cell aggregates 13 are arranged in the direction and the X direction. As is clear from FIG. 2, the number of unit cells 12 included in the unit cell aggregate 13 increases as the distance from the center O increases, and the number of unit cells 12 increases from the center to /! The number N of unit cells included in the first unit cell aggregate located at a distance of 1, and Ll
There is a relationship between the number Nj of unit cells included in the unit cell aggregate at the first intersection (4+ from the center) and the relationship Ni+t) N<and e,>c. Similarly, regarding the spacing between adjacent unit cell aggregates facing the same direction, Li + + >
There is a relationship of Li, and a large amount of wiring area is secured for unit cell aggregates at the periphery where the number of unit cells 12 is large.

FIG. 3 is a plan view showing another embodiment of the present invention, and in FIG. 2, unit cell aggregates 13 at the same level from the center are shown.
However, in this example, the number of unit cells 120 included in the one arranged in the X direction and the one arranged in the X direction was different, but in this example, the unit cell aggregates 131, 13'Ll, 13'ul, and 1aya are all rectangles of the same shape containing the same number of unit cells, and each unit cell aggregate is arranged so that each side includes one vertex of the square. . In this embodiment, the unit cell aggregates are arranged symmetrically with respect to the center.

FIG. 4 is a plan view showing still another embodiment, in which a hook-shaped unit cell aggregate I3 having arms of equal length in the X direction and in the X direction includes each vertex of a square. In this embodiment, the unit cell aggregates are arranged line-symmetrically with respect to the center R.

The present invention is not limited to the above embodiments.

The number of unit cells is equal in the X and X directions, and the number of unit cells included in each unit cell assembly increases according to the distance from the chip center. The present invention applies to all semiconductor integrated circuit devices having a master slice pattern in which the spacing between cell aggregates increases.

〔Effect of the invention〕

As described above, according to the semiconductor integrated circuit device according to the present invention, a plurality of unit cell aggregates are arranged symmetrically with respect to the chip center so that the number of unit cells is equal in the X direction and the Since we have a master slice pattern in which the number of site cells included in each unit cell aggregate increases as 1t increases, and the 1-inch interval between unit cell aggregates increases, the center The number of wiring is small because there are few unit cells to be wired.

In addition, although the number of unit cells increases at the periphery, a sufficient wiring area is secured, and there is no need for concentration of wiring or detours to avoid this, which can lead to deterioration of characteristics and reliability. There is no. Furthermore, the arrangement of the unit cells is the same when viewed from the X direction of the chip and when viewed from the X direction.

No matter which direction the input section or output section is located, variations in characteristics are unlikely to occur.

[Brief explanation of drawings]

FIG. 1 is a plan view showing a master slice pattern of a conventional master slice type semiconductor integrated circuit device. 2 to 4 are plan views showing master slice patterns of various embodiments of the semiconductor integrated circuit device according to the present invention. 1.11...chip, 2.12...unit cell, 3.
...Column, 13, 13', 13"... unit cell aggregate. Applicant's agent Kiyoshi Inomatab I Zukuku2 Takara 3 En et al.4 Sen

Claims (1)

[Scope of Claim] A semiconductor integrated circuit device in which a plurality of unit cell aggregates each having a plurality of unit cells arranged on a chip are arranged. The plurality of unit cell aggregates are arranged symmetrically with respect to the chip center so that the number of unit cells is equal in the X direction and the y direction, and the unit cells are included in each unit cell aggregate as the distance from the chip center increases. 1. A semiconductor integrated circuit device, wherein the number of said unit cells is increased, and the interval between said unit cell aggregates is increased.