JPS60118951A - Buffer memory control system in information processor - Google Patents

Abstract

PURPOSE:To write an operated before the registration from a main storage device to a buffer memory is not finished completely by providing a means representing up to which word in a block the registration is finished. CONSTITUTION:In executing an instruction requiring the write to the main storage device, whether a block including the operand exists in a buffer memory is checked and if not existing, whether or not the said block corresponds to a word finished for registration already in a block being registered from the main storage device to the buffer memory is decided by a comparator circuit 33. When the comparator circuit 33 decides that the operand having a write request exists in the word registered already, the circuit 33 sets a write enable signal to attain write to the buffer memory and the main storage device and in other cases, the circuit 33 writes the main storage device only.

Description

DETAILED DESCRIPTION OF THE INVENTION [Technical Field of the Invention] The present invention relates to an information processing device, and in particular to an information processing device that performs access processing in a central processing unit equipped with a buffer memory that retains a portion of the contents of a main storage device as a copy. This paper relates to a buffer memory control method for increasing speed.

[Technology background]

FIG. 1 is a conceptual diagram of a conventional information processing device to which the present invention can be applied. In the figure, 1 is the main memory, 2 is the central processing unit,
and 3 indicate buffer memory.

Note that other devices not directly related to the present invention are omitted.

FIG. 2 shows an example of the configuration of a buffer memory. As an example of the configuration of a buffer memory, a set associative method has been proposed and widely adopted, and this figure is also based on this method.

In the figure, 4 indicates a data section, which holds a part of the main memory as a copy. The data section 4 consists of M sets, each set consisting of N blocks. In order to make the explanation easier to understand, the number of blocks in the two explanations is 64.
It is assumed that the block consists of 64 consecutive bytes on a byte boundary, and the unit of block registration in the buffer memory is 8 consecutive bytes (2 words) on an 8-byte boundary. Reference numeral 5 denotes an address field, which holds a valid bit and an address on the main memory corresponding to each block of the data field 4.

In a conventional information processing device having such a buffer memory, if it is determined that the address of the operand write reference request exists in a block that is being registered from the main memory to the buffer memory, that block is The write reference of the operand was performed after the registration in the buffer memory of the operand was completely completed. in this case,
There is also a write reference request for a word that has already been registered in a block that is being registered in the buffer memory.

The drawback was that you had to wait until registration was completely completed.

[Purpose of the invention]

An object of the present invention is to compensate for the drawbacks of the prior art described above, and to speed up the processing of a central processing unit having a buffer memory so that blocks transferred from the main memory to the buffer memory are completely registered. The purpose is to provide a means to enable access to some previously registered data.

[Structure of the invention]

The present invention applies to words that have already been registered in a block of the buffer memory during the registration of the block from the main memory to the buffer memory. We note that operand write reference requests usually occur frequently.

In other words, when executing an instruction that requires writing to main memory, the central processing unit first executes an instruction that requires writing to main memory.

Check whether a block containing the operand address exists in the buffer memory, and if so, store it.

If the operand address does not exist in the buffer memory, it is determined that the operand address is an operand write reference to a registered word in the block that is being registered from the main memory to the buffer memory. It is intended to be stored.

The configuration of the present invention for this purpose is provided in an information processing apparatus having a buffer memory within the central processing unit that holds a copy of a part of the contents of the main memory.

A first means indicating which word in the block has been registered when registering a block from the main memory to the buffer memory, and a word at the address of the write reference request of the operand is registered from the main memory. A second means for detecting that the word of the address of the write reference request of the operand exists in the block that is being registered is in the main memory (also 〆τ). a third means for determining that by the first and twentieth means;

If the third means determines that the word at the address of the write reference request for the operand has already been registered from the main memory onto the buffer memory, the third means performs a write reference for the operand. It is characterized by having four means.

[Embodiments of the invention]

First, an outline of this embodiment will be described. First, it is detected whether the address of the operand penetrating reference request by the central processing unit matches the address of the busek that is currently being registered from the main memory to the buffer memory, and if they match, the operand detects whether the word indicated by the address of the write reference request for is already registered on the buffer memory or not, and if the corresponding word is already registered on the buffer memory, the write reference of the above operand is transferred to the buffer memory. and to the main memory.

If the write reference address of the operand does not match the address of the block that is about to be registered from the main memory to the buffer memory, or the address of the word that has already been registered, then Only performs a write reference of the operand.

In addition, before writing reference to the operand.

It is natural to refer to the address section of the buffer memory and check whether a matching block exists. If a block that matches the address of the operand write reference exists on the buffer memory, Then, write and refer to the operand in the main memory. and.

Only when the address of the omitted reference of the operand does not match any of the address parts of the buffer memory, the address comparison with the block and word being registered from the main memory described above may be performed.

FIG. 3 shows an embodiment of the configuration of a central processing unit based on the present invention, and is a diagram of the main part of the central processing unit, centering on the buffer memory. In the figure, 4 is the data section of the buffer memory, 5 is the address section of the buffer memory, and 6 is the instruction control section I.
U and f7 are calculation units EU.

8 is register MIR, 9 is register BWR, 10 is register BD 几, 11 is register IWR, 12 is register 0
WFL, 13 is register MWR, 14 is register MAR
, 15 is register BFAR, 16 is register EAR, 1
7 is a register BAR, 18 and 19 are selection circuits, 20
is a comparison circuit, 21 is a control line, 22 and 23 are address lines, and 24 and 25 are data lines.

Note that this embodiment will be explained assuming that a store-through type buffer memory is used. Therefore, if the store address is in the buffer memory, the store is performed in both the buffer memory and main memory.

Execution of instructions within the central processing unit occurs in a secondary manner. The instruction control unit IU6 (hereinafter referred to as IU) uses the address line 22 to send the address of the instruction to be executed to the register FliAR16 (hereinafter referred to as EA), and the address of the instruction to be executed is the address of the buffer memory. Comparison circuit 20 checks whether or not it exists in section 5 .

When it is found that the address of the instruction to be executed exists in the address section 5 of the buffer memory, one of the N blocks read from the data section 4 of the buffer memory is
Selected by the selection circuit 18.

The word of the instruction to be executed within the block is stored in register BD.
IU from the register IWRII (hereinafter referred to as IWR) via the filter 10 (hereinafter referred to as BDR) and the selection circuit 19
sent to and executed.

If the address of the instruction to be executed does not exist in the address section 5 of the buffer memory, a read request for the block containing the instruction is issued from register MAR1j (hereinafter referred to as MAR) to the main storage device.

As mentioned above, the block read from the main memory is divided into 8 times of 8 bytes (2 words) and transferred to the register MI.
The first word containing the instruction to be registered in the data section 4 of the buffer memory through the register BWR9 (hereinafter referred to as BWR) from the box 8 (hereinafter referred to as MIR) and to be executed is transferred to the data line 24 and the selection circuit 19. After that, I.W.
It is sent from R to IU and executed.

When executing a command, the IU uses the control line 21 to
Each command is sent to the calculation unit BU (hereinafter referred to as BU) to perform calculations. The operand data of the instruction required by the EU is read from the buffer memory or main memory in the same way as reading the instruction word of the IU, and is stored in register 0WR1.
2 (hereinafter referred to as OWR).

Additionally, if a block containing the address to which the EU operation result should be written is registered on the buffer memory,
The calculation result is stored in the buffer memory from the data line 25 via BWR, and also via register MWR13 (hereinafter referred to as MWR).

Stored in main memory.

Further, if the block including the address to which the EU operation result is to be written is not registered in the buffer memory, the block is stored only in the main memory via the MWR.

FIG. 4 is an explanatory diagram of the P■ flag used to detect the current registration position during block registration in the second embodiment. In the figure, 26 indicates a block, and 27 indicates a PV7 lag (Partial Valid Flag). The block consists of 8 x 2 words, and the PV flag is 8
There are bits, each corresponding to two words. Note that one word consists of 4 bytes. The P flag indicates which word (2 words) of the block has been registered when registering block 26 from the main memory to the buffer memory, and as the registration progresses, one pit is turned on. . Once the registration is complete, the validity of the block is indicated by the valid bit of each entry in the address section of the buffer memory.

All P■ flags are reset.

FIG. 5 shows the configuration of an embodiment of the address determination section which is the center of the present invention. When executing an instruction, the IU sets the address of the operand write reference request to Address Gen2.
2 is used to request the buffer memory, but at this time,
Register BFAR and comparison circuit? , 8, the addresses are compared.

BFAR contains the address and address of the block to be registered from the main memory to the buffer memory.

Three bits are held that indicate the address of the first two words needed as an operand.

These three bits of BF'AR are incremented by the increment circuit 29 as the block is registered in the buffer memory. The decoder circuit 3o decodes these 3 bits to create an 8-bit Pv flag register 310 set condition.

When the IU next issues an operand write reference request to the buffer memory, the 3 bits of the 2-word address within the block on the address line 22 are decoded by the decoder circuit 32, and further by the comparator circuit 33, the PV flag and register 310 are compared and decoder circuit 32
It is checked whether the PV flag corresponding to the on level of the eight signal lines taken out from is on.

As a result, the word of the address of the operand write reference request from the IU exists in the block currently being registered in the backup memory, and the PV flag and comparison circuit 3
If it is determined by step 3 that it has already been registered from the main memory to the buffer memory, the data line 24 in FIG. It is done.

As mentioned above, when executing an instruction that requires writing to a piece of main memory, a check is made to see if a block containing the operand exists in the buffer memory.

If the operand exists, the operand is written to both the backup memory and the main memory, but if the operand block does not exist in the buffer memory, the block is being registered from the main memory to the buffer memory. As described above, the comparison circuit 3 shown in FIG.
Judgment is based on 3.

If the comparator circuit 33 determines that the operand for which a write request is made exists in a word that has already been registered in the block that is being registered from the main storage device to the buffer memory, the comparison circuit 33 turns on the write enable signal and transfers the write-enabled signal to the buffer memory. Write to main memory. In other cases, writing is performed only to the main memory.

Although the above-described embodiment has been described as being based on a store-through type buffer memory system, it can be implemented in exactly the same way with a swap-type buffer memory system in which stores are always performed only on the buffer memory.

〔Effect of the invention〕

As described above, according to the present invention, operands can be written to words for which registration has already been completed within a block that has not yet been completely registered from the main memory to the buffer memory.

It is also possible to speed up the processing of a central processing unit having a buffer memory.

[Brief explanation of the drawing]

Figure 1 is a conceptual diagram of a buffer memory type information processing device.
FIG. 2 is an explanatory diagram of the structure of the buffer memory. FIG. 3 is a block diagram of an embodiment of a central processing unit based on the system of the present invention, FIG. 4 is an explanatory diagram of a PV flag, and FIG. 5 is a block diagram of an embodiment of an address determination section. In the figure, 6 is an instruction control unit IU, 15 is a register BFAR,
, 26 is a block, 27 is a PV flag, 28 and 33
29 is a comparison circuit, 29 is a step circuit, 30 and 32 are decoder circuits, and 31 is a P■ flag register. Patent applicant Fujitsu Ltd. Representative patent attorney Fumihiro Hase (1 other person)

Claims (1)

[Scope of Claims] In an information processing device having a buffer memory in the central processing unit that holds a copy of a part of the contents of the main memory, when a block is registered from the main memory to the buffer memory, the registration is blocked. and a second means for detecting that the word at the address of the write reference request of the operand exists in the block being registered from the main memory. . a third means for determining, by the first and second means, that the word of the address of the skin reference request of the operand has already been registered in the block in which it is being registered from the main memory; , furthermore, when it is determined by the third means that the word of the address of the evening reference request of the operand has already been registered from the main storage device onto the buffer memory, the writing of the operand is performed. 4. A buffer memory control method in an information processing apparatus, comprising: fourth means for performing reference.