JPS5990947A - Semiconductor device - Google Patents
Semiconductor deviceInfo
- Publication number
- JPS5990947A JPS5990947A JP57201454A JP20145482A JPS5990947A JP S5990947 A JPS5990947 A JP S5990947A JP 57201454 A JP57201454 A JP 57201454A JP 20145482 A JP20145482 A JP 20145482A JP S5990947 A JPS5990947 A JP S5990947A
- Authority
- JP
- Japan
- Prior art keywords
- resin
- impregnated
- semiconductor substrate
- insulating
- semiconductor device
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/552—Protection against radiation, e.g. light or electromagnetic waves
- H01L23/556—Protection against radiation, e.g. light or electromagnetic waves against alpha rays
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/484—Connecting portions
- H01L2224/48463—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/85—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a wire connector
- H01L2224/85909—Post-treatment of the connector or wire bonding area
- H01L2224/8592—Applying permanent coating, e.g. protective coating
Landscapes
- Physics & Mathematics (AREA)
- Health & Medical Sciences (AREA)
- Electromagnetism (AREA)
- Toxicology (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
Abstract
Description
【発明の詳細な説明】
産業上の利用分野
本発明は大規模集積回路メモリー装置において、その蓄
積信号計が、パッケージ材料中に含まれるウラン、トリ
ウム等から放出されるα線によって撹乱される、いわゆ
るソフトエラーを効果的に排除することができる構造の
半導体装置に関する。DETAILED DESCRIPTION OF THE INVENTION Field of the Invention The present invention relates to large scale integrated circuit memory devices whose storage signal meters are perturbed by alpha radiation emitted from uranium, thorium, etc. contained in the packaging material. The present invention relates to a semiconductor device having a structure that can effectively eliminate so-called soft errors.
従来例の構成とその問題点
半導体装置の製作するにあたり不可欠であるパッケージ
材料中には通常α線放出原子が含まれている。この原子
から放出されるα線のエネルギーは、平均して5MeV
程度といわれている。5MeV のエネルギーをもっ
たα線はノリコン中に約30ミクロンの深さまで入り込
み、そこで消滅する。この消滅までの間、α線は、シリ
コン中で電子・正孔対を発生させ、nチャンネル形のM
OSデバイスでは、このうちの電子が活性領域に集丑り
、誤動作の原因となる。この誤動作はソフトエラーと称
されている。この、α線によるソフトエラーを低減する
だめの方策として、従来d、半導体装置を構成するl荘
気回路もしくは、素−r構造を変えることによって行な
う方法、あるいは半導体素子の表面へ保獲膜を塗布する
方法がとられていだ4)前者は、例えば、ビット線の信
号量を大きくする回路方式、ワード線電圧を4二げる回
路方式、センスアンプの感度を上げる方式、あるいdl
、ノモリセルサイズを大きクシ7、容量を増大させる構
造をとることによってα線の影響を低減するものである
。まだ、後者は半導体素子の表面に保護膜を塗布するこ
とによって、α線が半導体素子の活性領域に到達するの
を防止するもので、保護膜の厚みをα線の侵入深さ以上
に選定し、α線を保護膜内で消滅させるようにした方法
である。この保護膜形成の/ξめに一般に使用される塗
布剤は、ポリイミド系樹脂、およびシリコーン系樹脂で
あり、ソフトエラーを防止するためには、いずれも30
ミクロン以上の塗布厚が必要とされる。Conventional Structure and Problems The package material, which is indispensable for manufacturing semiconductor devices, usually contains alpha-ray emitting atoms. The energy of the alpha rays emitted from this atom is 5 MeV on average.
It is said that the degree of The alpha rays with an energy of 5 MeV penetrate into Noricon to a depth of about 30 microns and disappear there. Until this extinction, the α rays generate electron-hole pairs in silicon, and the n-channel M
In an OS device, some of these electrons collect in the active region, causing malfunction. This malfunction is called a soft error. As a countermeasure to reduce soft errors caused by alpha rays, there are conventional methods by changing the air circuit or elemental structure constituting the semiconductor device, or by applying a retention film to the surface of the semiconductor element. 4) The former method includes, for example, a circuit method that increases the signal amount of the bit line, a circuit method that reduces the word line voltage by 4, a method that increases the sensitivity of the sense amplifier, or a method that increases the sensitivity of the sense amplifier.
The influence of alpha rays is reduced by increasing the size of the cell 7 and increasing the capacity. However, the latter method prevents alpha rays from reaching the active region of the semiconductor element by applying a protective film to the surface of the semiconductor element, and the thickness of the protective film is selected to be greater than the penetration depth of the alpha rays. This is a method in which α rays are extinguished within a protective film. The coating agents generally used for forming this protective film are polyimide resins and silicone resins, and in order to prevent soft errors, both
A coating thickness of microns or more is required.
ところで、ソフトエラー防止のだめ、半導体装置を構成
する電気回路もしくは素子構造を変更する対策方法には
、電気回路の変更にともない半導体装置の製作用マスク
に大幅な変更がもたらされること、あるいはメモリセル
サイズの増大による集積度の低下が生じることなどの不
都合があった。By the way, in order to prevent soft errors, countermeasures such as changing the electric circuit or element structure constituting a semiconductor device include making a major change in the mask for manufacturing the semiconductor device due to the change in the electric circuit, or changing the memory cell size. There were disadvantages such as a decrease in the degree of integration due to an increase in .
一方、保護膜を塗布する対策方法は、上記の対策方法に
くらべてはるかに簡便であり、しかも、上記のような不
都合もない。On the other hand, the countermeasure method of applying a protective film is much simpler than the above-mentioned countermeasure methods, and does not have the above-mentioned disadvantages.
第1図は、半導体素子の表面にソフトエラー防止用の保
護膜を塗布する従来の方法を説明するだめの図である。FIG. 1 is a diagram illustrating a conventional method of coating a surface of a semiconductor element with a protective film for preventing soft errors.
図示するように、半導体基板1をパッケージの基板接着
部2へ接着し、さらに半導体基板1上のボンディングパ
ノドと外部導出リードとの間を金線などの金属細線3に
より接続したのち、表面保護膜4を塗布、硬化させた構
造としている。なお、表面保護膜4の形成は、塗布剤と
してポリイミツド系樹脂あるいはシリコーン系樹脂を用
い、これを半導体基板1の表面に適准滴下させる塗布法
によって行う。As shown in the figure, after bonding the semiconductor substrate 1 to the substrate bonding part 2 of the package and connecting the bonding panode on the semiconductor substrate 1 and the external leads with thin metal wires 3 such as gold wires, the surface is protected. It has a structure in which the film 4 is applied and cured. The surface protective film 4 is formed by a coating method in which a polyimide resin or a silicone resin is used as a coating agent, and a suitable amount of the resin is dropped onto the surface of the semiconductor substrate 1.
ところでこの方法で塗布された塗布膜の断面形状は、は
ぼ円孤状を呈する。そして、例えば半導体基板1のサイ
ズを6ミリメ一ドル角程度にし、基板端縁から活性領域
までの距離aを200ミクロン程度にとった場合、塗布
膜厚t1 としてt1=30ミクロンが保たれるよう
に塗布したときの基板中央部での塗布膜厚t2は350
〜380ミクロンになる。この塗布膜厚t2r1、セラ
ミ、夕封止する場合のハノケージキャビティ深さ、ある
いは、樹脂封止する場合のバ、ケージ高さからみて、望
ま(〜い塗布膜厚とされる300ミクロンを超えており
、塗布膜厚t2を300ミクロン以下にする配慮が必要
である。By the way, the cross-sectional shape of the coating film applied by this method has a circular arc shape. For example, if the size of the semiconductor substrate 1 is about 6 mm square and the distance a from the edge of the substrate to the active region is about 200 microns, the coating film thickness t1 will be maintained at 30 microns. The coating film thickness t2 at the center of the substrate is 350
~380 microns. Considering this coating film thickness t2r1, the depth of the cage cavity when sealing with ceramic or resin, or the height of the cage when sealing with resin, the desired coating film thickness exceeds 300 microns. Therefore, consideration must be given to keeping the coating film thickness t2 to 300 microns or less.
もう一つの問題点は、基板中央部に滴下された樹脂は、
その表面張力作用によって、端面が基板周辺部まで拡が
りにくい点である。滴下後1時間以−にの放置時間をと
らなければならないこともある。背に、基板形状が長方
形の場合には、更に長時間を要することもある。更にも
う一つの問題点は、滴下量のコントロールが厄介な点で
ある。上記の基板サイズの場合の滴下量として、9.7
ミIJグラムないし10.3ミリグラムが適量であっ
たが、この値を越えた場合には、基板端部から塗布樹脂
が流出し、基板表面上に必要とされる厚みの保護膜を形
成することができず、一方、滴下量が少ない場合には、
基板端部に−1で樹脂が拡がらないなどの不都合が生じ
る。この1ミリグラム以下の滴下量のコントロールを定
常的に行なうには、ディスベンザ−の保守保全を確実に
行なう必要があり、これが製造工程における厄介な仕事
の一つとなるのであった。Another problem is that the resin dropped in the center of the board is
Due to the effect of surface tension, the end face is difficult to spread to the periphery of the substrate. It may be necessary to allow the solution to stand for one hour or more after dropping. On the other hand, if the substrate shape is rectangular, it may take even longer. Yet another problem is that it is difficult to control the amount of dripping. The dropping amount for the above substrate size is 9.7
The appropriate amount was 10.3 mg to 10.3 mg, but if this value was exceeded, the coating resin would flow out from the edge of the substrate and a protective film of the required thickness could be formed on the surface of the substrate. On the other hand, if the amount of dripping is small,
Inconveniences occur such as the resin not spreading at the edge of the substrate at -1. In order to regularly control the amount of drops of 1 milligram or less, it is necessary to maintain the dispenser reliably, which is one of the troublesome tasks in the manufacturing process.
発明の目的
本発明は、塗布すべき樹脂をあらかじめ含浸させた絶縁
布によって、半導体基板の活性領域上を被覆する構造と
することによって、表面保護膜形成のだめに樹脂を塗布
するようにした従来の方法で生じた塗布膜厚のばらつき
、あるいは、樹脂滴下量のコントロールのだめの塗布作
業上の問題などを排除するようにした半導体装1σの提
供を目的とするものである。′
発明の構成
本発明の半導体装置は、半導体基板の少くとも活性領域
上を、樹脂を含浸させた絶縁布で被覆した構造に特徴を
有するものであり、ソフトエラー防止用の表面保護膜の
厚みの制御を容易にするばかりでなく、表面保横膜の形
成作業を17i1略化することもでき、本発明によれば
十分なソフトエラ一対策の施された半導体装置が実現さ
れる。OBJECTS OF THE INVENTION The present invention has a structure in which the active region of a semiconductor substrate is covered with an insulating cloth pre-impregnated with the resin to be applied, thereby improving the conventional method of applying the resin before forming a surface protective film. The object of the present invention is to provide a semiconductor device 1σ which eliminates problems caused by the coating process such as variations in coating film thickness or problems in coating operations such as difficulty in controlling the amount of resin dripped. 'Structure of the Invention The semiconductor device of the present invention is characterized by a structure in which at least the active region of the semiconductor substrate is covered with an insulating cloth impregnated with resin, and the thickness of the surface protective film for preventing soft errors is The present invention not only facilitates control of the process, but also simplifies the process of forming the surface horizontal preservation film, and the present invention realizes a semiconductor device with sufficient measures against soft errors.
実施例の説明
本発明の半導体装置では、ポリイミド樹脂、あるいに1
、/リコーン樹脂等の高分子樹脂を直接半導体基板上に
滴下塗布した構造にかえて、高分子樹脂を含浸させた絶
縁布を所定の寸法に裁断し、この絶縁布を半導体基板上
の活性領域に位置合わぜして被覆した構造をとる。この
絶縁布の構成要素である含浸用の高分子樹脂は常温にお
いて液状を呈し、絶縁布に含浸させた後、加熱処理によ
って、半硬化状態となり、この状態で所望の形状に加工
され、半導体基板上を被覆した後に熱処理を行なうこと
によって、完全に硬化するたとえばビスフェノールタイ
プのエポキシ樹脂などの樹脂であることが工業的には最
も望ましい。また、絶縁布は、合成樹脂繊維の織布が使
い易さの点ではすぐれているが、必ずしも織布である必
要はない。DESCRIPTION OF EMBODIMENTS In the semiconductor device of the present invention, polyimide resin or 1
,/Instead of a structure in which a polymer resin such as silicone resin is applied dropwise directly onto a semiconductor substrate, an insulating cloth impregnated with a polymer resin is cut to a predetermined size, and this insulating cloth is applied to an active area on a semiconductor substrate. It has a structure in which it is aligned and coated. The impregnating polymer resin, which is a component of this insulating cloth, is liquid at room temperature, and after being impregnated into the insulating cloth, it is heated to a semi-hardened state. Industrially, it is most desirable to use a resin such as a bisphenol type epoxy resin, which can be completely cured by heat treatment after being coated. Further, as the insulating cloth, a woven cloth made of synthetic resin fibers is excellent in terms of ease of use, but it does not necessarily have to be a woven cloth.
さらに、含浸用の高分子樹脂は、350’Cの温度で1
11Jr間以内に完全硬化する!1!j性を具備してい
るものであることが望ましく、4寺に150℃、30分
程度の硬化条件の下で完全硬化するものであれば申し分
ない。このような高分子樹脂を含浸させた絶縁布を用い
るならば、半導体装置は、組立てに際して使用される材
料と、半導体基板との熱膨張係数は必ずしも適合したも
のではないが、硬化のだめの熱処理によって機械的破壊
あるいは電気的特性の劣化が生ずるおそれIrlない。Furthermore, the polymeric resin for impregnation is
Fully cures within 11Jr! 1! It is desirable that the material has high properties, and it is satisfactory if it can be completely cured under four-temperature curing conditions of 150° C. for about 30 minutes. If an insulating cloth impregnated with such a polymer resin is used, the semiconductor device can be assembled by heat treatment during curing, although the thermal expansion coefficients of the materials used during assembly and the semiconductor substrate do not necessarily match. There is no risk of mechanical damage or deterioration of electrical characteristics.
第2図および第3図は本発明で用いる絶縁布と上述した
構造を有する本発明の半導体装置の具体的な構造を例示
する断面図である。FIGS. 2 and 3 are cross-sectional views illustrating the specific structure of the insulating cloth used in the present invention and the semiconductor device of the present invention having the above-described structure.
以下に第2図および第3図を参照して本発明について詳
しく説明する。第2図で示す絶縁布5は素材である直径
約100ミクロンのナイロン糸6で織った絶縁織布に、
たとえば、ビフェノールタイプのエポキシ樹脂と硬化剤
とを混合さWた含浸剤7を含浸させ、これを表面採掘す
るべき半導体基板1の活性領域のXJ法に合せて裁断し
て形成されている。第3図は、この絶縁イiJ5で半導
体基板1の表面トを被覆しだ状態を示す図であり、金線
+Mll線3による電極接続寸でか終了した半導体装置
組立構体を約150℃に加熱した状態で半導体基板1の
表面上を被覆して形成されている。ところで絶縁織布に
樹脂を含浸させ、これを加熱、冷却し、含浸樹脂を半硬
化状態にして形成した絶縁布を用い、J二記の温度条件
で加熱被覆すると、含浸樹脂が一担溶融する。そして、
更に等温加熱をつづけることによって、硬化反応がすす
み、約30分で硬化する。この溶融時に、含浸樹脂は半
導体基板端面に向って流れ出す。この結果、第3図で示
すように、端部近傍でゆるやかに傾斜した樹脂面ができ
る。このようにして形成された表面保穫膜の半導体基板
中央部の厚さt2′は、はぼ絶縁布5の厚さによって決
定され、2oo〜250ミクロンの厚さになる。まだ、
半導体基板の端縁がら基板活性領域までの距離aの範囲
内における樹脂の厚さt1′も50ミクロン程度に保た
れる。すなわち、半導体基板上の全域にわたって、α線
によるノットエラー効果を防ぐに足りる厚さの保護絶縁
膜で覆われ、しかも、厚みの最大値がパッケージングに
支障をきだすことのない値とされた半導体装置が形成さ
れた。The present invention will be explained in detail below with reference to FIGS. 2 and 3. The insulating cloth 5 shown in FIG.
For example, it is formed by impregnating it with an impregnating agent 7 that is a mixture of a biphenol type epoxy resin and a curing agent, and cutting it in accordance with the XJ method of the active region of the semiconductor substrate 1 whose surface is to be excavated. FIG. 3 is a diagram showing the state in which the surface of the semiconductor substrate 1 is coated with this insulating iJ5, and the semiconductor device assembly structure, which has been completed with the electrode connection dimension using the gold wire + Mll wire 3, is heated to about 150°C. It is formed by covering the surface of the semiconductor substrate 1 in this state. By the way, when an insulating cloth is impregnated with a resin, heated and cooled, and the impregnated resin is semi-hardened, the insulating cloth is heated and coated under the temperature conditions specified in J2, the impregnated resin melts once. . and,
By further continuing isothermal heating, the curing reaction progresses and the film is cured in about 30 minutes. During this melting, the impregnated resin flows out toward the end surface of the semiconductor substrate. As a result, as shown in FIG. 3, a gently sloped resin surface is formed near the end. The thickness t2' of the surface protective film thus formed at the center of the semiconductor substrate is determined by the thickness of the insulation cloth 5, and is 200 to 250 microns thick. still,
The thickness t1' of the resin within the distance a from the edge of the semiconductor substrate to the substrate active region is also maintained at about 50 microns. In other words, the entire area on the semiconductor substrate was covered with a protective insulating film thick enough to prevent the knot error effect caused by alpha rays, and the maximum thickness was set to a value that would not cause any problems with packaging. A semiconductor device was formed.
発明の効果
本発明によれば、パッケージ利料から放出されるα線が
半導体基板の表面にまで到達することを防止するだめの
保護絶縁膜の厚さが、少くとも活性領域上の全域でほぼ
均一とされた半導体装置が実現され、ソフトエラーの発
生が効果的に防止されるところとなり、半導体装1δの
信頼性が飛躍的に向上する効果が奏される。Effects of the Invention According to the present invention, the thickness of the protective insulating film that prevents α rays emitted from the package material from reaching the surface of the semiconductor substrate is approximately equal to at least the entire area over the active region. A uniform semiconductor device is realized, the occurrence of soft errors is effectively prevented, and the reliability of the semiconductor device 1δ is dramatically improved.
まだ、保護絶縁膜の厚みが所定値以下の均一な厚みとな
るだめ、パッケージングに際して不都合をきだすことも
ない。However, as long as the thickness of the protective insulating film is uniform and less than a predetermined value, there will be no inconvenience during packaging.
第1図は従来方法によって製造されたソフトエラー防止
用の保護絶縁膜をもつ半導体装置の半導体基板部の断面
図、第2図は本発明の半導体装置で使用する絶縁布の構
成状態を示す図、第3図は本発明の半導体装置の半導体
基板部の断面図である0
1・・・・・・半導体基板、2・・・・・・基板接着部
、3・・・・・・金属細線、4・・・・・・表面保護膜
、5・・・・・・絶縁布、6・・・・・・ナイロン糸、
7・・・・・・含浸剤(樹脂)。FIG. 1 is a cross-sectional view of the semiconductor substrate portion of a semiconductor device having a protective insulating film for preventing soft errors manufactured by a conventional method, and FIG. 2 is a diagram showing the configuration of an insulating cloth used in the semiconductor device of the present invention. , FIG. 3 is a cross-sectional view of the semiconductor substrate portion of the semiconductor device of the present invention. , 4... Surface protective film, 5... Insulating cloth, 6... Nylon thread,
7... Impregnating agent (resin).
Claims (3)
を含浸させた絶縁布よりなる保護絶縁膜で被覆したこと
を特徴とする半導体装置。(1) A semiconductor device characterized in that at least an active region of a semiconductor substrate is covered with a protective insulating film made of an insulating cloth impregnated with resin.
成されていることを特徴とする特許請求の範囲第1項に
記載の半導体装置。(2) The semiconductor device according to claim 1, wherein the insulating cloth is formed by impregnating a synthetic fiber woven cloth with a resin.
ることを特徴とする特許請求の範囲第1項に記載の半導
体装置。(3) The semiconductor device according to claim 1, wherein the semiconductor substrate is a large-scale integrated circuit memory element substrate.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP57201454A JPS5990947A (en) | 1982-11-16 | 1982-11-16 | Semiconductor device |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP57201454A JPS5990947A (en) | 1982-11-16 | 1982-11-16 | Semiconductor device |
Publications (1)
Publication Number | Publication Date |
---|---|
JPS5990947A true JPS5990947A (en) | 1984-05-25 |
Family
ID=16441355
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP57201454A Pending JPS5990947A (en) | 1982-11-16 | 1982-11-16 | Semiconductor device |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS5990947A (en) |
Citations (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
WO2007008848A2 (en) * | 2005-07-07 | 2007-01-18 | Seattle Genetics, Inc. | Monomethylvaline compounds having phenylalanine carboxy modifications at the c-terminus |
JP2007514652A (en) * | 2003-11-06 | 2007-06-07 | シアトル ジェネティックス, インコーポレイテッド | Monomethylvaline compounds that can be conjugated to a ligand |
JP2010523469A (en) * | 2007-03-30 | 2010-07-15 | ジェネンテック, インコーポレイテッド | Antibodies and immunoconjugates and methods for their use |
-
1982
- 1982-11-16 JP JP57201454A patent/JPS5990947A/en active Pending
Patent Citations (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2007514652A (en) * | 2003-11-06 | 2007-06-07 | シアトル ジェネティックス, インコーポレイテッド | Monomethylvaline compounds that can be conjugated to a ligand |
WO2007008848A2 (en) * | 2005-07-07 | 2007-01-18 | Seattle Genetics, Inc. | Monomethylvaline compounds having phenylalanine carboxy modifications at the c-terminus |
JP2010523469A (en) * | 2007-03-30 | 2010-07-15 | ジェネンテック, インコーポレイテッド | Antibodies and immunoconjugates and methods for their use |
Non-Patent Citations (2)
Title |
---|
JPN6015051113; Bioconjugate Chem., 2008, Vol.19, pp.1960-1963 * |
JPN6015051114; Bioconjugate Chem., 2006, Vol.17, pp.114-124 * |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
US2758261A (en) | Protection of semiconductor devices | |
US4637130A (en) | Method for manufacturing a plastic encapsulated semiconductor device and a lead frame therefor | |
US4470063A (en) | Copper matrix electrode having carbon fibers therein | |
US4201598A (en) | Electron irradiation process of glass passivated semiconductor devices for improved reverse characteristics | |
EP0029858B1 (en) | Semiconductor device | |
US4210464A (en) | Method of simultaneously controlling the lifetimes and leakage currents in semiconductor devices by hot electron irradiation through passivating glass layers | |
US4240844A (en) | Reducing the switching time of semiconductor devices by neutron irradiation | |
JPS5990947A (en) | Semiconductor device | |
JP3065753B2 (en) | Resin sealing method for semiconductor integrated circuit bare chip, semiconductor device | |
JPS5645060A (en) | Semiconductor device | |
JPS5790966A (en) | Semiconductor device | |
JPH10270602A (en) | Electronic circuit device, method of forming sealing layer thereof, circuit board and die for forming the sealing layer | |
JPS5848950A (en) | Semiconductor device and its manufacture | |
JPS5776868A (en) | Forming method for resin protected film | |
JPS58124251A (en) | Resin-sealed type semiconductor device | |
JPH07302809A (en) | Resin sealing type semiconductor device and its production process | |
JPS5887834A (en) | Resin sealing of semiconductor device | |
JPS60245260A (en) | Semiconductor element | |
JPS6097672A (en) | Semiconductor device and manufacture thereof | |
JPH01133328A (en) | Sealing of semiconductor element | |
JPS6224650A (en) | Semiconductor device | |
JPS61236871A (en) | Adhesive | |
JPS6332267B2 (en) | ||
JPS5816553A (en) | Semiconductor device and manufacture thereof | |
JPS5999747A (en) | Semiconductor device |