JPS59502047A - Semiconductor epitaxial phase and growth method with controlled defect concentration cross section for mixed epitaxial semiconductors on insulating mixed substrates - Google Patents

Abstract

(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

[Detailed description of the invention] Semiconductor epitaxial phase and growth for mixed epitaxial semiconductors on insulating mixed substrates The present invention generally relates to silicon-on-sapphire (SOS), etc. is another type with an epitaxial layer of silicon single crystal and a sapphire substrate. The impurities in the original substrate, such as the aluminum used, can be This paper relates to the production of semiconductors on insulating mixed substrates with highly controlled surface defects.

2. Description of conventional technology It has the advantage of usability. It consists of a single crystal semiconductor layer such as silicon and is placed on an insulating substrate. Epitaxial precipitation of mixed substrates is well known.

Such utilization substantially reduces stray capacitance between the active area and the substrate. , thereby eliminating leakage currents flowing between adjacent active devices. effect can be obtained.

Then, the substrate is made of an insulating material such as sapphire (Al2O3), which is a strong, high-density R material. It can serve the purpose of being used as a It is also possible to provide a conductive path through which the current flows.

At present, conventionally planned and actually realized on a mixed board.

Ideal silicon-on-insulators have failed due to several significant problems. most Simply put, an ideal mixed substrate is a perfect single crystal, free of defects, and has no active elements. Any silicon layer may be used as long as it is thick enough to accommodate the manufacturing process. This silicon layer is a substrate that is kept in a highly insulated state from its neighbors, and that is Discontinuities in the crystal lattice are minimal.

To give an overview below, a mixed substrate with extremely mixed phases, including defects in the cross section of the concentration, in particular. is superior in terms of simplicity and is an ideal mixed board.

Historically, the first major problem was adding impurities to silico.

An epitaxial layer is deposited on top of the main layer to form a step intended for the assembly of an ideal mixed substrate. It happened on the floor.

In particular, when using an Al2O3 substrate, the concentration of aluminum impurities is Sometimes it passed through the epitaxial layer. Essentially, a high concentration of aluminum As a result of using impurities in the silicon epitaxial layer, the impurities are of the type of additives. MO3FETs (Metal Oxide) 3emiconductor Field Effect Transistor ) and MESFETS (Metal Sem1 conductor FET) unwelcome leakage current between the source and drain regions of a P-channel active device. will occur. Such leakage current always causes the above P-channel active element to Large enough to turn on or conductive. Original substrate silicon The amount of impurities incorporated into the layer is based on the inherent consequences of the high temperature process steps. this The typical utility of the steps is the initial deposition of the epitaxial layer on the silicon layer and the subsequent By tempering the crystalline silicon layer contained within itself. In this way, mainly Trials and failures have shown that the silicon layer of the original substrate is not substantially enriched with impurities. The highest efficacy was observed at a treatment temperature of approximately 910°C.

In practice, it was immediately understood that the second problem was preventing high-temperature tempering. Good morning. The single-crystal quality of the silicon layer due to epitaxial deposition is due to the fact that there are no active elements in it. The quality is insufficient for assembling the child. Recently, solid phase epitaph A method called EPE is known. ”　A　OI)lierj　P hysics Letters,” Vol, 34, No. 1.1) p., 76-7 8. January 1979, “Ion Implantation Handbook” by S. S. Lau et al. An improvement in the single-crystal quality of the epitaxial silicon layer due to the steps is observed. SEP The process is an epitaxial silicon layer on a silicon-on-sapphire mixed substrate. Provides a low temperature sub-process to improve single crystals. The SEP process is , leaving a substantially single-crystalline layer on the surface of the original epitaxial layer. The ion-driven silicon layer forms a substantially amorphous silicon layer near the fire boundary. Ion implantation of silicon and silicon epitaxial layers (from 250 KeV as a typical value) 600KeV). The thickness of the silicon epitaxial layer is essentially silicon -On-insulator composite board (typically 4000 or more) Become. Since most of the ions are implanted through the epitaxial layer, The sapphire layer is in the amorphous region following the silicon/sapphire boundary. The splitting is greatest near the lattice of the con crystal. During ion implantation, the sapphire substrate is Liquid nitrogen (kept at a low temperature of about 77', K). Single stage low temperature Tempering of the composite substrate at a Convert to Recon single crystal. During this regeneration period, the surface of the remaining single crystal silicon layer The regenerated portion of the silicon epitaxial layer is , it has a general crystallographic arrangement and virtually no crystal defects occur.

Fabrication of silicon-on-insulator composite substrate during SPE process In this subprocess, impurities are added to the original insulator of the silicon epitaxial layer. The ease of mixing is an important improvement in crystallinity. The concentration of impurities is SP This is the result of executing the E process, and unfortunately, on a composite substrate by the SPE process. The production of integrated circuits would be sufficiently impeded to practical use. active elements are working properly. The reason for the defective products is essentially the high temperature in the composite board manufacturing process as mentioned above. process steps.

Another advantage of the invention is that the following summary description may be considered a multiple reference to portions of the form. clearly and easily recognized by

Figure 1 is a cross section showing an insulating substrate and the epitaxial deposition of a silicon layer on its surface. figure, Figure 2 is similar to Figure 1 with an amorphous embedded silicon layer formed on the silicon layer. The cross-sectional view of the composite substrate shown in Figure 3 shows the removed boundary of the amorphous layer centered on Rp. A hypothetical graph showing the implanted ion concentration versus the depth from the surface of the silicon layer, showing one The boundary is adjacent to the surface of the insulator and the amorphous layer corresponds to that in FIG. Figure 4 shows the composite shown in Figure 1 in which amorphous embedded silicon is formed within a silicon layer. In the cross-section of the substrate, the amorphous layer has an absolute thickness corresponding to the remaining thickness of the crystalline silicon boundary layer. away from the edge board, Figure 5 shows the removed boundary of the amorphous layer shown in Figure 4, and shows the implanted ion concentration versus silicon An ideal graph of the depth just below the surface of the epitaxial layer shows how the ions are implanted. Figure 6 shows the self-sealing and virtual self-sintering surface of the composite substrate shown in Figure 2. A cross section showing an increase in thickness from an amorphous buried silicon layer to a silicon insulating substrate boundary. figure, Figure 7 shows the initial annealing/regrowth of embedded amorphous silicon on the composite substrate shown in Figure 2. A cross-sectional view showing the generation of seeds for regrowth of a crystalline silicon surface layer using a thin layer. Engraving (Contents, G,: Changed. Z L) G ”Omote 1984-” O2” 7(4) No. Figure 8 is a cross-sectional view showing a fully regenerated buried silicon layer, and Figure 9 is a cross-sectional view showing a fully regenerated buried silicon layer. The ridges on the surface of the crystalline silicon layer are shown after the remnants of the adjacent regrown crystalline silicon layer have been removed. A cross-sectional view of the composite substrate in Figure 8, FIG. 10 includes a second epitaxially deposited silicon layer of the regrown crystalline silicon layer. A cross-sectional diagram showing the complete composite substrate, Figure 11, shows a thin partial burnout adjacent to the insulating substrate. MESFE fabricated on the island-shaped part of the silicon boundary layer with torsion or remaining defects Cross-sectional view showing an ideal active display such as T Disclosure of the invention The present invention provides insulation for composite substrates, which is desired for use in the production of high-speed semiconductor circuits. providing a single crystal layer of semiconductor on the surface of the portion. The process is semiconductor and A wide variety of variations in insulation can be made in nature. like this U.S. Patent No. 3,393,088 (Silicon on α-aluminum oxide) Con), U.S. Patent No. 3,414,434 (Silicon on Spinel Insulator); U.S. Patent No. 3.475°209 (Gold Curb Silicone), U.S. Patent No. 3 , 664.866 (Jib-■a semiconductor compound on an insulating substrate).

For the purpose of clarifying the following assertion, silicon is, for example, a semiconductor material. (Al2O2) is used as an insulator, for example. Therefore, the following The examples in this specification are merely representative of the many attempts made with the present invention.

In FIG. 1, the silicon layer 12 is connected to the sapphire substrate 10 of the composite substrate 10.12. The epitaxial layer is shown as being deposited on top. To prepare the substrate 10, Techniques for depositing taxial layers are well known. U.S. Patent No. 3,508, 962, U.S. Patent No. 3, 546, 036 and J. C. Don et al. “Journal of Applied Physi C5, Vol. 50 ．． No, 2. pp, 881-885. February 1979. to°′amorphous Laser epitaxy of quality silicon substrate and doping effects are observed. It will be done.

The sapphire substrate 10 has a thickness of 10 to 13 mils, and the crystal axes on the surface are arranged in ( 1102) (hexagonal system mirror index notation) is preferably within 1°. like this In the special crystal arrangement, the crystal axis arrangement is (100) (regular hexagonal system mirror index notation) This method is necessary for the epitaxial growth of silicon layers.

Silicon epitaxial @12 is characterized by the arrangement of crystal axes on the surface, as outlined below. It is desirable to have columns (100). First silicon epitaxial layer 12 is deposited on the surface of the sapphire 10, preferably by chemical vapor deposition (CV). This is due to step D). Formation of the epitaxial layer 12 by this CvD He measured the appropriate reaction by chemical decomposition of silicon hydroxide (Sit-1+) using an incandescent pyrometer. It is desirable to measure at approximately 910°C (errors included). Silicon E The epitaxial thickness is preferably between 1000 and 2500, so the epitaxial The growth rate of Char is about 0.3 to 2.4 InrL/min, preferably 2.4 InrL/min. It is. The minimum film thickness is such that it facilitates the manufacture of composite substrates io, i2. A film of silicone having a substantially uniform surface is applied continuously with sufficient pressure to Must come. The best minimum thickness is 1000, silicone/saf As a result of the defects at the wire boundary, the impact on the manufacturing of composite substrates is initially very small. In the early stages of epitaxial deposition, the degree of distortion corresponds to the experimental Decide accordingly. The best maximum thickness is 2500 people, outlined below. It is determined based on the reason. The best epitaxial growth rate is 2.4 pm 7 min. Selected from low growth rates resulting in the lowest density of flaws in the silicon at the silicon/sapphire interface. I am choosing. This low growth rate allows a high concentration of scratches, making sapphire a typical type. A matrix formed in the initial part of the silicon layer 12 of the epitaxial layer on the surface 60 of There is an icrotwin-shaped scar.

The second reason to choose the best low growth rate is that the silicon/sapphire composite substrate is Since it is manufactured to meet each requirement of Union Carbide, NC, 8888 Balboa Ave.

San Diego, CA92123 crystal layer M part C is available for commercial production. It is for use.

With reference to FIG. 2, the present invention is shown as being essentially equivalent to an ideal composite substrate. The first important example will be explained. Ion 18 is exposed to silicon 12a. Amorphous silicon covered with a substantially crystalline silicon layer 16 by implanting through the surface The silicon layer 14 is made to have a high quality. Silicon epitaxial layer 12a A preferred method for eliminating undesirable impurities in the silicon crystal layer on the surface of On is silicon. Other preferred inert ions include argon and neon is used as appropriate.

In order to strictly achieve the purpose of an ideal composite substrate, the energy of ion implantation is , strictly controlled to form the amorphous layer 14 directly adjacent to the sapphire substrate 10. must be controlled. As shown in Figure 3, the implanted ions It shows a statistical distribution in which the center of the distance Rp directly below the pitaxial layer 12a is the maximum. vinegar. The distribution ΔR1) of the lapel-like pot difference of the injected ions with respect to Rp and Rp is Depending on the type of semiconductor material and the implanted ions. Rp and △Rp are also 18 Post H59-502047 (5) is proportional to the implantation energy, so both increase as the implantation energy increases. do. Silicon ions as well as various standard ion and semiconductor material combinations is injected into silicon material with various energies, and the values Rp and △Rp are determined and tabulated. Ta. J.F., Mr. Gibbons, W.F., Mr. Johnson, S.W.

Mr. Miller, “projectecl　Ranqi　5tatiatics , 2 ed, Haistead Press 3troudfburg 197 5. is shown.

The maximum collapse of the structure of the silicon crystal lattice occurs at the maximum implanted ion concentration from Rp. and its depth is just below the exposed surface of epitaxial layer 12a.

However, a sufficient number of ions must be present to collapse and thereby become amorphous. The silicon layer 12a is implanted with silicon to make the arrangement of the silicon layer 12a substantially symmetrical around Rp. There must be. Originally, the width of the amorphous layer is determined by the given implantation energy. , corresponding to the increase in the amount of ions (ion amount/unit in the surface area) during implantation, Substantively dependent and increasing. Increasing the implantation energy broadens the distribution of ion implantation, Thereby, the desired large amount of ions can maintain or increase the width of the amorphous layer. Let's do it.

In the present invention, the implantation energy and the amount of ions given are selected. , if it is not perfect, the amorphous layer 14 formed near Rp will be approximately Rp-1,5Δ It spreads from Rp to R,l)+1°5△Rp. In the present invention, the implantation energy and The amount of on required to achieve the amorphous width is approximately 3 times the constant. can be easily obtained. Sapphire layer 10/¥ The thickness of the initial silicon crystal layer is approximately R to form an amorphous layer 14 in close proximity to p+1,5ΔRp. The key to seeing the invention clearly with respect to the prior art is the above note. The input energy and the amount of ions are the concentration threshold at which the sapphire substrate 10 becomes a defective product. The reason is that it is forced to be low enough so that it does not exceed. Crystalline material becomes defective item The concentration is the amount of ions penetrating the surface of the crystal, and the period of the average energy of the penetrating ions. For the time being, it is limited here. Concentration that causes defects in various crystalline insulating materials The threshold value of is determined in an experimental process. This kind of thing is M, w, Tompso '[)ifects and Radio Damage i n fvleta l s,” Cambridge University Press, Cambr., Mass., 1969. sa The experimentally determined concentration threshold for fire failure is estimated at the surface of sapphire. approximately 1×10 ke-ions/ctj.

The threshold value of the defect concentration of sapphire during the period of forming the amorphous layer 14 is determined by the crystallization of sapphire. This is due to defects in the region near the crystal boundary 60.

It is believed that this defect is caused by highly mobile AlO2 fragments in Sapphire 10. be lost. Boundary region between epitaxial silicon layer and sapphire layer 10 As a result of the defect, the diffusion of the defect increases or the current and next process step ``Gettering'' occurs even though the temperature is low.Mobility High AlO2 diffuses from the sapphire substrate 10 to the epitaxial silicon. It enters the conductive layer 12a and becomes an effective impurity. Ion implantation energy and ion number/, S′″ The number of trade-off balances between and ■ the thickness of the bitaxial layer 12 is substantially The amorphous layer 14 is formed with sapphire groups without exceeding the defect concentration of sapphire 1o. It must be formed close to the plate 10. Amorphous silicon layer 14 to provide maximum sapphire defect concentration without exceeding the threshold concentration of sapphire defects. The thickness of Recon Sou 12a is approximately 2,500 people. maximum injection energy and The number of ions is that+r corresponding to approximately 90±10Ke and 2X10 ions/d, respectively, which is substantially less than that prescribed by the prior art.

For example, a composite substrate such as that shown in Figure 2 may be made of a sapphire substrate approximately 10 mils thick. Manufactured using an epitaxial deposited layer of 2000 ± 10% thickness on the surface. . Silicon ions with an energy of about 55 Ke form the epitaxial silicon layer 1. 2a, the number of ions perpendicular to the exposed surface is 1X10 ions/ Run with ci. While performing this ion implantation, the back surface of the sapphire substrate is maintained at a constant value below 20°C. Temperature control and the reason for its special value This will be discussed in the overview below.

A second embodiment of the present invention will be described with reference to FIG. This example essentially consists of: It is made of a crystalline material, and is formed between the amorphous silicon layer 22 and the sapphire substrate 10. The remaining defects provided by the sandwiched silicon/sapphire interface 60 The boundary layer 20 of the silicon crystal is formed by implanting heavy ions as shown in Figure 2. There is a difference in that. This structure is lρ Injecting ions 26 into the silicon of the epitaxially deposited silicon layer 12b. This is achieved by Most of the surface layer 16 of the epitaxial layer 12b is The epitaxial layer 12b is made substantially crystalline while being amorphous by heavy ion implantation. It remains crystalline. Although the implant energy is controlled, such thin residual The remaining layer 20 is insufficient for implantation to make it amorphous. implanted ions The concentration cross section corresponds to a composite substrate as shown in FIGS. 4 and 5. The cross section is substantial symmetrically, centered around the maximum implanted ion concentration, the exposed silicon layer 1 The depth is Rp from the surface of 2b. With proper injection, amorphous Layer 22 extends from approximately R1)-1,5ΔRp to Rp+1.5ΔRp. epitaxy The thickness t of the silicon layer 12a is larger than Rp+i and 5ΔRp. consequential The remaining thin silicon layer 20, which has been heavily implanted, is thereby substantially There are several crystal scratches between the sapphire substrate 10 and the amorphous silicon layer 22. Effectively sandwiched, layer 20 has a width of approximately t-Rp+1.5ΔRp.

The preferred remaining boundary layer width is about 200±1 oo. Originally, this prepared The thin, missing boundary layer 20 increases the thickness t of the epitaxial silicon layer 12b. The width of the amorphous layer 22 can be reduced by reducing Rp and reducing the ion implantation energy. The number of ions is reduced by reducing the number of ions, or a combination of these is generated. one As a special result, the epitaxial silicon layer 12b and the sapphire substrate 1 The remaining missing boundary 20 prepared at the boundary with 0 is slightly removed from the remaining layer 2° The maximum pitaxial layer 12b thickness, implantation energy, and The ion dose can all be increased as described above. More results below This is explained in the overview.

Of the configurations provided by the processes of the two main embodiments of the invention described above, the maximum The deformation of is by controlling the temperature of the substrate. This modification ultimately leads to silicon/ Partially annealing the defective silicon crystal boundary layer at the sapphire boundary 60 It's there. As shown in FIG. The process for composite substrate 10.12 of Example is applied. Ion 58 is a good In the preferred silicon, the epitaxially deposited silicon on the surface of the sapphire substrate 10 is In this example, ions were implanted into the contact layer 12C. During ion implantation, sapphire The backside surface of the substrate 10 maintains a particularly high controlled temperature. this is sapphire This can be achieved by attaching a heat sink (not shown) to the substrate 10. Thin flap Film temperature paste or a thin film of silicone is applied to the heat sink and sapphire. It is useful because it can provide high thermal conductivity as an interface between the Ru. Using thermal paste in this manner is a well-known technique. Ru. Using silicon heat dissipation layer, thin uniform silicon layer prevents uneven temperature pace The relative thickness of the composite substrate 10 to the film is optimal from the point of view of heat conduction. ．． 12c in subsequent process steps, especially in ion implantation. It can be positioned accurately. Does the silicon layer have high thermal conductivity? The interface layer of the silicon heatsink may have an appropriate thickness. Furthermore, this The interface layer is deposited epitaxially on the back surface of the sapphire substrate at the appropriate time. can be deposited, and epitaxially applied to the silicon layer on the back side of the previous sapphire substrate 10. As deposited, the thermal interface layer is resistant to relatively low levels of impurities. I'll get a higher portion. During ion implantation, the temperature of silicon layer 132C increases substantially. , which reacts with respect to the back surface of the substrate 10 to absorb ion implantation energy. Ru. Due to the thickness of the silicon layer 12G and the inherent high thermal conductivity of silicon, silicon The temperature of the contact layer 12C can be considered to be essentially uniform. relatively safe The lower thermal conductivity of the sapphire substrate, combined with its greater thickness, makes the sapphire Temperature gradient in the substrate (typical value 150 & -200℃) of silicon/sapphire It increases from the surface 62 on the back side of the boundary 60. The temperature of the silicon layer 12G is The ion implantation of the implanted ions 58 is performed by changing the amount of energy given to the layer 12G. by changing the energy and/or ion dose. can be made into This can be achieved by further changing the ion dose rate. This can be accomplished by changing the energy applied to the silicon layer 12c. . Controlled by heat sink (not shown): temperature regulation and sapphire The choice between the two surfaces of the back side of the band 10 is to change the temperature of the silicon layer 12c. I can do it. The high temperature of the silicon layer 12G causes partial annealing of the silicon boundary layer. A silicon/sapphire boundary layer 60 is formed by allowing the process to proceed. Figure 6 shows a number of results. A self-tempering layer 30 containing crystal defects, in other words damaged and amorphous It is formed partially on the epitaxial silicon layer 12C to be Ru.

During the initial period of ion implantation, maximum collapse of the crystal lattice and initial partial heating or silicate This occurs at a depth R1) directly below the exposed surface of the contact layer 12G. Provided like this The heating increases the temperature of the silicon molecules at a depth of about Rp to an average temperature of about 150°C or Raise the temperature sufficiently higher than that and virtually temper it above and below Rp of the silicon crystal lattice. occurs. A thin, self-tempering layer 30 under Rp is at the silicon/sapphire interface. effectively increases in the direction of layer 60. This is an ion for a pseudo-amorphous point. The self-tempering layer directly beneath the silicon layer 32 is increasingly damaged by the implantation of It happens at 30. The self-tempering layer 30 acts to seed a pseudo-amorphous layer. , the lower boundary of the self-tempering layer 30 is directed toward the silicon/sapphire boundary 60. grow effectively. The upper boundary of the self-tempering layer 30 is similarly increases towards the boundary 60 of the fire. This upper boundary regression is equivalent to Rp. The self-tempering layer 30 is continuously implanted symmetrically and continuously. Particularly its upper boundary collapses due to partial tempering of the silicon crystal. Gradually crystallizes. As a result, a thin, self-tempering boundary layer 30 forms an amorphous layer 1 4a to the silicon/sapphire boundary 6o or a certain width. It increases until a substantial crystalline layer, such as the stabilized remaining boundary layer 20, is reached. Rp's The self-tempering boundary layer formed directly on the -20th Although not shown in Figure 6, the remaining series from the previous fully qualified representative layer Crystalline/amorphous silicon between the crystalline layer 16 and the amorphous silicon layer 28 It is formed to reach the boundary 64. The fully crystalline nature of this upper layer is due to the implanted Due to the fact that it is subjected to a large magnetic field from the The growth rate of the returning layer essentially fails.

Implant energy, ion dose, ion dose rate, and heat sink temperature must be balanced for the purpose of increasing self-tempering @3o and ensuring composition. Must be. Silicon sapphire with the best thickness of 2゜±100 people Finally providing a partially tempered interface layer 30 adjacent boundary 60. 1110.12 and otherwise described above. Implant energy 55 KeV, equivalent to that provided in the main embodiment of the invention , supplied ion dose lX10 iono/cti, ion dose rate 1x io ions/ci-second while the heat sink maintains a constant temperature of approximately 23°C. , must be achieved as best as possible (consistent with the example above). thinly , the indistinct tempered boundary layer reduces the heat sink temperature to about -20°C. This is achieved by an essentially untempered boundary layer 30. paraphrase In other words, the temperature of the heat sink, approximately 250°C, is the temperature at which the quality layer 14b is finally formed. This results in extremely rapid self-tempering. Selected second ion implantation The step carries out the provision of a partial self-tempering layer 30.

When beginning to form a composite substrate in accordance with the principal embodiment of the present invention, The temperature is kept low and the second ion implantation is performed using low mass ions such as hydrogen. Let's do it. , the implantation energy and the ion and ion doses are determined by the amorphous layer 14 (first 2), 22 (Fig. 4) into a substantially uniform layer by partial tempering. Adjust to provide localized heating in minutes. With low mass ions, partial There is no substantial collapse when forming the tempering layer on the silicon layer 1 during the formation of the layer. 2 can be left substantially at a depth Rp just below the surface of No. 2. In this way, it is desirable Silicon/sapphire boundary layer 60 (in the first main embodiment) or amorphous layer 2 2 and the remaining damaged boundary layer 20 via the amorphous layer 14 (FIG. 2), 2 A tempering layer can be partially formed on any layer between 2 (FIG. 4).

However, in all cases, the sapphire substrate 10 exceeds the defect concentration threshold limit. Implant energy and ion dose must be limited to avoid

Once the desired ion implantation step has been completed, both the main embodiment of the invention and the optional When fully implemented using the modified example, the two-step heat treatment process described above The amorphous layer can be tempered. The first step as shown in Figure 7 , the initial amorphous silicon layer 14b forms a crystalline/amorphous silicon boundary 64 ( Typical temperature range is 500°C to 600°C) to start agglomerating. Achieve sufficient temperature. The remaining damaged layers 20 and 20 are shown for clarity purposes. A partially tempered boundary layer 30 is shown in FIGS. 7 and 8. Usual sources of flocculation: 22 In order to grow the amorphous layer 14b, which becomes silicon with a normal crystal orientation, desirable. The tempering avoids most of the amorphous layer 14b and spontaneously aggregates. The crystal regeneration of the remaining amorphous silicon layer 36 is performed at a sufficient temperature. placed after the defect-free crystalline silicon layer 34, typically □silicon/sapphire. The process proceeds until it reaches the regenerated crystalline/amorphous silicon boundary 60. Re The resulting crystalline layer 34 follows the crystallographic alignment of the initial epitaxial silicon layer 12. As was the intended result in the choice of Growth of epitaxial deposition of silicon layer on fire substrate is in (100) direction It is. In this way, the subsequent growth of silicon crystal layer 34 also essentially (100) direction. Defects at the silicon/sapphire boundary are bounded by remaining defects. increases from field defects to silicon layer 12, but mainly due to crystallographic alignment (111) has. Afterwards, the defects agglomerate and regenerate boundaries due to increased growth of the original crystal. does not have the same crystallographic arrangement, so the typical arrangement size is Their defects effectively “glow out” because the speed of As a result, regeneration between the crystallized silicon layer 34 and the amorphous silicon layer 36 occurs. The boundary between the original crystalline 7/amorphous The cells grow from the boundary 64 of the quality silicon. Naturally, if the second main implementation of the invention The remaining missing boundary layer 20, provided as an example, or the two main Tempered and defective boundary layer 30 provided as a variation of the embodiment, and/or 3 Therefore, the growth of the crystalline/amorphous silicon boundary stops once it reaches those layers. Stop. Only amorphous silicon clearly recrystallizes. Recrystallization tempering is 3 0 minutes to 3 hours are required. Once a second temperature tempering step is carried out Then, recrystallization is completed. Temperatures above about 910°C can be used; There is no risk of any random agglomeration of any amorphous silicon after this. Furthermore, this After that, the surface of the sapphire substrate 10 is cleaned of the original impurities of the silicon layer 16.38. There is no risk of contamination, so no damage will occur. This high temperature tempering takes more than 1 hour. This was achieved in a short period of time, mainly in the early stages of regeneration of original crystals/amorphous silicon. Any damage caused to the quality silicon boundary layer 64 can be removed. Similarly, left Damaged boundary layer 20 and partially tempered boundary layer 30 defects may occur. If so, the desired concentration is uniformly lowered without being completely eliminated. This is the desired defect concentration. Establish a degree cross section.

In the example described above, an initial tempering step to recrystallize the amorphous layer 14b is desirable. is carried out at 60° C. for 3 hours in a nitrogen atmosphere.

The second tempering step is preferably also carried out at 850°C for 1 hour in a nitrogen atmosphere. cormorant. Of course, the tempering step heats the silicon layer with aluminum impurities. The temperature must be sufficient to allow it to enter. At this point, the composite board is as shown in Figure 8. The original crystalline layer of the sapphire substrate 10 and the initial epitaxial layer 12 is It consists of an essentially intact crystalline silicon layer 38 sandwiched between 16 and 16. compound group A relatively thin impurity layer 66 is present during the process steps for processing the plate. 2Z Otherwise, the surface of the silicon crystal layer 16 will be exposed.

This impurity layer 66 is preferably formed on the surface of the composite substrate using techniques included in conventional processes. Surface impurities were etched with a mixture of H2SO4 and HF at a volume of 50:50. Remove by cleaning and use.

The remaining original crystalline silicon layer 16 is then recovered from the regenerated crystalline silicon layer 38. The remaining part of the composite substrate is removed and the remaining part is placed adjacent to the sapphire substrate 10 as shown in FIG. let In theory, any tempered layer or remaining defect boundary layer is a recrystallized silicon layer. 38 and the sapphire substrate 10 during the initial ion implantation process. Ru. These layers are not shown in Figures 9 and 10 for clarity. do not have. Rather, the remaining crystalline silicon layer 16 brings the system to a temperature of about 910° C. The complex group is maintained in an atmosphere where H2 flows at a rate of 100 liters per minute. Removal in the reactive process of plate 10.38.16. This step The regrowth of the silicon layer 38 can be carried out in a The next step of epitaxially depositing further on the surface of the composite substrate 10.38 It can be implemented without any processing. As shown in FIG. 1, the epitaxial layer 40 is regenerated. Since it is deposited on the long-crystalline silicon layer 38, it is essentially adjacent to the sapphire substrate 10. A uniform silicon layer 42 is then formed. The second epitaxial silicon layer 40 also The all-silicon layer 42 can be deposited to any desired thickness. Of course, Siri Any conventional technique for providing the cone epitaxial layer 40 can be used. Ru. However, the demand for composite substrates 1o and 3s was met with: 502047(8) Silicon layer 4 without shielding and without any unnecessary processing The epitaxial deposition of 0 is preferably completed in a CVD reactor. Composite substrate 10. With the silane mixture above No. 38. The chemical reaction was performed using silane at a flow rate of 100 to 100 The internal composite substrate was maintained at 910°C at The crystalline silicon is grown at a rate of approximately 2.4 μm/min. epitaxial deposition continues until the desired thickness of the silicon layer 42 is achieved, preferably approximately 5,000 times. It is. At this point, the formation of composite substrate 10.42 is substantially complete and composite substrate 1 0.42 further prepares the silicon layer 42 for forming active elements, respectively. No. As shown in FIG. 11, in the standard process step, gate region 4 of silicon layer 42 is Source and drain regions 48.50 (denoted as N-type) divided by 6 (denoted as P-type) ). In the conventional M　ME　FET　ET, aluminum or The metal contacts 52, 54, 56 which are difficult to melt are connected to the desired gate 46, source 48 and the drain 50, respectively. of silicon layer 42 The exposed sapphire substrate 10, which is partially removed by etching, is an active element. , and the other parts formed in the silicon layer 42 respectively. effectively insulating the device from all other devices. Similarly, a boundary layer 44 is shown in FIG. this Layer 44 is the remaining missing boundary layer or layer provided during the ion implantation step described above. or a tempered boundary layer. Boundary @44 consists of a similarly tempered boundary layer and an alternating The remaining missing boundary layer is further Adjacent to the sapphire substrate 10. The reasons stated in the summary are highly desirable as follows: One or both of the boundary layers of the completed composite substrate 10.42 are connected to the gate of the FET device. The first fundamental reason for including at least one boundary layer in the It has a high concentration of defects in the material of the gate region of the part and is known as a charge pump. The operation of the FET active device prevents the phenomenon that the inversion region in the gate material is conductive or The device is periodically switched between conduction and non-conduction. Good high-speed blocking operation Therefore, two conduction conditions must be satisfied. One is the gate of the active element. During initialization, the charge passing through the region must have high mobility. The current in the conductive state is not limited. This is a charge that alternates between generation and recombination. This means that the charge must have a long lifetime. original quality, essential In semiconductor crystalline materials such as silicon, defects can be converted into charges due to their high mobility and As a result, it does not exhibit long life.

Another requirement that determines the conduction state of an active device is that the charge in the gate region is quickly charged. It is about recombining. The lifetime of the charge in the gate region of an active device is As a result, the charge in the gate region is accumulated. this is The operating parameters of active elements change dramatically as a function of frequency and potential. This causes the device to be prevented from switching to a non-conducting state. A gate like this The charge Ha within the region is typically known as charge pumping. .

Prediction in the high defect concentration region is at least active element gate: 27 Effectively prevents charge pumping in the area. Defects in the crystals of semiconductor materials are called char. This effectively reduces both the mobility and the lifetime of dicharges, essentially reducing the scattering and recombination Becomes the heart. The high concentration defect region in the gate region is occupied only by the fragments of all the gate regions. The mobility of the charged charge in the conducting state is effectively non-charging. however Although extremely small, the highly concentrated defect region within the gate is sufficient for charge pumping. The purpose is to eliminate and recombine charges faster than their accumulation. this provides a boundary @44 with a high concentration of defects such that the desired high depth Allows optimized high-speed operation of active elements in the defect region. Included in high concentration defect layer The second fundamental reason is that the assembly of integrated circuits on composite substrates requires heat dissipation. It may increase significantly. The first result of exposing the integrated circuit for heat dissipation is the silicon layer 1 This is the generation of a false charge within 2. The heat dissipation of the generated charge is also effective. Qualitatively, the intended operation of the active elements of an integrated circuit is determined by the intensity of heat dissipation and the charge generated. Disturb depending on the number of charges. Silicon/sapphire dissipates heat from generated charges. There is a tendency to accumulate at the boundary 60. High defect concentration at silicon/sapphire boundary 60 As a result of providing a continuous boundary layer 44 with increases the tolerance or tightness of the heat dissipation of the integrated circuit; Re Defects in the crystal at the center of recombination substantially reduce the heat dissipation of the recombined charges. ratios increase thereby limiting their boundaries to the desired behavior of the active elements. . High Defects: A fundamental third reason for providing a silicon layer (well, a At least within the gate region of the active device is known as back channel re-cage. Prevent events. Originally, two different crystalline materials placed side by side have a potential close to the boundary. Ru. This potential is essentially important for extracting the boundary potential. In addition, Saf The extracted charge within the bulk of the fire substrate 10 causes exposed heat dissipation to occur as well. You may do so. The bulk from which those charges are extracted has an increased charge as it crosses the boundary. Add. Although this charge is small, the active device source and drain regions 48. effectively introducing a thin inversion layer of silicon/sapphire interface 60 between 50 and 50. This anti The current conducted through the inversion is commonly referred to as back channel retraction. then reverse The part generates a charge that is handled at the silicon/sapphire boundary 60, and Some minimal inversion layers remain substantially unchanged. However, the leakage current is substantially This effectively causes a reduction in the mobility of charge charges through the inversion layer. this is Provide a thin, high defect concentration region such as the boundary layer of the silicon/sapphire interface 60 accomplish something. The thickness of the boundary layer 44 must be greater than the thickness of the back channel inversion layer. do not need. Defects in the crystal are essentially centers of scattering, thereby effectively of the back channel re-cage current between the source and drain regions 48.50 of the device. It becomes a net.

Considering at the same time, the appropriate choice of dimensions, location and special defect concentration of the boundary layer 44 Desired for the reasons mentioned above, including ensuring the exact need for minimal joint leakage A highly productive active element having current can be obtained. The first step in manufacturing active devices is the exposure process. Person 1 @59-502047 (9) The silicon layer 42 is a silicon layer 42 with a desired high defect concentration region exposed. The idea is to prepare it so that it is located as far away from the surface as possible. Siri The best in layer 44, placing a high defect concentration boundary layer 44 at the con/sapphire boundary 60. Although the results of It doesn't even make a sound. High defect concentration boundary layer to minimize junction leakage current 44 is made as thin as possible to provide the desired number of recombination centers for the required defect concentration. .

In particular, the defect at the recombination center causes leakage current to flow across the reversal section and bypass the P-N junction. Ass. The active device source 48 and gate 46 regions or drain 50 and The leakage current in the region of the Proportional. In this way, the thickness of the junction area of the boundary layer 44 and the correspondence are as small as possible. The layer 44 preferably has a thickness of about 200 layers. Ru. In this way, a semiconductor composite substrate on an insulating material with a highly controlled concentration cross section can be obtained. The manufacturing process of the board was clarified.

Obviously, many variations and modifications of this invention are possible in light of the best best practice in the circumstances. It is. Their variations include the use of specified semiconductor and insulating materials, specific conductivity types, and Semiconductor layer, specific ion, ion dose, and dose skewer, implant energy and may include variations in process times and temperatures within the limits published herein. . In addition, there are various substances and substances that are important and have not been mentioned so as not to obscure this process. Certain conventional methods include preparing for epitaxial deposition of semiconductor materials on and steps of well-known processes. Added claims for understanding Within the scope, the invention may be practiced otherwise than as specifically described above.

Fig　1゜ Fig, 9, Procedural amendment 1.Display of the incident PCT/US83101622 2. Name of the invention Fully controlled defect concentration cross-section for mixed epitaxial semiconductors on insulating mixed substrates Conductor epitaxy phase and growth method 3, person performing correction Relationship to the incident: Patent applicant Name: Hughes Aircraft Company 4, Agent Address: 1-26-5 Toranomon, Minato-ku, Tokyo 17th Mori Pill 105 Phone: 03 (502) 3181 (Main representative) Ming ao (pages 1 and 5 to 9) and scope of claims These are handwritten Engraving (no changes to the content) Specification Fully controlled defect concentration cross-section for mixed epitaxial semiconductors on insulating mixed substrates Conductor epitaxy phase and growth method technology field 1. Field of invention Non-inventions generally include, for example, silicone-on-sapphire.

(SOS), etc., or other devices with a silicon single crystal epitaxial layer. However, the original substrate has extremely high levels of impurities, such as the aluminum used in sapphire substrates. Manufacturing of semiconductors on insulating mixed substrates with low concentration and highly controlled defects in the cross section of the concentration Regarding.

2. Description of conventional technology It has the advantage of usability. It consists of a single crystal semiconductor layer such as silicon and is placed on an insulating substrate. Epitaxial precipitation of mixed substrates is well known.

Such utilization substantially reduces the stray capacitance f between the active area and the substrate. , which eliminates leakage current flowing between adjacent active devices. You can get the same effect.

The substrate is made of an insulating material such as sapphire (A'zOs), which is a hard high-f color material. It can serve the purpose of being used as A conductive path for leakage current can be provided.

At present, conventionally planned and actually realized on a mixed board.

Ideal silicone material - International investigation report due to several serious problems

Claims (1)

[Claims] 1.a) A semi-finished material of a given thickness and prepared close to the surface of a given insulation material. a) a layer of a conductive material; b) a buried portion of this semiconductor layer is made amorphous; is made of a semiconductor layer that is substantially unaffected by the amorphization of the buried portion of the semiconductor layer. A method for manufacturing a composite substrate, characterized by steps of: 2. Amorphousization of the buried portion of the semiconductor layer by the method of claim 1 The step further includes a given implantation energy given to the semiconductor layer. ion at a given dose and non-implanting the buried portion of the semiconductor layer. Crystallization occurs when the dose and energy of each residual ion causes insufficient damage. and passes through the semiconductor layer and into the insulating material to eliminate a plurality of impurities. As a result of the dispersion, any defects in the insulating material become slight impurities in the semiconductor layer. 3. The step of implanting ions by the method of claim 2 further comprises the thickness of the semiconductor layer given above, the ion dose given above and the implantation etching given above. energy is generated by the embedded amorphous material that exists in close proximity to the surface of the insulating material. It is characterized by going to the part. 4. In the step of implanting ions by the method of claim 2, the ions further: The thickness of the semiconductor layer given above, the ion dose given above and the given above For a given thickness of the insulating material and a given crystal lattice of the above insulating material, within said semiconductor material spaced apart from the surface of the remaining boundary layer having a concentration of defects. It is characterized in that it is applied to the existing buried amorphous portion of the semiconductor layer. 5. The filling of the semiconductor layer by the method of claim 1, 2, 3, or 4. The step of amorphizing the included part is as follows: For a virtual tempered layer of given thickness and given crystal lattice defect concentration Using the boundary between the insulating material and the semiconductor material at a given constant temperature, an amorphous layer of the semiconductor layer disposed proximate to the surface of the semiconductor material proximate to the body material; arranging to form within said semiconductor material adjacent a boundary of said semiconductor material; include. 6. By the method set forth in claim 5 a) crystallizing the buried amorphous portion of the semiconductor layer; b) The recrystallized portion of the semiconductor layer is substantially exposed to X to partially form the semiconductor layer. and C) the layer added to the recrystallized portion of the semiconductor layer is providing a layer in which the recrystallized portion is added in close proximity to the semiconductor material to substantially form the crystalline structure; eliminate child loss, Consists of steps. 7. Scope of Claims No. 1. in a second or third method a) said embedding of said semiconductor layer; crystallization of the amorphous part, b) causing the recrystallized portion of the semiconductor layer to substantially come out and partially exposing the semiconductor layer to C) The layer added to the recrystallized portion of the semiconductor layer is left on the semiconductor layer. providing a layer in which a recrystallized portion is added in close proximity to the semiconductor material, substantially altering the crystal lattice; eliminate defects, Consists of steps. 8. By the method set forth in claim 4 a) crystallizing the buried portion of the semiconductor layer; b) exposing substantially all of the recrystallized portion of the semiconductor layer and partially exposing the recrystallized portion of the semiconductor layer; C) The layer added to the recrystallized portion of the semiconductor layer is left on the semiconductor layer. providing a layer with a recrystallized portion in close proximity to the semiconductor material, substantially forming a crystal lattice; Eliminate the loss of Consists of steps. 9. The above code table 111159-5020 of the above semiconductor layer by the method according to claim 6. 47 (2) having a step of recrystallizing the embedded amorphous portion, &) recrystallization said semiconductor so as to shape the layer to have a substantially uniform crystallographic arrangement. The buried amorphous part of the layer is regenerated and grown. b) It contains many defects in the crystal lattice, and the defect concentration in the crystallized layer is low and a region of the semiconductor layer uniformly related to and apart from the crystallized layer and the insulating material; Temper the semiconductor layer by creating a substantial number of defects in the semiconductor layer. Contains steps. 10. Regenerating the buried amorphous portion of the semiconductor layer by the method according to claim 8. a) crystallizing the recrystallized layer to a uniform crystallographic alignment; The buried amorphous portion of the semiconductor layer is regenerated to form the semiconductor layer. let me b) It contains many defects in the crystal lattice, and the defect concentration in the crystallized layer is low and a region of the semiconductor layer uniformly related to and apart from the crystallized layer and the insulating material; Temper the semiconductor layer by creating a substantial number of defects in the semiconductor layer. Contains steps. 11. In the second, third or fourth method, the insulating material has a defect concentration. Threshold, dose, and averaged residual value of ions passing through the semiconductor layer. 3 Gen energy, and the inside of the insulating material has a threshold concentration of defects in the insulating material. ion implantation step characterized by less than or equal to the number of ions. 12. In the method according to claim 11, the step of implanting ions is performed on the insulating material. is sapphire, and the defect concentration threshold of the insulating material is approximately I x 1015 keV. ion/crn2. 13. The step of implanting ions in the second, third, or fourth method comprises the steps described above. The thickness of the semiconductor layer is characterized as being less than or equal to about 2,500X. 14. In the method according to claim 13, the ion implantation step is performed at the above-mentioned implantation energy. - is characterized by being less than or equal to about 90 keV. 15. In the method of claim 14, in the ion implantation step, the ion dose is approximately It is characterized by being equal to or less than 2×10 15 ions/LM2. 16. In the method of claim 15, the ion implantation step includes the ion implantation step described above. The semiconductor material is characterized by silicon. 17. In the method of claims 2, 3 and 4, the ion implantation step is , the ion is the same element or composition of elements as the above semiconductor material. It is characterized by 18 Ion implantation step e by the method of claim 17 The knob ion is characterized in that the ion and the semiconductor material are silicon. 19 In the method of claim 17, the ions in the implantation step are arsenic. The above semiconductor material is characterized by GaAs5.