JPS5938056Y2 - semiconductor switchgear - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a semiconductor switchgear that can be turned on and off by a control signal applied to a gate.

Transistors, gate turn-off thyristors (hereinafter abbreviated as GTO), and the like are known as semiconductor switching devices for turning on and off a load current according to a control signal.

Each of these switchgears has advantages and disadvantages, but GTO, which has a large overload current capacity, is more suitable for high-power applications.

FIG. 1 shows the structure of a conventional general GTO.

FIG. 1a is a plan view of the GTO, and FIG.

In the figure, 1 is a GTO substrate consisting of p emitter 2, n base 3, p base 4, and n emitter 5, 6 is a cathode electrode that is ohmically connected to n emitter 5, and 7 is the same as the exposed surface of n emitter 5 of GTO substrate 1. A gate electrode is ohmically connected to the p base 4 exposed on the surface 9, and an anode electrode 8 is ohmically connected to the p emitter 2.

Reference numeral 10 denotes an insulating film made of SiO2 or the like for protecting the surface of the element and electrically insulating the cathode electrode 6 and the p base 4.

As shown in FIG. 1a, a GTO generally has a structure in which n-emitters are arranged in a long and narrow strip, and the n-emitters and gate electrodes are intertwined with each other.

The width of each n emitter is approximately 100 μm to 500 μm.

The reason for this structure is that when a turn-off signal is applied to the gate of the GTO in the on state, the path of the current flowing laterally through the p base layer toward the gate electrode is shortened.
This is to reduce the lateral voltage drop that occurs in the p base due to this lateral current.

If the lateral voltage drop is small, the potential at a location away from the gate of the p-base does not become high, so the turn-off point works effectively on the junction 11 between the p-base and the n-emitter, resulting in good turn-off efficiency.

As described above, since the n-emitter has an elongated structure and has a narrow width, when attaching a lead wire to the cathode electrode, it is impossible to attach it to a portion of the cathode electrode above the n-emitter.

Therefore, as shown in FIG. 1a, a wide cathode electrode portion 61 connecting the cathode electrodes on each n emitter is provided to provide a sufficient area for connecting the lead wires.

At this time, the insulating film 10 insulates the p base 4 and the cathode electrode portion 61.

By the way, it is difficult to obtain an oxide film such as SiO2 attached to the surface of a device in a completely uniform form, and pinholes, that is, small holes that may be formed in the insulating film, can be removed by photo-etching, for example. This occurs when undesired portions of the insulating film are etched away in dots when forming holes for electrode formation.

When a cathode electrode is formed on an insulating film having a pinhole in this way, the p base 4 and the cathode electrode 61 are short-circuited through the pinhole 12, as shown in FIG.

The resistance of this short circuit is determined by the diameter and number of pinholes, which cannot be controlled.

This causes large variations in characteristics such as the ignition current of the element, which largely depends on the magnitude of the short-circuit resistance.

Furthermore, if the p base and the cathode electrode are short-circuited, the gate current will change between the p base and the n
Since the pinhole portion is shunted in addition to the emitter junction 11, the sweep of excess carriers from the p base to the gate is weakened, resulting in poor turn-off gain or, in some cases, inability to turn off the device.

For these reasons, it has heretofore been difficult to obtain GTO with desired characteristics at a high yield.

The purpose of the present invention is to provide a GTO with a new structure that solves the problems of the conventional GTO described above.

A feature of the present GTO to achieve this purpose is that an n conductivity type layer is formed under the large area 61 of the cathode electrode to which the lead wire is connected, and the p base and cathode electrode are separated by pinholes formed in the insulating film. In addition to preventing short circuits in G
The point is that the region of TO where the n-conductivity type layer is formed is not turned on.

Hereinafter, the present invention will be explained in detail with reference to the drawings.

FIG. 3 shows a plan view a and a partial sectional view of a GTO according to an embodiment of the present invention, which has a rated voltage of 600 cm and a rated DC current of 5 A.

In the figure, the same parts as in FIG. 1 are indicated by the same symbols as in FIG. 1.

The GTO of this embodiment is different from the conventional GTO shown in FIG.
does not extend over the entire surface of the GTO substrate 1 opposite to the surface 9, and the p emitter is removed on the surface 14 facing the n conductivity type layer 13.

It is desirable that the lateral distance d between the end 15 of the p emitter and one end of the n-type layer 13 is at least equal to or longer than the diffusion length of the injected carriers in the n base.

Specifically, an n-type silicon substrate 1 with a resistivity of about 30βa
A p emitter 2 and a p base 4 are formed by a selective diffusion method known in the art.

Next, an n emitter 5 and an n-type layer 13 are simultaneously formed in the p base 4 by a known selective diffusion method.

Further, an oxide film 10 is formed on the element surface 9 and selectively etched away with known dimensions to form holes for electrode contacts.

Finally, cathode electrode 6, gate electrode 7, anode electrode 8
form.

The n emitter 5 has a width of 240 μm and a length of 1300 μm.
Five block-shaped emitters each having a thickness of 15 μm are arranged side by side,
The thicknesses of the p base 4, n base 3, and p emitter 2 are 30 μm, 120 μm, and 45 μm, respectively.

N-type layer 13 (7) width is 700 μm, p emitter 2 to n
The lateral distance d to the mold layer 13 is 100 μm.

With the structure shown in FIG. 3, the area of the region where the cathode electrode 6 and the p base layer 4 face each other with the oxide film 10 in between becomes extremely small compared to the conventional example shown in FIG. The probability of short-circuiting between 6 and the p-base 4 through a pinhole formed in the oxide film 10 becomes extremely small.

On the other hand, by forming an n conductivity type layer 13, the anode electrode 8, the p emitter 2, the n base 3, the p base 4, the n type layer 13, and the cathode electrode 6 connected to the layer 13 through the pinhole 12 are formed. A pnpn four-layer cyrisk structure is produced.

It is not preferable that this four-layer thyristor structure is turned on together with the original thyristor region (1) consisting of the anode electrode 8, p emitter 2, n base 3, p base 4, n emitter 5, and cathode electrode 6.

(If it is 5'J, in that case, the n-type layer 13 is located far from the gate electrode 7, so even if you try to turn off the gate of the thyristor with the n-type layer 13 as the n-emitter, the This is because the gate current path is long, and therefore the voltage drop in the lateral direction becomes large, and the potential under the p-based n-type layer 13 becomes high, making it impossible to turn off the thyristor.

That is, the GTOl containing the thyristor cannot be turned off and does not function as a GTO.

However, if the p-emitter is not formed on the anode side element surface 14 facing the n-type layer 13 as in this embodiment, there is almost no possibility that the thyristor using the n-type layer 13 as the n-emitter will turn on.

This is because, in this case, the holding current of the thyristor becomes extremely large compared to the holding current of the original thyristor region I where the n-type layer 5 and the p-emitter 2 directly oppose each other.

At this time, it is desirable to make the lateral path distance d between the end 15 of the p emitter 2 and the n-type layer 13 longer than the diffusion length of the carriers injected into the n-base. can be completely prevented.

In this way, in this example, the manufacturing yield of GTO could be increased to 90φ or more.

Comparing this to the conventional 60+, it can be seen that the effect of the present invention is large.

In this embodiment, the end portion 15 of the p emitter and the end portion 16 of the n emitter 5 are vertically overlapped, but it is not necessary to do so in order to obtain the effects of the present invention.

However, if the end 15 of the p emitter 2 is unnecessarily exposed to the outside of the n emitter 5 (to the left in FIGS. 3a and 3b), the end of the n-type layer 13 that is d laterally away from the p emitter 2 moves to the left accordingly, the area of the region where the cathode electrode 6 and the p base 4 face each other with the oxide film 10 interposed therebetween increases, and the probability of pinhole short circuit increases.

Therefore, it is not preferable to unnecessarily expose the end portion 15 of the p emitter 2 to the outside of the n emitter 5.

The advantage of this embodiment is that the n-type diffusion can be done only once because the n-emitter 5 and the n-type layer 13 can be formed at the same time;
This is because there is no p emitter in the vertically opposing portions of the mold layer 13.

This means that the undesirable thyristor effect caused by using the mold layer 13 as an n emitter can be almost completely prevented.

FIG. 4 is a diagram showing another embodiment of the present invention.

The p emitter 2 is not selectively diffused but is formed over the entire surface.

In this example, the n-type layer 13, which prevents a short circuit between the cathode and the p-base due to a pinhole generated in the oxide film, is diffused to be shallower than the n-emitter 5, and the p-base thickness of the region By making it thicker, the electron transport efficiency becomes worse.
This prevents the region (2) in which the n-type layer 13 is an n-emitter from being turned on.

In this example as well, the effect of the present invention obtained was almost the same as in the example shown in FIG.

From the viewpoint of the manufacturing method, the structure of this example has the disadvantage that layer 13 and layer 5 cannot be formed at the same time, requiring two n-type diffusions. However, since selective diffusion is not required to form the p emitter, the dopant used can be This has the advantage of increasing the degree of freedom regarding types.

As described above, according to the present invention, short circuits between the cathode electrode and the p-base can be almost prevented without impairing the function of the GTO.
GTO can be obtained with a higher yield than before.

Although the present invention has been explained above with reference to specific embodiments, the effects of the present invention are not limited to these structures.
The effects of the present invention can be obtained in general GTOs having a structure in which a cathode electrode having a large area is connected to a semiconductor layer other than an n emitter via an insulating film.

Furthermore, the ptn conductivity type of the element may be completely reversed from the above description.

[Brief explanation of drawings]

Fig. 1 is a plan view and a partial sectional view showing the structure of a conventional GTO, Fig. 2 is a diagram explaining the problems of the conventional example, and Fig. 3 is a plan view and a partial sectional view showing an embodiment of the present invention. , FIG. 4 is a partial sectional view showing another embodiment of the present invention. 1...GTO base, 2...-p emitter, 3...n
base, 4...p base, 5...n emitter, 6...
... Cathode electrode, T... Gate electrode, 8... Anode electrode, 10... Insulating film, 12... Pinhole,
13...N conductivity type layer.

Claims (1)

[Scope of utility model registration request] A first layer of one conductivity type, adjacent to the first layer forming a first pn junction with the first layer, and a second layer of one conductivity type, adjacent to the second layer. forming a second pn junction with the second layer, and forming a third pn junction with the third layer adjacent to the third layer; a semiconductor substrate having a fourth layer of the other conductivity type, the second layer and the third layer having higher specific resistance regions than the first layer and the fourth layer; and at least the first layer and the fourth layer. It consists of a pair of main electrodes each in ohmic contact with the surface, a control electrode in ohmic contact with the third layer for controlling the two states of conduction and non-conduction between the main electrodes, and a control electrode in ohmic contact with the fourth layer. In a semiconductor device having a structure in which an electrode is connected to a semiconductor layer other than the first layer and the second layer via an insulating film, a fifth layer of the other conductivity type within the third layer is separated from the fourth layer. A semiconductor switchgear, characterized in that the semiconductor switchgear is formed to be connected to a main electrode in contact with the fourth layer via an insulating film, and includes means for preventing a region including the fifth layer from becoming conductive.