JPS5925990U - chiyotsupa circuit - Google Patents

chiyotsupa circuit

Info

Publication number
JPS5925990U
JPS5925990U JP12127982U JP12127982U JPS5925990U JP S5925990 U JPS5925990 U JP S5925990U JP 12127982 U JP12127982 U JP 12127982U JP 12127982 U JP12127982 U JP 12127982U JP S5925990 U JPS5925990 U JP S5925990U
Authority
JP
Japan
Prior art keywords
switch element
circuit
chiyotsupa
transformer
mo3fet
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP12127982U
Other languages
Japanese (ja)
Inventor
福原 佳彦
塚本 一男
Original Assignee
日本電信電話株式会社
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 日本電信電話株式会社 filed Critical 日本電信電話株式会社
Priority to JP12127982U priority Critical patent/JPS5925990U/en
Publication of JPS5925990U publication Critical patent/JPS5925990U/en
Pending legal-status Critical Current

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Abstract

(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。
(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

【図面の簡単な説明】[Brief explanation of drawings]

第1図は従来のチョッパ回路の構成図、第2図は第1図
の動作を説明するための波形図、第3図は本考案のチョ
ッパ回路の実施例の構成図、第4図は第3図の動作を説
明するための波形図である。 1・・・直流電源、2・・・MOSFET、3−6−チ
ョークコイル、4,7.11・・・ダイオード、5・・
・コンデンサ、6・・・負荷、8・・・変成器、9,1
2・・・トランジスタ、10・・・抵抗。
FIG. 1 is a configuration diagram of a conventional chopper circuit, FIG. 2 is a waveform diagram for explaining the operation of FIG. 1, FIG. 3 is a configuration diagram of an embodiment of the chopper circuit of the present invention, and FIG. 4 is a waveform diagram for explaining the operation of FIG. 3. FIG. 1...DC power supply, 2...MOSFET, 3-6 choke coil, 4,7.11...diode, 5...
・Capacitor, 6...Load, 8...Transformer, 9,1
2...Transistor, 10...Resistor.

Claims (1)

【実用新案登録請求の範囲】 MOSFETのゲート・ソース間に変成器の2次巻線と
ダイオードを直列接続し、該変成器の1次巻線に直列接
続した第1のスイッチ素子を導通させることにより、前
記MO3FETを主スィッチ素子として導通させる構造
の降圧形チョッパ回路において、 前記MO3FETのゲートと環気の間に第2のスイッチ
素子を接続し、前記第1、第2のスイッチ□素子を交互
に導通、遮断させることを特徴とするチョッパ回路。
[Claims for Utility Model Registration] A secondary winding of a transformer and a diode are connected in series between the gate and source of a MOSFET, and a first switch element connected in series with the primary winding of the transformer is made conductive. Accordingly, in a step-down chopper circuit having a structure in which the MO3FET is made conductive as a main switch element, a second switch element is connected between the gate of the MO3FET and the ambient air, and the first and second switch elements are alternately connected. A chopper circuit characterized by conducting and cutting off.
JP12127982U 1982-08-09 1982-08-09 chiyotsupa circuit Pending JPS5925990U (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP12127982U JPS5925990U (en) 1982-08-09 1982-08-09 chiyotsupa circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP12127982U JPS5925990U (en) 1982-08-09 1982-08-09 chiyotsupa circuit

Publications (1)

Publication Number Publication Date
JPS5925990U true JPS5925990U (en) 1984-02-17

Family

ID=30277640

Family Applications (1)

Application Number Title Priority Date Filing Date
JP12127982U Pending JPS5925990U (en) 1982-08-09 1982-08-09 chiyotsupa circuit

Country Status (1)

Country Link
JP (1) JPS5925990U (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6140998A (en) * 1984-07-31 1986-02-27 株式会社 間組 Method of lock anchor construction

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6140998A (en) * 1984-07-31 1986-02-27 株式会社 間組 Method of lock anchor construction
JPH0349358B2 (en) * 1984-07-31 1991-07-29 Hazamagumi Kk

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