JPS59223997A - Storage device - Google Patents

Abstract

PURPOSE:To perform a high speed operation without using any timing signal from the outside and, at the same time, reduce the power consumption of a storage device using insulated gate field effect transistors (MISFETs), by generating timing signals through the change of address input signals. CONSTITUTION:When address input signals inputted into terminals A0-An-1 change, two input signals of an exclusive OR circuit EXOR50 in a change of input signal detecting circuit 5 change with a time difference and a pulse signal of a logic ''1'' appears on the output line 6 of the EXOR50 during the period of this time difference. When an MISFET71 in a control signal generating circuit 7 of a dynamic circuit is turned on and the electric charge of a capacitor 73 is discharged, the voltage across the terminals of the capacitor 73 drops and MISFETs75 and 76 are cut off and, as a result, a control signal phip becomes high level. When the output signal of the EXOR50 becomes low level and the MISFET71 is turned off, the capacitor 73 is gradually charged through an MISFET72 for load and the voltage across the terminals of the capacitor 73 is changed to high level.

Description

[Detailed Description of the Invention] This invention relates to an insulated gate field effect transistor (hereinafter referred to as
The present invention relates to a storage device using MIS FET.

Conventional integrated circuit storage devices using MIS FETs can be roughly divided into static types in which the output is determined only by address signals, and dynamic types in which the output is determined using the address signal and one or more timing signals. Static type integrated circuit storage devices consist only of static logic circuits, and the resistance ratio between the switch elements and load elements that make up the logic circuits must be approximately 1:10, so the output capacitance of each logic circuit must be charged. It takes a long time, which reduces the speed of reading and writing memory contents.Also, whenever a switch element conducts, there is a current path from the power supply through the load element and through the switch element, which increases power consumption. There were disadvantages. Dynamic type integrated circuit storage devices are similar to static type integrated circuit storage devices in terms of logic circuits, but
As shown in FIG. 1 as a configuration example and as shown in FIG. 2 as a time chart, it is characterized by including a dynamic logic circuit that operates in response to a timing signal ψ synchronized with an address input signal.

In Fig. 1, 1 is a decoder device using a dynamic logic circuit, which performs precharging and subsequent sampling operations based on the timing signal ψ, thereby shortening the charging time of the load capacitance and reducing the DC current path. By reading the stored contents from the memory element matrix, a memory device with high write speed and low power consumption can be obtained.

3 is an input/output circuit. The disadvantages of the integrated circuit storage device of FIG. 1 are firstly that it requires an external timing signal synchronized with the address input signal, and secondly that it requires an extra input terminal for the integrated circuit. be.

The object of the present invention is to generate a timing signal based on changes in an address input signal, to enable high-speed operation without using an external timing signal, and to reduce power consumption.
The purpose of this invention is to provide a storage device using FET.

An embodiment of the present invention will be described below with reference to FIGS. 3 and 4. The third panel is a diagram showing an embodiment in which the present invention is applied to a read-only storage device using MISFET.
is an address decoder circuit, 2 is a storage element matrix,
2o and 21 are memory elements that store logic IQI and -1°, respectively; 22 are output lines B1 to B1 of the memory element matrix;
MIS FBT that precharges Bm, 3 is the readout circuit, 3o and 31 are the output B of the memory element matrix
MIS PET for holding the previous read data while 1 to Bm are precharged; 32 is a buffer amplifier; 4 is an address input driver; 5-digit address input signal change detection circuit; 6 is an address input signal The output line 7 outputs the pulse signal generated by the change in the pulse signal, and the control signal ψp of the dynamic circuit is output by the pulse signal.
This is a circuit that generates

Next, the operation shown in FIG. 3 will be explained using the time chart shown in FIG. The following description will be made regarding an N-channel MISFET. First, when the address input signal input to the terminal Ao''-An-1 changes, the two input signals of the exclusive OR circuit (hereinafter referred to as EXOR) 50 in the address input signal change detection circuit 5, i.e. The address input signal input directly and the address input signal input via the inverters 11 and 51 change with a time difference, and during this time difference, a logic 11m pulse signal appears on the output line 6 of the EXOrt 50.This pulse signal causes the dynamic When the MIS FET 71 in the control signal generation circuit 7 of the circuit turns on and the charge of the capacitor 73 is discharged, the capacitor 7
The voltage across the terminals of MIS FET 75 drops as a result.
and 76 are cut off, and the control signal ψp becomes high level. The output signal of EXOR50 goes to low level, MI
When S FET71 turns off, the load MIS FET
Through capacitor 72, capacitor 73 is gradually charged and the voltage across its terminals shifts to a high level.

During this charging period, since the MIS PET 10 is driven by the signal ψp, all of the word lines Wo-WN-1 become low level. Furthermore, the bit lines B1 to Bm are all precharged to a high level by driving the MIS FET 22 for precharging with the signal ψp, while the output terminals 0UT1 to OUTm are connected to the MIS by the signal φpD.
By turning off the FET 30, the bit lines 81~
The data that was being output just before being disconnected from Bm is transferred to MIS.
It is held as it is by the latch circuit 3 consisting of FETs 30 and 31 and inverters 33 and 34.

The potential of the capacitor 73 is connected to the Schmitt trigger circuit 74.
When reaching the on level, the Schmitt trigger circuit 74 is turned on, the signal ψp becomes low level, and the bit lines 81 to
Bm precharging is completed. At this time, only the decode signal output #12 in the address decoder circuit 1 corresponding to the word line selected by the address input signal has reached a high level, and those corresponding to other word lines have reached a low level. Therefore, when the signal ψp goes low and the signal φp goes high, the address decoder circuit connected to the selected word line has M
Since ISFET II is turned on and MISFET 10 is turned off, only the selected word line becomes high level, and the other word lines remain low level. Therefore, when the signal ψp becomes low level and the precharging of bit lines B1 to Bm is completed, and the selected word line becomes high level, data sampling is performed, and depending on the storage contents of the storage elements, bit lines 81 to Bm level is determined. The signal φpD is output by the delay element 81 at a certain time interval after the signal ψp goes low level and the signal ψp goes high level, that is, the bit line B
After the level state of 1 to Bm is determined, it becomes high level, turns on MISFET 30, and turns on the bit lines Bl to Bm.
Output the memory data output to m to the output terminal OUT 1- OUT
Take it out to m.

The advantages of integrated circuit storage devices that operate as described above are explained below.
! i' To be clear, the decoder circuit, which detects changes in the address input signal and is driven by an internally generated timing signal, and the memory element matrix circuit, are operated by an old-fashioned method that requires a short charging time for the load capacitance. , MIS with few distribution channels
Since it is configured with a dynamic type circuit using FETs, it goes without saying that it is possible to create a storage device that can operate at high speed and consumes little power, and the present invention eliminates the need to generate external timing signals other than address signals. Therefore, the number of terminals of the integrated circuit storage device can be reduced.

Furthermore, ii'! The control signal generation circuit 7 of the embodiment operates as a retriggerable monostable multivibrator, and even if multiple address input signals change with a time lag, precharging is performed from the address input signal that changed last. It also generates control signals ψp and the like necessary for sampling, thereby ensuring normal operation as a storage device.

In addition, in the case where there is no latch circuit, a logic IQ @ level signal is applied to the output terminal when precharging the bit line, so the readout circuit must be configured not to read out the output signal during that period. Although the readout circuit itself becomes complicated, such a drawback can be eliminated by adding a latch circuit.

Another embodiment of the invention is shown in FIG. FIG. 5 shows a case where the application is applied to a readable/writable storage device, in which dynamic circuits are used for the address decoder circuit 1, input/output circuit 2, etc. Similarly to the second embodiment, an address input signal change detection circuit is used. 5 and a circuit 7 for generating a control signal ψp, etc., it is possible to improve read and write speeds, reduce power consumption, and reduce the number of terminals.

[Brief explanation of the drawing]

FIG. 1 is a block diagram of a conventional storage device using an external timing signal, FIG. 2 is a time chart showing the operation of the circuit of FIG. 1, and FIG. 3 is a readout according to an embodiment of the present invention. FIG. 4 is a time chart showing the operation of the circuit of FIG. 3, and FIG. 5 is a block diagram of a read/write storage device according to another embodiment of the present invention. DESCRIPTION OF SYMBOLS 1... Address decoder circuit, 2... Storage element matrix, 3... Input/output circuit, 4... Address/input driver, 5... Address input signal change detection circuit,
6.12... Output line, 7... Control signal generation circuit, 3
3,34°41,51...Inverter, 32...Buffer amplifier, 1o. 11, 22.30.31, 7], 72.75.
76...MI 5FET, 73...Capacitor,
74...Schmitt trigger circuit, 81...delay element. 11]・Representative Patent Attorney Susumu Ueban -- 6゛ra 1. Engraving of the drawings (no changes to the contents) '; ) 6 7゜59.7゜1983 Commissioner of the Japan Patent Office 1, Indication of the case 1982! 1'1mi Permit No. 41773 2, Title of the invention Storage device 3, Relationship to the amended case Applicant: 5-33-1 Shiba, Minato-ku, Tokyo (423) NEC Corporation Representative: Sekimoto Tadahiro 4, Agent Address: 1137-8 Shiba-go, Minato-ku, Tokyo 108) Sumitomo Sanda Building Subject of amendment: 4 sets of 1, lfl dust Contents of amendment: Engraving of the specification and drawings (no change in content)
Nowa 2-

Claims (1)

[Claims] An address input signal is input to one input terminal, and one first pulse is output each time the input signal changes, mainly using an exclusive OR circuit which inputs the input signal after delaying it to the other input terminal. an address input signal change detection circuit to output, and a second pulse having a constant pulse width driven by the first pulse.
a pulse generating circuit that outputs a pulse and a third pulse having a phase opposite to the second pulse; a decoder circuit that inputs the address input signal; and a gate that receives the output of the decoder circuit and receives the third pulse at one end a first transistor whose other end drives the word line; and a second transistor which is connected between the word line and the reference potential 1 and whose gate receives the second pulse. storage device.