JPS59207731A - Analog digital conversion - Google Patents

Abstract

PURPOSE:To perform A/D conversion at high speed without causing malfunction by increasing clock pulse frequency of a successive comparison type A/D converter continuously from high order side bit to low order side bit. CONSTITUTION:An analog signal from a terminal 7 is added with output from a DA converter 5 by an adder 1 and the result of addition is impressed to a comparator 2 that judges positive or negative of the polarity, and inputted to a successive comparison register 3 that set the content basing on the result of comparison. The DA converter 5 outputs binary weighted analog value to the adder 1 basing on digital output 4 of the register 3. Clock pulse CP from a clock oscillator 6 is processed by a controlling circuit 8, and frequency is changed to lower frequency for comparison of high order bit side and to higher frequency for comparison of low order bit side. The CP is impressed to the register 3 and comparison time is set longer in high order side bit.

Description

DETAILED DESCRIPTION OF THE INVENTION Field of the Invention The present invention relates to an analog-to-digital conversion method, particularly to a successive approximation analog-to-digital conversion method.

Conventional configuration and its problems As is well known, the successive approximation type analog-to-digital (AD) converter uses a digital-to-analog (DA) converter as a feedback circuit, and the analog value output from the ODA converter. The contents of the register are set from the upper digits of 2 bases so that the value and the analog input value to be AD-converted match, and the binary code is obtained.

FIG. 1 is a diagram showing an example of the configuration of such a successive approximation type AD converter, and includes an adder 1, a comparator 2 to which the addition result of the adder is added and determining whether the polarity is positive or negative, and a comparison result. a successive approximation register 3 whose contents are set based on the register, a DA converter 6 which outputs an analog value weighted in binary based on the digital output 4 of the register to an adder, and a clock generator 6. It is made up of. Note that 7 is a terminal to which an analog input to be converted is added.

In the successive approximation type AD converter configured as above,
Binary weighted analog values are sequentially output from the DA converter 6, and the contents of the register 3 are sequentially set from the most significant bit (MSB) to the least significant bit (LSB). 0 FIG. 2 is a timing chart for explaining the operation of digitally converting the analog value 142, for example.
The figure a shows the clock pulse, the figure b3 b: Rike analog human power At and the analog output Ao of the DA converter 5.
, C of the same figure are diagrams showing the digital output (register contents) 4, respectively.

This timing chart is an example of AD conversion (8 pins). First, the analog value Ao (2'
= 128 ) and xB = 142) are compared, and At )
Based on the comparison result of Ao, "1#" is set in the most significant digit of the successive approximation register 3. Then, the 2nd bit Ao = (2' + 2' = 192) is output from the DA converter 5, This Ao and Ai are compared, and the comparison result of At (Ao is obtained, and the next digit of successive approximation register 3 is “
0'' is set.The DA converter 6 sets Ai (Ao
Based on the comparison result of Ao (2'+2' -2
5=160). Based on the comparison results below,
Ao is output, and successive approximation register 3 contains At (-14
2) Digital data (1ooo1110) is set.

In a successive approximation type AD converter, AD conversion is performed by the well-known comparison operation as described above, but as shown in the figure, the repetition period of the clock pulse that governs the comparison operation is always constant. Incidentally, as various devices equipped with such AD converters become more sophisticated, there is a strong desire for faster AD converters. In principle, increasing the speed of the AD converter can be achieved by increasing the clock pulse frequency. However, when the clock pulse frequency is increased, when the analog input to be converted is around 1/2 of the full scale, there is a risk that an error may occur due to a delay in the rise time of the output of the DA converter. For example, as shown in FIG. 3a, when comparing the first bit, the A converter output AO shown by the solid line should normally be output to the comparator, but the output Ao' shown by the broken line is output. Then, At (the comparison result that should be Ao) is Ao', and the successive approximation register shown in FIG. 3 is set.

That is, the successive approximation register that should be set to (01111110) is set to (1ooooOoo), causing a problem in which correct AD conversion is not performed.

5. Purpose of the Boehmig Invention The present invention provides an AD converter that can perform AD conversion operations at high speed without causing malfunctions in AD conversion operations.
The purpose is to provide a conversion method.

Structure of the Invention The feature of the AD conversion method of the present invention is that the clock pulse frequency for setting the comparison time of the successive approximation type AD converter is increased continuously or stepwise from the upper bit to the lower bit. , the comparison time is set longer in the upper bits.

According to this method, when comparing the upper bits where the rising time of the output of the DA converter is a problem, the time is set to ensure that the output of the DA converter rises, while the lower bit side (The comparison time is set to the minimum necessary limit or close to this limit as one moves toward the minimum limit.) Overall, the time required for AD conversion can be shortened.

In addition, since the comparison time for the side bits is set to a sufficient length, the problem of malfunctions is also eliminated, resulting in 6 pages.

DESCRIPTION OF EMBODIMENTS The AD conversion method of the present invention will be described in detail below with reference to the drawings.

FIG. 4 is a block diagram showing the configuration of a successive approximation type AD converter that enables the AD conversion method of the present invention. As shown in the figure, the clock pulses governing the operation of the AD converter are The clock pulse CP is processed by the control circuit 8, and the clock pulse CP changes so that the frequency is low for comparison on the upper bit side and high for comparison on the lower pit side. The structure is designed to supply the following. Other than this point, the overall configuration and AD conversion operation of the AD converter are the same as those of the conventional AD converter.

By the way, it is preferable that the control circuit 8 described above is configured with a programmable read-on memory (FROM) so that the frequency setting can be freely programmed.

Figure 6 shows page 7 with the lock pulse as shown above:
This is a timing chart for explaining the operation of the AD converter that controls the AD conversion operation. C is a diagram showing digital output.

In the AD conversion method of the present invention, as shown in FIG. 6a, the repetition time of the clock pulse becomes shorter from T to T8, that is, from the upper bit side to the lower bit side. . Therefore, the fifth DA converter
Where the analog output Ao is relatively large, a sufficiently long comparison time is set, and the output A of the DA converter is adjusted within this time.

is established reliably, and error-free comparison results can be obtained. Then, successive approximation register 4 is set in sequence,
For example, if the analog input At is 142, the corresponding digital output (10oo11
o) is obtained.

Incidentally, the time required for the above AD conversion is shorter than in the conventional method in which the pulse interval is constant.

Effects of the Invention According to the AD conversion method of the present invention, since the comparison time is set in accordance with the response speed of the AD converter, error-free A
Not only can the D conversion operation be performed, but the time required for AD conversion can be shortened, and a high-speed, high-performance AD converter can be realized.

[Brief explanation of the drawing]

FIG. 4 is a block diagram showing the configuration of a successive approximation AD converter that enables the AD conversion method of the present invention, and FIG.
2 is a timing chart for explaining the AD conversion method of the present invention. 1...Adder, 2...Comparator, 3...
...Successive approximation register, 4...Digital output, 5...DA converter, 6...
Clock generator, 7...analog input application terminal, 8...control circuit. Name of agent: Patent attorney Toshio Nakao and 1 other person 2nd
Figure (a) Figure 3 (2L) (b)

Claims (1)

[Claims] The feature is that the clock pulse frequency for setting the comparison time of a successive approximation type analog-to-digital converter is increased continuously or stepwise from the upper bit to the lower bit, and the comparison time is set longer in the upper bit. An analog-to-digital conversion method.