JPS59194584A - Video signal recording device - Google Patents

Abstract

PURPOSE:To compensate a fluctuation, and to obtain a picture having a high quality by constituting so that a time base converting means outputs a video signal to be converted, by a frequency corresponding to a relative speed, in a device for executing a record at a speed different from a generating speed of an input video signal. CONSTITUTION:When a start pulse SP is inputted, an input signal Sin is stored in an analog register 10 by a sample pulse phi1, read out by a read-out shift pulse phi2, and inputted to a filter 11. Its output Fout is read in an analog register 12 by a sample pulse phi3 of a period gamma3, in the effective period, and shifted successively. Read-out from the register 12 is executed by synchronizing with a synchronizing signal SY2 of an output side by a read-out shift pulse phi4 of a period gamma4. Accordingly, as for a frequency characteristic of the filter 11, a scale of a frequency axis is converted in an output Sout, the output Fout is extended to gamma4/gamma3, and an equal signal to that which has been sample-held in the period gamma4 is obtained.

Description

[Detailed Description of the Invention] (Technical Field) The present invention relates to a video signal recording device that records an image according to an input video signal, and particularly relates to a video signal recording device that records at a speed different from the generation speed of the input video signal. .

(Description of Prior Art) For example, when obtaining a grid image from an NTSC standard television, the television signal generates an image signal for one frame in 1/60 seconds, but the printer usually generates an image signal of 1/60 seconds.
Recording cannot be completed in 60 seconds.

Therefore, it is conceivable to provide a printer with a memory for storing an image for one frame, but an image memory for one frame has a large storage capacity and is very expensive.

Therefore, the time axis conversion between the input television signal and the print signal is performed without using the image memory for one frame. Time axis conversion can be performed, for example, by using an analog shift register with a capacity for one line and making the periods of the input clock and output clock of the analog shift register different.

However, according to this method, the number of sandal pixels of the input television signal and the number of pixels of the output signal end up being the same. Therefore, the output image size becomes constant.

Furthermore, if the output clock is obtained from a reference oscillator such as a crystal oscillator, it cannot follow the relative speed between the print head of the printer and the print medium, and the quality of the image obtained will deteriorate due to fluctuations in the relative speed.

(Object of the Invention) In view of the above-mentioned drawbacks of the prior art, the present invention aims to provide a video signal recording device that can obtain high-quality images even when there are fluctuations in the relative speed between the recording head and the recording medium. There is.

(Description of Embodiment) FIG. 1 is a time axis conversion circuit diagram of a first embodiment of the present invention. -1 In figure 1, Sin is the input analog signal, 10
is the first analog shift register, Fin is the output of the first analog shift register and is the input signal of the filter 11,
11 is a low-pass filter, Font is the output signal of the filter 11, and 12 is a second analog shift register N 5
out is an output signal, 13 is a clock pulse generation circuit to be applied to the first and second analog shift registers, and φ1 is an input analog signal S to the first analog shift register 10.
φ2 is the clock pulse used to read the signal from the first analog shift register 10 and apply it to the filter 11; φ is the clock pulse used to read the filter output into the second analog shift register 12. , φ4 is a clock pulse for reading out the signal 5out from the second analog shift register 12, SY1 is a synchronization signal on the signal input side, and SY2 is a synchronization signal on the signal output side. SP is a start pulse.

Figure 2 is one of the timing charts for each of the above signals.
For example, the frequency of each clock pulse, the number of clock pulses, etc. can be selected as appropriate.

Next, the operation will be explained. Input signal 5initSYIK synchronous L7'c start pulse SP is pulse generator 1
3, the sample shift pulse φ with period τ
, is applied to the first analog shift register 10 and Si
n is sequentially sampled at φ1 and stored in the analog shift register 10.

This sampled signal is A & (k=1,...
, N1). N does not necessarily have to be equal to the number of stages of the first analog shift register 10, but if N is less than the number of stages, an extra shift clock must be applied to the analog shift register N. Here, the number of stages of the first analog shift register 10 and N are set equal. Then, when the pulse of φ1 is output Nt times, the signal Ak (k=1 to N,) sampled and sequentially filtered by the first analog shift register is set in the first analog shift register. At this time, since A1 is stored in the final stage (N1th stage), when the second read shift pulse φ is applied to the first analog shift register 10, AI, . . . It is read out sequentially at a period τ2. This inertial signal is shown as Fin in FIG.
is low-passed at fc, and the output Fout of filter 1 becomes a signal with cutoff frequency fc. τ2 is” (25c
), that is, fc is 1 of the frequency of φ2.
If it is smaller, Fout can ignore Kempling's contribution. When this condition is Yj + σ, Fout becomes a signal with a waveform equivalent to a signal obtained by exchanging Sin by time !1ijl ! and reducing it by τ6 times, and low-passing it at the cutoff frequency tdfc.By the way, Fin is N with a period of τ2.

Since the readout is performed by the second shift pulse φ2 having a pulse of , Fin is valid only during the time width τ2·N2. According to Takumi, the period during which Fout is valid is the time 1i of τ2・N2.
'M. During this time period, pulse E/ with period τ,
N, is sampled by the third sample shift pulse φ, and read into the second analog shift register 2 and sequentially shifted. Here again, the number of stages of the second analog shift register 120 is assumed to be N3 stages.

Then, the time width required to read into the second analog shift register 12 is τ3·N3, τ2·N, >τ
3.N, only a part of the valid part of the Fout signal is read into the second analog shift register. On the contrary, τ
,・Nl <τ3・N3, up to the invalid part of the Fout signal is read into the second analog shift register, but the invalid part is ignored or the analog signal is inputted at an appropriate level while Font is invalid. All you have to do is switch the input of the shift register. Reading from the second analog shift register 12 is performed using the fourth read shift no.
4, it is read at a cycle of τ4 in synchronization with JSY2. φ4
The number of pulses N4 may be less than or equal to the number of stages of the second analog shift register, and when τ2・Nt <τ,・N, N4
If =τ, ·N, /τ3, the output 5out can be obtained by converting only the effective part of the font to the time axis.

Now, 5out means that Fout is sampled with a period τ and reproduced with a period τ4, so Fout is ry, r.

The result is a signal equivalent to that obtained by stretching the sample and holding the signal at a period of τ4. Therefore, the frequency characteristic of the filter 11 is scale-converted on the frequency axis at 5out, and the apparent cutoff frequency becomes (τ) times (τ) fc. In the end, 5 out is Sin
The signal waveform of is stretched by (-122-) τ3° τ, and the cutoff frequency of the low-pass filter is multiplied by (7), making it equivalent to the waveform sampled and held at τ4.

FIG. 3(a) is a circuit diagram of another embodiment, and those having the same functions as those in FIG. 1 are indicated by adding "l". 20 is a first analog shift register, 21 is an operational amplifier, 25 is a weighted average circuit, 22 is a low-pass filter,
23 is the second analog shift register, 31, 32.3
3 is the last three stages of the first analog shift register, Ro
-R- is resistance. -1 By using the weighted average circuit 25 in this way, R1,
By making the resistance values of L and Rs different, arbitrary filter characteristics such as edge noise removal can be provided. The weighted average is not limited to the last three stages of the analog shift register, but may be used in any number of stages.

Further, another embodiment of the weighted average circuit 25 is shown in FIG. 3(b). In the figure, 34 is an amplifier that performs inverting amplification, and 35 is an amplifier that performs non-inverting amplification. By providing inverting and non-inverting amplification functions in this way, it is possible to design filter characteristics with a large degree of freedom, and it is also possible to provide both edge enhancement and noise removal characteristics.

FIG. 4 shows an embodiment in which the circuits shown in FIGS. 1 and 3 (a) and (b) are applied to a serial video printer that prints out video signals.

In FIG. 4, reference numeral 41 denotes a magnetic disk on which video signals for one field are recorded in one revolution, 41 a playback head for playing back the video signal on the magnetic disk 40, 42 a playback amplifier, and 43 a playback video signal. 44 is a frequency multiplier circuit that multiplies the horizontal synchronous signal l-15, 45 is a waveform shaping circuit, 46 is a shift pulse generation fB, and 47 is a high-frequency reference clock S. ) 12; 50 is a defocus signal separation circuit for extracting a video signal from a reproduced video signal; 51 is a first analog shift register;
2 is a low-pass filter, 531r is a second analog shift register, 54 is an amplifier, and 55 is a printer drive circuit which outputs a print start signal 127 PS and a print ready signal PRY indicating that printing by the printer is possible. 56 is a ji4<IJ:JJ motor that drives the print head in the main scanning direction; 57 is a frequency j1j circuit that multiplies the pulse signal according to the degree of rotation of the drive motor 56; 58 is a waveform 11 circuit; 59 For example, the output voltage of the amplifier 54 (1st hand, etc.): EK Akira,
7. The operation will be explained below.

(The disk 40 is rotated by a motor (not shown) in the direction of the arrow, for example, at 60 revolutions per second, and the video signal of the same field is reproduced by the reproduction head 41.

The reproduced video signal is a composite video signal containing a synchronization signal and a video signal, and is inputted to a synchronization separation circuit 43 and a video signal separation circuit 50 via an amplifier 42. Then, a vertical synchronizing signal Vs and a horizontal synchronizing signal Hs are obtained by the synchronizing separation circuit 43, and both are inputted to the shift pulse generator 46.

Further, the horizontal synchronizing signal H5 is converted into a pulse signal multiplied by the number of samples of the first register 51 in a frequency multiplier circuit 44, and further waveform-shaped in a shaping circuit 45 to produce a shift pulse S.
It is input to the shift pulse generator as HI. Here, the frequency multiplier circuit 44 is connected to PLL (Phase Lock).
By using the ED Loop circuit, a more accurate shift pulse can be obtained. Since the shift pulse SH1 is a product obtained by multiplying the horizontal synchronization signal H8, it contains a constant number of pulses within the horizontal synchronization period, regardless of the jitter of the reproduced video signal. The output reference clock SH2 of the clock generator 47 is input to the shift pulse generator 46. The output of the printer drive circuit 55 is DRIVE! The pulses that drive the auxiliary motor 56 and indicate the rotational speed of the drive motor 56 are sent to a frequency multiplier 57 to record 6i during the lifetime scanning of the recording head.
1 is multiplied to obtain the number of 9 pulses corresponding to the number of threads, that is, the number of output stages of the second register. It is desirable to use a PLL circuit as the multiplier circuit 57. The multiplied pulse is waveform-shaped and then input to the shift pulse generator 46 as a shift pulse S if 4. S114
Even if there is fluctuation in the moving speed of the recording head, the frequency changes according to the fluctuation. The shift pulse generator 46 includes shift pulses 5) 11, 5)) 4 and a clock SH2.
Vertical synchronization 1 day f Gin V'S, horizontal synchronization (G No. H5,
Shift pulses φl", φ2", φ3", φ4 are generated based on the print start signal PS and the print ready signal PRY, respectively.
'' and also controls the printer drive circuit 55. Details of the shift pulse generator 46 will be described later.

10,000, the video signal is passed through the Lujistar 51, the filter 52, and the second
After receiving the time axis conversion described above in the register 53, the amplifier 5
4 to the head driver 59. The head driver 59 operates to record a density on the recording paper that corresponds to the level of the video signal.

Next, the configuration and operation of the shift pulse generator 46 will be explained.

FIG. 5 is a detailed circuit diagram of the shift pulse generator 46, and FIG. 6 is a timing chart of each part in FIG. In the figure, T1 to T7 are input terminals, T8 to T12 are output terminals, 61 is an H counter that counts how many horizontal scanning lines the reproducing head 41 is currently reproducing, and 62 is how many horizontal scanning lines the recording head is currently reproducing. A line counter that counts whether recording of a scanning line is completed; 63 is a comparator; 6
4,65,66,67 are shift pulses φl"~φ4, respectively.
When N+, Nt s Ns and N4 counters each count up 2 pulses, a high level output is latched, and the count and latching are canceled by a reset input.

68.69.70 is a mono multivibrator, 71.7
2 is a set-reset flip-flop (hereinafter referred to as JI'/F
), 73.74.76.77.78.79.8o is AND gate, 81-85 is invar, evening, 88.89V
This is a frequency divider that divides the frequency of lock SH2.
(When the is different and the reset input is at the low level, the minute J- is performed, and the minute 1 = is set at the rising edge of the reset input.)
I'l start with it.

Assuming that the (n 1) i-th horizontal run n r13A is now recorded, the count number of the lie/counter 62 is multiplied by n. And the playback head is the nth horizontally open IC.
'When you read out J Gogo, the count number of ■1 cow/ri is also 1.
1, the p1 comparator 63 outputs a high-level signal S M P L for one horizontal run interval. At this time, the Q1 output of F/Ii'71, which is a high level signal tL'J in which the 5th register 5] is open, is also at high level, so the Punto gate 73 is opened as the open shift pulse S H1+u
A pulse φ1 is applied to the first run starter 51, n n
Sampling is performed for t, N pieces of the t-th horizontal scanning report.

Pulse φ1 Prevents generation of “pulse φ1”. At the same time, the F/F 71 is reset and the AND gate 73 is closed.

That is, when information is stored in the second register 53, information on the next scanning line is prevented from being input to the register 51. Note that N, the counter is reset at the next rising edge of the signal SMPL, is 1, and it is desirable to set it equal to the number of stages of the register 51. Also, N, the output 5E of the counter 64
TI is input to AND gate 74. and gate 7
When no information is stored in the second register 53, a high-level signal Q2 is input to 4. At this time, the signal Q2 is at a high level, so the AND gate 74 is open, and the frequency divider 88 .89 started branching at the same timing,
The shift pulse φ2'', φ3〃+l<x is output to the register 51 and the second register 53, and the information of the second register 51 is
Transfer to register 53. In this way the frequency divider 88.89
starts operating at the same time, and the base r-Itsuk S H
Since the circumference of 2 is sufficiently high compared to φ2′′ and φ3〃,
The phase difference between the first pulses of the pulses φ2'' and φ3' is always -M1,N.Therefore, the phase of the end of the video signal is +iN, which makes it possible to obtain a good image of 111 degrees. The N, , h counter 65 receives a shift pulse φ2 "gold N2
When only Ns are counted, the output becomes a high level, and the AND gate 78 closes to prevent the generation of subsequent shift pulses φ2''. Then, the output is 5ET
2 is at a high level, AND gate 79 is closed to prevent generation of shift pulse φ3p'. F/F 7 at the same time
2 is reset, AND gate 74 is closed, and frequency divider 88 is closed.
．． 89 stops the operation.

That is, while information is stored in the second register 53, the AND gate 74 is kept closed.
The way the 2 comes out is F/F 71. That is, the generation of the shift pulse φ1 is permitted upon completion of the output of the information 7Jl' from the register 51. 11:0,N, ,N,
The counter 65.6G is reset by the rising edge of the Q2 output of the F/F 72.

Further, it is desirable that N3 be equal to the number of stages of the second register 53. A signal 5ET2 indicating the end of counting N8 by the counter 66 is input to the AND gate 76, and an inverted signal 5ET3 of the output of the N4 counter 67 ET3 is also input to the AND gate 76. 5ET3 is at a high level after the N4 counter 67 counts up until the printer ready signal PRY is output, which indicates that the printer is ready to print.
ET3 is a signal indicating a print prohibition period, and therefore, this inverted signal 5ET3 indicates a printable period and a print period. When the storage is completed, the gate is opened and the shift clock SH4 is outputted as a shift pulse φ4'' to the second register 53. When N4 shift pulses φ4 are generated, the output 5ET3 of the rain counter 67 becomes the NO level. At the same time as closing the F/F 76, the F/F 72 is set.In other words, the AND gate 7 indicates that the second register 53 will perform the F/F 72 after the reading of information from the second register 53 is completed.
4, and the generation of shift pulses φ2'' and φ3'' is permitted. That is, after the information in the second register is read,
To enable sampling by the second register even if the signal PRY is not at a high level. In other words, it is possible to speed up time axis conversion. Note that the N4 counter 67 is reset at the rising edge of the printer ready signal.

As described above, samples are input to the first register 51 according to the jitter components of the input video signal, and samples are output from the second register according to the scanning speed of the recording head. In other words, an image with time axis compensated quality can be obtained regardless of changes in the scanning speed of the recording head. Moreover, after the reading of information from the first register 51 is completed, the second register 51
Manual ramping of the video signal is possible even if information is stored in the second register, and once reading of information from the second register is completed, even if the printer is not capable of printing,
Since sampling using registers is possible, it is possible to speed up time axis conversion. Although the sampling frequency of video signals is high, there may be a time interval between sampling one horizontal scanning line and the next, and the recording speed of printers is generally slow. Therefore, the time axis conversion of this embodiment is effective in reducing the overall printing time.

In this embodiment, time axis conversion is performed by reproducing the video signal recorded on the recording medium, but if the video signal of the same screen can be obtained repeatedly, the received video signal,
Alternatively, it can of course be applied to time axis conversion of a video signal read by an imaging means. At this time, when a solid-state image sensor is used as the imaging means, the shift clock of the imaging cable is changed to the shift pulses φ1, φ1', φ without using the horizontal synchronization signal.
1" may be used.

Further, in this embodiment, the time axis conversion output is used for printing, but it can also be used for transmission, etc.

FIG. 7 is a system block diagram of a video printer that obtains a color print from a color video signal. In the diagram, parts having the same functions as those in FIG. 4 are given the same reference numerals. In the figure, 50' is a color signal processing circuit that separates the video signal into R, G, and B color signals; 51a, 5lb
, 51c is a first analog shift register corresponding to each color ID number, 52r+.

52b and 52c are fills corresponding to each color and number 1, r
i3a) 53h and 53c are second analog shift lens stars, 54' is a color signal processing circuit that obtains valley print color signals of yellow Y, magenta M1 cyan C1 black BK from each color signal of R, G%B, 59' is YlM, This is a head driver that drives each C and BK inkjet head.

The R, G, and B color signals obtained by the color signal processing circuit 50' are each sampled by a shift pulse φ1'' and input to second registers 51a, 51b, and 51c. Similarly to the embodiment, the second register 52
After being transferred to a152b and 52c, the shift pulse φ
4'' is output to the color signal processing circuit 54'.The color signal processing circuit 54' performs known color signal processing such as γ conversion, masking processing, and under color removal, and outputs each print color of Y1M%C, BK. A signal is obtained and output to the head driver 59'.

The inkjet heads for each color (not shown) are Y, M, C%B.
Ink droplets of an amount corresponding to the K color signal voltage are ejected to form a color image on the recording paper corresponding to the reproduced video signal.

For example, the inkjet head is
A head such as that described in Japanese Patent No. 495 can be used. It should be noted that other recording devices such as a thermal transfer recording device, an electrophotographic recording device, etc. are also applicable in addition to an inkjet recording device.

8(a) and 8(b) are detailed circuit diagrams of the first and second analog shift registers of this embodiment, respectively.

In the figure, 90.90' is an analog switch, 9119
1' is inverter, 92.92' is OR gate, 2# 93.93' is buffer amplifier 1194.94' is COD
Line memory 95.95' is an amplifier.

Vref 1 s and Vref 2 are reference voltages and the respective signals SMPL.

When 5ET2 is "0", that is, when each shift register is not in the manual sampling period, unnecessary signals are prevented from being read into the CCDs 94 and 94'. Particularly, since the second analog register is sensitive to extreme level fluctuations due to the response characteristics of the filter, it is desirable that unnecessary portions of the CCDs 94 and 94' contain signals at a constant level. Although a COD is used as an analog shift register, other devices such as a BBD can also be applied. Further, although a shift register that shifts one stage with one pulse is used, it is of course possible to use a shift register with multi-phase drive such as two-phase or three-phase.

Furthermore, in the above embodiments, analog shift registers are used as both the first and second time axis conversion circuits;
It is also possible to use a digital shift register or a digital memory capable of both writing and reading for one or both of them. For example, as shown in FIG. 9, when digital signal 1 (jO) is input, the digital shift register 101 performs the first time axis conversion, and the output is converted to D/
, converted into an analog signal by the converter 102 and sent to the filter 10
3, and then performs second time axis conversion using the analog shift register 104. and if a digital signal is required as output, Ayi) converter 10
If an analog signal is required, the output of the register 104 can be used. In this way, the time axis conversion circuit can use both analog and digital memories depending on the format of the input and output signals. Furthermore, even when a digital memory is used in the first conversion circuit, by adding a digital filter, the
It is possible to perform weighted averaging as shown in (b).

As explained above, when the time axis conversion device of this embodiment is applied to a video printer, it is not only effective in keeping the speed ratio of the input side and the output side. The signal is read from the first shift register using a reference clock that is completely independent of the synchronization signal, so it is possible to compensate for fluctuations in the time base on the input side.
Since the input to the shift register is performed using the reference clock and the readout is performed using the synchronization signal on the output side, fluctuations in the time base on the output side can be compensated for. Since the input signal to the filter is based on time axis compensation, accurate filtering characteristics can be stably obtained1. Even if the frequency characteristics of the filter are constant, The frequency characteristics of the entire system can be changed according to the conversion of the time axis by the shift register. That is, the frequency characteristics of the filter can be made variable by changing the scale of the frequency axis by time jlJ axis transformation.

As shown in FIGS. 3(a) and 3(b), a filter configuration that takes the average of the time series signal can be easily created by using an analog shift register.

(Description of Effects) As explained above, the video signal recording device of the present invention not only allows one person to convert the time axis of the video signal and the output recording signal, but also allows the time axis conversion means to convert the time axis between the recording head and the recording medium. Since the converted video signal is output at a frequency that corresponds to the relative speed, it is possible to compensate for fluctuations in the time base on the recording device side. That is, even if there is a variation in relative velocity,
A high quality image can be obtained by keeping the interval between recording dots constant.

[Brief explanation of drawings]

FIG. 1 is a time axis conversion circuit diagram of the first embodiment of the present invention, FIG. 2 is a signal waveform diagram of each part of FIG. 1, and FIG.
Figure 6 [b] is a time axis conversion circuit diagram of the embodiment, Figure 6 [b] is another weighted average circuit diagram, and Figure 4 is a block diagram when the time axis conversion circuits of Figures 1 and 6 are applied to a video printer. , Fig. 5 is a detailed circuit diagram of the shift pulse generator shown in Fig. 4, Fig. 6 is a signal waveform diagram of each part of Figs. 4 and 5, Fig. 7 is a block diagram of the color video printer, and Fig. 8 (a) and Φ) are for 1. FIG. 9, a detailed circuit diagram of the second analog shift register, is a time axis conversion circuit diagram using a digital memory. Applicant: Canon Co., Ltd.

Claims (1)

[Claims] (1) Time axis conversion means for time axis conversion of an input video signal, a recording head for recording the output of the conversion means on a recording medium, and speed detection for generating a speed signal according to the relative speed of the recording head with respect to the recording medium. A video signal recording device comprising: means for converting, the converting means outputting a video signal to be converted at a frequency corresponding to the speed signal. (2. In Claim 1, the time axis conversion means includes a first time axis conversion circuit that converts the time axis of the input video signal, and a filter that filters the output of the first time axis conversion circuit. and a second time-base conversion circuit for time-base converting the output of the filter, and the second time-base conversion circuit outputs a video signal to be converted at a frequency corresponding to the speed signal. Signal Recording Apparatus. ('5) The video signal recording apparatus according to claim 2, wherein the first reading time interval and the sampling interval of the second time axis conversion circuit are constant.