JPS59178049A - Data transfer control system - Google Patents
Data transfer control systemInfo
- Publication number
- JPS59178049A JPS59178049A JP58051879A JP5187983A JPS59178049A JP S59178049 A JPS59178049 A JP S59178049A JP 58051879 A JP58051879 A JP 58051879A JP 5187983 A JP5187983 A JP 5187983A JP S59178049 A JPS59178049 A JP S59178049A
- Authority
- JP
- Japan
- Prior art keywords
- data
- length
- packet
- receiving
- computer
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F15/00—Digital computers in general; Data processing equipment in general
- G06F15/16—Combinations of two or more digital computers each having at least an arithmetic unit, a program unit and a register, e.g. for a simultaneous processing of several programs
- G06F15/163—Interprocessor communication
- G06F15/17—Interprocessor communication using an input/output type connection, e.g. channel, I/O port
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/14—Handling requests for interconnection or transfer
- G06F13/20—Handling requests for interconnection or transfer for access to input/output bus
- G06F13/28—Handling requests for interconnection or transfer for access to input/output bus using burst mode transfer, e.g. direct memory access DMA, cycle steal
Landscapes
- Engineering & Computer Science (AREA)
- Theoretical Computer Science (AREA)
- Physics & Mathematics (AREA)
- General Engineering & Computer Science (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Software Systems (AREA)
- Computer And Data Communications (AREA)
- Data Exchanges In Wide-Area Networks (AREA)
- Communication Control (AREA)
Abstract
Description
【発明の詳細な説明】
（１）発明の技術分野
本発明は計算機間のデータ転送方式に係ｐ１特にデータ
パケット転送に先立ち、受信側計算機にデータパケット
の長さに関する情報を知らせることによシ受信側のバッ
ファメモリを有効に使用する方式に関する。Detailed Description of the Invention (1) Technical Field of the Invention The present invention relates to a data transfer method between computers. This invention relates to a method for effectively using buffer memory on the receiving side.
（２）従来技術と問題点
従来、計算ｍＡから計算機Ｂヘデータバケツ）を送る場
合、受信側計算機で受信準備を行なう際データパケット
長に関する情報を送信側計算機から送らないため、予Ｍ
し得る最長のバッファメモリを準備しなければならなか
った。この為バッファメモリの有効利用が図れたいとい
う欠点がおった。(2) Conventional technology and problems Conventionally, when sending a data bucket from calculation mA to computer B, when the receiving computer prepares for reception, the sending computer does not send information regarding the data packet length, so the pre-M
I had to prepare the longest possible buffer memory. For this reason, there is a drawback that it is desirable to make effective use of the buffer memory.
（３）発明の目的
本発明は゛前記欠点を解消して、送信側計算機からパケ
ットデータを送信するに先だって該パケットデータ長を
受信側計算機に送ることにより、受信側計算機は該デー
タパケット長に適合したバッファメモリを準備すること
によシバソファメモリの有効利用を図るデータ転送方式
を提供することを目的とする。(3) Purpose of the Invention The present invention solves the above-mentioned drawbacks, and by sending the packet data length to the receiving computer before transmitting the packet data from the sending computer, the receiving computer adapts to the data packet length. The purpose of the present invention is to provide a data transfer method that makes effective use of the buffer memory by preparing a buffer memory.
測針算機にパケットデータを転送するシステムにおいて
、該送信側計算機に送信するバクットデータ長に関する
情報を、パケットデータに先立って送信する手段を設け
るとともに該受信側計算機に該パ）ｒットテーク長に関
する情報を検出する手段を設け、該パケットデータ長に
達合した受信データバッファを準伽させることを特忙と
するデータ転送制御方式により達成される。In a system for transmitting packet data to a point-finding computer, a means is provided for transmitting information regarding the length of backt data to be transmitted to the sending computer prior to the packet data, and information regarding the length of the packet to the receiving computer is provided. This is achieved by a data transfer control method that includes a means for detecting the packet data length, and whose main function is to make the received data buffer ready when the packet data length has been reached.
（５）発明の実施例 以下図面を参照しつつ本発明を訂糺に駁１明する。(5) Examples of the invention The present invention will be explained in more detail below with reference to the drawings.
図は本発明の一実施例を示すシステム相４氏図である。The figure is a system phase 4 diagram showing one embodiment of the present invention.
図において、１１は計シ、Ｉ桜Ａ、１２ｉ主処刑装散Ａ
１１３はメモリＡ１１４けテークバスＡ１１５Ｂ１１１
０け主処理装ｊｉｉ：Ｂ、１１１はテークバスＢ１１１
２は信号検出部Ｂ、１１３はメモリＢ、 １１４けパケ
ット制御部Ｂ、１１５は信号発生部Ｂ、１１６は選択回
路Ｂ、１１７はパケット網である。In the figure, 11 is a plan, I Sakura A, 12i Main Execution Suit A
113 is memory A114 and take bus A115B111
0 main processing unit jii: B, 111 is take bus B111
2 is a signal detection section B, 113 is a memory B, 114 packet control sections B, 115 is a signal generation section B, 116 is a selection circuit B, and 117 is a packet network.
計３！４＃ｌｉ１からパケット交換網を介して計算ｉＢ
１．９にデータを送信する場合について説明する。送イ
ＬデータＣ１メモリＡ１３に格納されておシ、主処理装
ｇｆ： Ａ １２は送信するパケットデータ長を決めて
、該パケットデータ長を信号発生部Ａ１５に送る。該信
号発生部Ａ１５は、該データパケットの長さに関する情
報を付加した受信要求信号を生成する。次に鷺択回路Ａ
１６け、前記パケットデータ長を付加した受信要求信号
をパケット網を経由して割算機Ｂ１９のイ言号杉）出部
Ｂ１１２へ通る。該信号検出部Ｂ１１２は受信要求信号
を検出し、データパケット長に関する情宰［ｔを抽出し
、主処理装σ７Ｂ１１０に該データパケット長の情報を
送る。該処理装置ＢＩＩＯ−メモリＢ１１３の受信デー
タバッファ長を、前記データパケット長に連合させる。Total 3!4 iB calculated from #li1 via packet switching network
1.9, the case of transmitting data will be explained. The main processing unit GF:A12 determines the packet data length to be transmitted, and sends the packet data length to the signal generator A15. The signal generator A15 generates a reception request signal to which information regarding the length of the data packet is added. Next, heron selection circuit A
16, the reception request signal to which the packet data length has been added is passed through the packet network to the output section B112 of the divider B19. The signal detection unit B112 detects the reception request signal, extracts information [t regarding the data packet length, and sends the information on the data packet length to the main processing unit σ7B110. The reception data buffer length of the processing unit BIIO-memory B113 is associated with the data packet length.
一方、該佃号桔出部Ｂ１１２は受年準仏児了仏刊をパケ
ット交換網１１７を経由してパケット制御部Ａに該受信
瞠ダ１〕完了偏号を迭る。該受悄準備完了化号を受けと
ると割算機Ａ １１のメモリＡ１３から主処理装置Ａ１
２はデータを取シ出しパケット制御部１７に送る。該パ
クッ制御部１７は該送られたテークを井に公知形式のパ
ケットデータを渭ｉ成Ｌ、選択回路Ａ１６紗由で計獅機
Ｂ１９にパケットテークを送る。計↑＞枦Ｂ１−１、前
記受信データバンファを使って該送部されたデータを利
用したり、メモ’） Ｂ １１３に格納したシする。On the other hand, the postal address sending section B112 sends the receiving order number 1 to the packet control section A via the packet switching network 117. When the readiness completion signal is received, the main processing unit A1 is transferred from the memory A13 of the divider A11 to the main processing unit A1.
2 extracts the data and sends it to the packet control section 17. The packet control unit 17 sends packet data in a known format to the sender B19 through the selection circuit A16 and the sender B19. ↑> B1-1, the received data buffer is used to utilize the transmitted data or to store it in the memo') B113.
以上の説明では計γ根を２台として説明したが、本発明
の方式り計算イχ、が何台になっても全く同様に集施で
きる。In the above explanation, the total number of γ roots is two, but the method of the present invention can be calculated in exactly the same way no matter how many units χ.
（６）発明の効呆
以上良１を明したように、本発明によれはパケノ）デー
タ長を、受信側計算機に、送信に先立って通知できるの
で、受信側計算機で（はバッファメモリ〃資源の有効オ
リ用が図れる。(6) Effects of the Invention As stated above, the present invention allows the receiving computer to be notified of the data length prior to transmission. It is possible to aim for effective use.
図は本発明の一実施例を示すシステム構成図である。
記号の説明、１１は計算板Ａ１１２は主処理装ｖｌ
１ ］−ｊニア＋、モリＡ１１４はデータ／＜スＡ、１
５１３．１１０は主処理装置Ｂ、１１１はデータノくス
Ｂ１１１２は信号検出部Ｂ１１１３はメモリＢ、１１４
はパケ７）制御部Ｂ、１．１５は信号発生部Ｂ 、 １
１６は選択回路Ｂ、１１７けパケ、７ ）網。
Ｂ−：’： ”’、：’−＋ｉ
代理人 弁理士 松 −宏四部 ：
１、−□−ノThe figure is a system configuration diagram showing an embodiment of the present invention. Explanation of symbols: 11 is the calculation board A112 is the main processing unit vl
1]-j near+, Mori A114 is data/<s A, 1
513.110 is the main processing unit B, 111 is the data node B1112 is the signal detection unit B1113 is the memory B, 114
7) Control section B, 1.15 signal generation section B, 1
16 is a selection circuit B, 117 is a package, and 7) a network. B-:': ”',:'-+i Agent Patent attorney Matsu - Koshibu: 1, -□-ノ
Claims (1)
にパケットデータを転送するシステムにおいて、該送信
側計算機に、送信するパケットデータ長に関する情報を
、パケットデータに先立って送信する手段を設けるとと
もに、該受送ｉ１１＋ Ｈ算機に該パケットデータ長に
関する情報を検出する手段を設け、該パケットデータ長
に適合した受信デー・タバッファを準備させることを％
ｅｉとするデータ転送制御方式。In a system that transfers packet data from a sending computer to a receiving computer via a packet switching network, the sending computer is provided with means for transmitting information regarding the length of the packet data to be transmitted prior to the packet data; It is recommended that the receiving/transmitting i11+H computer be provided with means for detecting information regarding the packet data length and preparing a receiving data buffer that is compatible with the packet data length.
Data transfer control method with ei.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP58051879A JPS59178049A (en) | 1983-03-28 | 1983-03-28 | Data transfer control system |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP58051879A JPS59178049A (en) | 1983-03-28 | 1983-03-28 | Data transfer control system |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS59178049A true JPS59178049A (en) | 1984-10-09 |
Family
ID=12899163
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP58051879A Pending JPS59178049A (en) | 1983-03-28 | 1983-03-28 | Data transfer control system |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS59178049A (en) |
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO1992006430A1 (en) * | 1990-09-28 | 1992-04-16 | Fujitsu Limited | Message control system in a data communication system |
| WO1992006435A1 (en) * | 1990-09-28 | 1992-04-16 | Fujitsu Limited | Message control system in a data communication system |
| JP2512847B2 (en) * | 1990-09-28 | 1996-07-03 | 富士通株式会社 | Message control method for data communication system |
| JP2512848B2 (en) * | 1990-09-28 | 1996-07-03 | 富士通株式会社 | Message control method for data communication system |
-
1983
- 1983-03-28 JP JP58051879A patent/JPS59178049A/en active Pending
Cited By (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO1992006430A1 (en) * | 1990-09-28 | 1992-04-16 | Fujitsu Limited | Message control system in a data communication system |
| WO1992006435A1 (en) * | 1990-09-28 | 1992-04-16 | Fujitsu Limited | Message control system in a data communication system |
| JP2512847B2 (en) * | 1990-09-28 | 1996-07-03 | 富士通株式会社 | Message control method for data communication system |
| JP2512848B2 (en) * | 1990-09-28 | 1996-07-03 | 富士通株式会社 | Message control method for data communication system |
| US5592624A (en) * | 1990-09-28 | 1997-01-07 | Fujitsu Limited | Data communication for controlling message transmission and reception among processing modules using information stored in descriptor to form a loosely coupled multiprocessing system |
| US5727151A (en) * | 1990-09-28 | 1998-03-10 | Fujitsu Limited | Message control system specifying message storage buffer for data communication system with general purpose and arbitrary form buffers |
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